JPH0232102U - - Google Patents

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Publication number
JPH0232102U
JPH0232102U JP10813488U JP10813488U JPH0232102U JP H0232102 U JPH0232102 U JP H0232102U JP 10813488 U JP10813488 U JP 10813488U JP 10813488 U JP10813488 U JP 10813488U JP H0232102 U JPH0232102 U JP H0232102U
Authority
JP
Japan
Prior art keywords
set value
outputs
manipulated variable
status signal
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10813488U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP10813488U priority Critical patent/JPH0232102U/ja
Publication of JPH0232102U publication Critical patent/JPH0232102U/ja
Pending legal-status Critical Current

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Description

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本考案に係る調節計の一実施例を示す
ブロツク図、第2図はその動作を説明するための
図、第3図は他の実施例を示すブロツク図、第4
図は従来の調節計のブロツク図、第5図、第6図
はその動作を説明するための図である。 1……設定値出力部、2,3……操作量演算部
、10……遅延部。
FIG. 1 is a block diagram showing one embodiment of the controller according to the present invention, FIG. 2 is a diagram for explaining its operation, FIG. 3 is a block diagram showing another embodiment, and FIG.
The figure is a block diagram of a conventional controller, and FIGS. 5 and 6 are diagrams for explaining its operation. 1... Set value output section, 2, 3... Manipulated amount calculation section, 10... Delay section.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] あらかじめ設定されたプログラムに基づいて求
められた設定値及び前記プログラムに基づく制御
を行うことを示すステータス信号を出力する設定
値出力部と、このステータス信号が入力されこの
信号を遅延させる遅延部と、前記設定値出力部と
離隔して配置され前記設定値と前記遅延部の出力
及びプロセス量が入力されこれらの値から操作量
を演算して出力する操作量演算部とを有すること
を特徴とする調節計。
a set value output section that outputs a set value determined based on a preset program and a status signal indicating that control is to be performed based on the program; a delay section that receives this status signal and delays this signal; The device is characterized by comprising a manipulated variable calculation unit arranged separately from the set value output unit, into which the set value, the output of the delay unit, and the process amount are input, and calculates and outputs a manipulated variable from these values. Controller.
JP10813488U 1988-08-17 1988-08-17 Pending JPH0232102U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10813488U JPH0232102U (en) 1988-08-17 1988-08-17

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10813488U JPH0232102U (en) 1988-08-17 1988-08-17

Publications (1)

Publication Number Publication Date
JPH0232102U true JPH0232102U (en) 1990-02-28

Family

ID=31343181

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10813488U Pending JPH0232102U (en) 1988-08-17 1988-08-17

Country Status (1)

Country Link
JP (1) JPH0232102U (en)

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