JPH023178A - Memory device - Google Patents

Abstract

PURPOSE:To hardly receive the influence of noise by providing two signal lines between the output of a sense amplifying circuit and the input of a circuit in a rear step and causing an output buffer circuit in the rear step to hardly sense the in-phase signal component of the two signal lines. CONSTITUTION:An output signal from output terminals 40 and 40' of a sense amplifier is amplified by inverter circuits 57 and 58 and transmitted to an output buffer circuit 34. When the voltage of an input terminal 24 in the sense amplifier goes to be a higher level than the voltage of an input terminal 25, the continuity degree of an MOST35 is increased. Then, since the continuity degree of an MOST35' is decreased, the output terminals 40 and 40' are almost simultaneously changed toward L and H respectively. Since the output terminals 40 and 40' are transmitted through two signal lines L1 and L2 to the inputs of the circuits 57 and 58, the outputs of the circuits 57 and 58 are almost simultaneously changed to the H and L respectively. Accordingly when the inversion WE.CS of an output control signal is H, the outputs of inverter circuits 49 and 50 go to the L and H respectively and the output signal of a grounding level appears in an output level 53.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a memory device such as a static MOS memory device.

[Conventional technology]

FIG. 1 shows an example of a conventional static type MOS memory device, and is a block diagram of its main parts.

In FIG. 1, 1.2 is a memory cell group (memory plane), and its unit circuit (memory cell) 3 is 4.5.6
．． It consists of four MOS transistors of 7.7 mm (hereinafter abbreviated as MO5T) and a resistor of 8.9 mm. This memory cell is accessed by the decoder 12 that drives the word line 10.11, and the output signal appears as a minute potential difference on the data line 13.14, and appears as common data 17.1g through the MO8T for switch 15.16. This common data line 17
．． Since the drains of all the switches MO8T are connected to 18, the parasitic capacitance becomes large, which hinders high-speed operation of the memory device. For this reason, this common data line is usually divided into a plurality of pieces using MO5T to improve performance. In FIG. 1, as an example, two parts are shown. The above-mentioned minute signal is selected by turning on either MO5T 19, 20 or 21.22 (7), and is connected to the input terminal 24.2 of the sense amplifier 23.
5. 26.27 and 28.29.30.3
MO8T 1 is a load for keeping the data line 13.14 and the common data line 17.18.32.33 at a predetermined potential. Note that 34 is an output buffer circuit.

In the memory device having the above configuration, the common data line 17.
Conventionally, a circuit shown in FIG. 2 has been used as the sense amplifier 23 and the output buffer circuit 34 for amplifying a minute signal of 1g, 32.33. In the figure, 24 and 25 are input terminals of the sense amplifier 23, into which signals from the common data line (17, 18, 32, and 33 in FIG. 1) are input. 3
5.36 is a pair of differentially connected N-type MO3Ts (hereinafter abbreviated as NMO8T) that receives the minute differential potential of the input terminals 24.25, and 37.38 is a P-type MO5T (hereinafter referred to as PMO8T).
(abbreviated as 5T) serves as a load (load element).

The gate and drain of PMO5T38 are commonly connected, and P
MO5T37.38 operates as a constant current source. That is, PMO3T37.38 operates as a load for the drains of NMO535 and 36.

Now, input terminals 24 and 25 each have V. eV, Vc
c It is assumed that a potential of Vth-ΔV is applied.

However, Vcc: power supply voltage, Vth: for example, NMO in Fig. 1
Threshold voltage of 3T36, ΔV: A minute potential difference (the same applies below) that occurs when a memory cell is accessed. At that time, node 39 moves to a high potential, and PMO
The current flowing through the 5T37 is reduced, and the potential at the node (output terminal of the sense amplifier) 40 is further lowered. NMO3
T41 is a switch that is activated only when its gate terminal 42 is brought to a high potential by the activation control pulse signal. In this way, a signal is output to the output terminal 40 of the sense amplifier, which signal is further amplified by the inverter circuits 43 and 44 and transmitted to the output buffer circuit 34.

The output buffer circuit 34 includes output transistors 45, 46,
Signal WE created by write signal and chip select signal
- A signal 51 consisting of a logic section 47.48 controlled by C8 and an inverter circuit 49.50, and an output signal of the sense amplifier 23 is obtained via the inverter circuit 43;
Furthermore, two signals, a signal 52 obtained via the inverter circuit 44, are input. Note that 53 is an output terminal of the output buffer circuit 34.

[Problem to be solved by the invention]

However, as a result of studies conducted by the present inventors, it has been found that the conventional memory device equipped with the sense amplifier and output buffer circuit configured as described above has various problems as described below. Namely.

■The output of the sense amplifier 23 is covered by the output sofa circuit 3 in the subsequent stage.
Since there is only one signal output line between the input of the inverter circuit 43 of the switch MO8T41 and the input of the inverter circuit 43 of the switch noise, etc.) is likely to be induced, and in response to this noise, the output MO5T of the output buffer circuit 34
One of 45 and 46 becomes conductive and a noise component is generated at the output terminal 53.

■Since only one output line comes out from the sense amplifier 23, two input signals 51.5 to the output buffer circuit 34
2 must be created via an inverter circuit.

■A delay inevitably occurs between the two input signals 51 and 52,
In order to align the phase of the input signal 54.55 to the output transistor 45.46 and reduce the through current consumed in said output transistor 45.46, the logic section 47.4
8 and inverter circuits 49 and 50, making the circuit design complicated.

■ Due to the necessity of matching the phases of the input signals 54 and 55 of the output transistor, the signal 52 is inevitably slower than the signal 51.
The total delay time is determined by

Therefore, an object of the present invention is to solve the above-mentioned problems and provide a memory device that is less susceptible to noise and operates at high speed.

[Means to solve the problem]

In order to achieve the above object, the memory device of the present invention replaces the amplifier circuit section of the sense amplifier with a conventional amplifier circuit (shown surrounded by broken lines in FIG. 2) that receives minute differential potentials between two input terminals. 2 sets of 56 are used, and between the output of these two amplifier circuits and the input of the output cover sofa circuit in the latter stage
Two signal lines are arranged, and two output transistors of a subsequent output buffer are made to respond to two amplified signals of the same phase and opposite phase obtained on these two signal lines.

[Effect]

If noise is induced in one of the two signal lines placed between the output of the two amplifier circuits and the input of the subsequent circuit,
Noise in phase with this noise is also induced on the other side. but,
Although the output buffer circuit in the latter stage responds to the difference signal component between the two signal lines, the circuit configuration is difficult to respond to the in-phase signal component of these two signal lines. It becomes possible to reduce noise components at the output terminal.

Moreover, the phases of two amplified signals of opposite phases can be used to shift the inputs of the two output transistors 45 and 46 of the output buffer circuit 34 in the subsequent stage without using the conventional inverter circuit 44 for logic inversion shown in FIG. As a result, through current is reduced and high-speed memory operation is realized.

〔Example〕

The present invention will be explained in detail below using examples.

FIG. 3 is a schematic diagram showing a configuration example of a sense amplifier and an output buffer circuit used in the memory device of the present invention.

In FIG. 3, the same reference numerals and symbols as those described above indicate the same or equivalent parts, and the explanation will be omitted as appropriate. Further, 35.36 and 35'36' are a pair of NMO5Ts that receive minute differential potentials read from the memory cells, respectively, and 37.38 and 37',
38' is a PMoST serving as a load.

That is, two sets of portions 56 surrounded by broken lines in FIG. 2 are symmetrically connected. Both PMO3T38 and 38' have P
Since MO5T3g, 38', 37.37' operates as a constant current source, high-speed switching can be performed. Also, P M OS T38.38'37.3
7'(7)"/-Sni connected NMO5T41 is
This is a switch that puts the sense amplifier into operation only when a high level ("1") control pulse signal is supplied to its gate terminal 42. The sense amplifier with the above configuration is 2
It has two output terminals 40 and 40', and the output signals therefrom are guided to inverter circuits 57 and 58 provided in parallel, amplified, and transmitted to the output sofa circuit 34.

When the voltage at the input terminal 24 of the sense amplifier becomes higher than the voltage at the input terminal 25, the conductivity of MO8T35 increases and the conductivity of MO3T35' decreases, so that at about the same time the sense amplifier output terminals 40 and 40' respectively Low level, changes towards high level.

This output terminal 40.40' is transmitted to the input of the inverter circuit 57.58 via the two signal lines L1 and L2, so the output of the inverter circuit 57.58 goes to high level and low level almost simultaneously. Change.

Therefore, when the output control signal WE-C5 is at a high level,
The outputs of the NAND gate circuits 47 and 48 change to high level and low level almost simultaneously, and the outputs of the inverter circuit 49
．． The outputs 54 and 55 of 50 also change to low level and high level, respectively, almost simultaneously. Thus, the output MOST45.
46 become non-conductive and conductive at the same time, respectively, and an output signal at approximately the ground level appears at the output terminal 53.

On the other hand, if the voltage relationship at the input terminals 24, 25 of the sense amplifier is opposite to the above, an output signal at approximately the level of the power supply voltage Vcc appears at the output terminal 53, contrary to the above.

As explained above, in the embodiment shown in FIG. 3, the inputs of the two output transistors 45 and 46 of the output buffer circuit 34 in the subsequent stage are driven without using the conventional inverter circuit 44 for logic inversion shown in FIG. Since the phases of the two amplified signals of opposite phases are aligned, the through current is reduced and high-speed memory operation is realized.

In addition, in one embodiment, NMO8T35.36.3
5', 36' drain load PMO3T3
7°38.37', 38' rapidly charge the output terminal 40.40' in response to the difference signal of the input terminal 24.25;
On the other hand, in response to this input terminal 24.25 difference signal, the NMO
Since 5T35, 36, 35' and 36' discharge their outputs at high speed, high-speed memory operation is realized.

Furthermore, in this embodiment, two signal lines L1, L2
Even if in-phase noise is induced, the gates of the output MO5T45 and 46 of the output buffer circuit in the subsequent stage are controlled in-phase in response to this noise, and the degree of conductivity changes in the same way, so that it is transmitted to the output terminal 53. It is possible to significantly reduce the noise components caused by noise.

Furthermore, the monolithic integrated circuit constituting the circuit of the embodiment shown in FIG. 3 has the advantage that it is easy to obtain a DC balance between the two outputs 40 and 40'.

In the embodiment shown in FIG. 3, two differential pair connections N
Since the source of MOS T35.36.35', 36' is connected to the switch means consisting only of MO8T41, the source of NMO8T35.36 and the NMOS
Compared to the case where separate switch means are provided for the sources of T35' and 36', this has the advantage of not only reducing the number of circuit elements but also making it easier to obtain DC balance between the two outputs 40 and 40'. .

The present invention is not limited to the above embodiments.

Various alternative embodiments can be adopted.

For example, in order to prevent an increase in delay time due to parasitic noise on the common data line, a method is proposed in which multiple sense amplifiers are used depending on the division of the common data line, and only one of them is activated to extract the output signal. In that case, the inverter circuit shown in FIG.
Just replace it with the selection logic part.

〔Effect of the invention〕

As explained above, according to the present invention, even if in-phase noise is induced in the two signal lines arranged between the outputs of the two amplifier circuits of the sense amplifier and the input of the subsequent circuit, , since the subsequent circuit has a circuit configuration that is difficult to be sensitive to the in-phase signal components of the two signal lines, it is possible to reduce the noise component at the output terminal of the subsequent circuit, and the output vanofer circuit of the subsequent stage can be reduced. Since the phases of the opposite phase amplified signals for driving the two output transistors are aligned, the penetration 1
! The memory flow is reduced and faster memory operation is achieved.

[Brief explanation of the drawing]

FIG. 1 is a main part configuration diagram showing an example of a conventional memory device, FIG. 2 is a circuit diagram showing an example of the configuration of a conventional sense amplifier section and an output buffer circuit section, and FIG. 3 is a circuit diagram showing an example of the configuration of a conventional sense amplifier section and an output buffer circuit section. FIG. 3 is a circuit diagram showing an example of the configuration of an output buffer circuit section. Explanation of symbols> 1.2...Memory cell group (memory plane) 3...
Unit circuit (memory cell) 12...Decoder 17.18.32.33...Common data line 23...
・Sense amplifier 24.25...Sense amplifier input terminal 34.34.
... Output buffer circuit 35, 36, 35', 36'... Elements 37, 38, 37', 3g' forming a differential pair... Load element 40, 40'... Sense amplifier Output terminal 56
...Amplification circuit

Claims (1)

[Claims] 1. A memory device comprising a memory cell and a sense amplifier for amplifying a signal read from the memory cell, wherein the sense amplifier includes a first, a second, and a third sense amplifier. , a fourth transistor, and fifth, sixth, seventh, and eighth transistors having conductivity types opposite to those of the first, second, third, and fourth transistors; , the sources of the third and fourth transistors are connected to the first operating potential point, and the sources of the fifth, sixth, seventh,
The source of the eighth transistor is connected to a second operating potential point, the drain of the first transistor and the drain of the fifth transistor are connected, and the drain of the second transistor and the drain of the sixth transistor are connected. the drain of the third transistor and the drain of the seventh transistor are connected, the drain of the fourth transistor and the drain of the eighth transistor are connected, and the drain of the sixth transistor is connected. The gate and drain of the transistor are connected, the gate and drain of the seventh transistor are connected, the gate of the first transistor and the gate of the third transistor are connected, and the gate of the second transistor is connected. The gate is connected to the gate of the fourth transistor, and is configured to obtain a first amplified signal from the drain of the first transistor and obtain a second amplified signal from the drain of the fourth transistor, The first amplified signal and the second amplified signal of the sense amplifier are transmitted to a first input and a second input of a subsequent stage circuit via a first signal line and a second signal line, respectively. The circuit includes ninth and tenth transistors connected in series between the first operating potential point and the second operating potential point, and the first input of the subsequent circuit and the ninth transistor. By setting the number of logic circuits connected between the control input and the number of logic circuits connected between the second input of the subsequent circuit and the control input of the tenth transistor to be equal, A memory device characterized in that the control inputs of the ninth and tenth transistors are driven by mutually opposite complementary signals having substantially no phase difference. 2. A patent claim characterized in that a switch means controlled by a control signal is connected between the sources of the first, second, third, and fourth transistors and the first operating potential point. The memory device according to item 1. 3. A patent characterized in that the switch means is constituted by an eleventh transistor, and the operating current flowing through the first to eighth transistors is substantially set only by the current flowing through the eleventh transistor. A memory device according to claim 2. 4. The subsequent circuit has high sensitivity to the difference signal component between the first input and the second input, and has low sensitivity to the in-phase signal component between the first input and the second input. Claims 1 to 3 are characterized in that they are circuits.
The memory device according to any of paragraphs. 5. The memory device according to claim 4, wherein the subsequent circuit is an output buffer circuit. 6. A signal read from the memory cell via a common data line transmitting a read signal from the accessed memory cell is transmitted to the gates of the first and third transistors of the sense amplifier and the second and second transistors of the sense amplifier. 6. The memory device according to claim 1, wherein the memory device is transmitted to the gate of a transistor No. 4. 7. In a memory device comprising a memory cell and a sense amplifier for amplifying a signal read from the memory cell, the sense amplifier includes first, second, third, and fourth transistors. , comprising fifth, sixth, seventh, and eighth transistors of opposite conductivity types to the first, second, third, and fourth transistors; The sources of the transistors are connected to the first operating potential point, and the sources of the fifth, sixth, seventh, and
The source of the eighth transistor is connected to a second operating potential point, the gate of the first transistor and the gate of the third transistor are connected, and the gate of the second transistor and the gate of the fourth transistor are connected. A voltage responsive to the drain current of the second transistor is generated between the source and drain of the sixth transistor, and a voltage is generated between the source and drain of the sixth transistor. By applying the voltage between the source and gate of the fifth transistor, a current flowing to the drain of the fifth transistor is set;
A voltage responsive to the drain current of the third transistor is generated between the source and drain of the seventh transistor, and the voltage generated between the source and drain of the seventh transistor is applied to the eighth transistor. The current flowing through the drain of the eighth transistor is set by applying between the source and gate of the transistor, and the difference current between the current flowing through the drain of the first transistor and the current flowing through the drain of the fifth transistor. 1st by
the first amplification signal of the sense amplifier; Signal and the second above
The amplified signal is transmitted to a first input and a second input of a subsequent stage circuit via a first signal line and a second signal line, respectively, and the latter circuit operates at the first operating potential point and the second operating potential point. a ninth and a tenth transistor connected in series between the potential point and the number of logic circuits connected between the first input of the subsequent circuit and the control input of the ninth transistor; By setting the number of logic circuits connected between the second input of the subsequent circuit and the control input of the tenth transistor to be equal, the control input of the ninth and tenth transistors can be effectively controlled. A memory device characterized in that it is driven by complementary signals having mutually opposite phases and having no phase difference. 8. Claim 7, characterized in that the gate and drain of the sixth transistor are connected, and the gate and drain of the seventh transistor are connected.
Memory device as described in section. 9. A patent claim characterized in that a switch means controlled by a control signal is connected between the sources of the first, second, third, and fourth transistors and the first operating potential point. The memory device according to item 8. 10. A patent characterized in that the switch means is constituted by an eleventh transistor, and the operating current flowing through the first to eighth transistors is substantially set only by the current flowing through the eleventh transistor. A memory device according to claim 9. 11. The subsequent circuit has high sensitivity to the difference signal component between the first input and the second input, and has low sensitivity to the in-phase signal component between the first input and the second input. 11. The memory device according to claim 7, wherein the memory device is a circuit. 12. The memory device according to claim 11, wherein the subsequent circuit is an output buffer circuit. 13. A signal read from the memory cell via a common data line transmitting a read signal from the accessed memory cell is transmitted to the gates of the first and third transistors of the sense amplifier and the second and second transistors of the sense amplifier. 13. The memory device according to claim 7, wherein the memory device is transmitted to the gate of a transistor No. 4.