JPH0231586A - Digital video processor - Google Patents

Abstract

PURPOSE:To reduce the capacity of a picture memory by writing the digital data of input video signals during a picture effective period except the vertical and horizontal blanking periods and the one-bit data of burst phase information outputted from a detecting section in the picture memory. CONSTITUTION:The digital data of the picture effective period of one-field composite color input video signals and one-bit data of burst phase information outputted from a burst phase detecting section 11 are written in a digital picture memory 10. Moreover, when the picture memory 10 is read out, composite color output video signals are formed by synthesizing the digital data read out of the memory 10 with burst signals formed by a burst signal generating section 15 based on the output signal of a D/A converting section 18 converted into analog signals, composite synchronizing signals formed by a synchronizing signal generating section 14, and the one-bit data of the burst phase information read out of the memory 10. Therefore, the capacity of the picture memory required for storing one field quantity of pictures can be reduced.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention controls the writing and reading of one field of composite color video signals into and from a digital image memory, and generates an image based on the digital data read from the image memory. The present invention relates to a digital video processing device that reproduces and forms a processed composite color video signal.

[Conventional technology]

To perform image processing on composite color video signals obtained by conventional reception, tape playback, etc., and reproduce and form composite color video signals of various special aspects such as still images, strobe images, picture-in-picture images, or scan conversion surfaces. Some video equipment, such as television receivers, video tape recorders, etc., are equipped with a digital video processing device having a rewritable digital image memory called a digital field memory.

The conventional digital video processing device of a television receiver with a still image processing function is configured with an Eζ groove as shown in FIG. The signal is processed by the signal processing section (
After being subjected to various analog processing such as filter processing and clamp processing in step 2), the data is input to an analog/digital converter (hereinafter referred to as A/D converter) (3) and converted into digital data.

Then, digital data of one field's worth of input video signals outputted from the converter (3) is written into the digital image memory (4).

Furthermore, the digital data written in the memory (4) is read out repeatedly and the digital/analog converter (hereinafter referred to as D/
(referred to as A conversion section) (5), the digital data is converted into analog by the conversion section (5), and then stored in the memory (4).
A composite color output video signal of a static image is reproduced based on one minute of digital data written in the image.

Then, the output video signal of the converter (5) is a video amplification fraud! (6) is output from the output terminal (7), and the still image is reproduced.

By the way, the sampling frequency of the converter (3) when digitally converting the input video signal should theoretically be at least twice the highest frequency of the input video signal, and usually the color subcarrier frequency (color printing carrier frequency)
The frequency is set to 3 or 4 times the fsc.

Then, the conversion unit (3) # (4) conversion and memory (
In order to control the writing and reading of 4), the synchronizing signal separated and extracted from the input video signal by the processing unit (2) is input to the pulse generation circuit unit (8). Generation circuit section (8) synchronized with
Based on the 3fsc or 4fsc timing pulse, the memory control unit (9) controls the conversion of the conversion unit (3) and the writing of the memo J (4), and when reading from the memory (4), synchronization formation or free-running oscillation formation is performed. Based on the 3fsc or 4fsc timing pulse generated by the generation circuit unit (8), the memory (4) is controlled by the control unit (9).
reading and conversion by the conversion unit (5) are controlled.

By the way, in the case of an input video signal of the NTSC system, based on the standard, one frame of 1/30 seconds formed by two consecutive odd and even fields consists of 525 horizontal lines, and the above-mentioned color subcarrier frequency fsc is 8,579545MHz ii:.

In the case of Figure @13, all the digital data of the input video signal for 1 field is written to the memory (4), so if the sampling frequency of the converter (3) is 3fsc, the request is made to the memory (4). The processing speed (cycle time) is 1/(3579545X8) 93.1nSeC
become.

Furthermore, if the number of quantization bits of digital data is 8 bits, there is a relationship of fs = (455Xfn)/2 (fn is horizontal scanning frequency), so the required capacity of memory (4) is used as image memory for processing. High-speed, large-capacity digital memory is required.

It is desired to reduce the capacity of digital image memory, for example, Japanese Patent Laid-Open No. 61-84981 (HO
4N 7101) states that the digital data of one field of input video signals excluding the vertical blanking period portion is written in a storage device as a digital image memory, thereby reducing the capacity of the image memory. has been done.

[Problem to be solved by the invention]

If data during the vertical retrace period is not written as described in the above publication, the number of horizontal lines written to the digital image memory decreases to 490, which is +490.
455 Image memory capacity, =-x x 3 x 8 =
That's 1337700 bits.

In this case, the memory capacity is reduced to only about 93.4% based on the difference in the number of horizontal lines written, compared to the capacity required when writing all the digital data for one field.

Therefore, in this type of digital video processing device, l
It would be desirable to further significantly reduce the capacity of digital image memory for storing one field minute of images.

SUMMARY OF THE INVENTION An object of the present invention is to provide a digital video processing device in which the capacity of an image memory for storing l-field images can be significantly reduced.

[Means to solve the problem]

Means for achieving the above object will be described below with reference to FIGS. 1 and 2, which correspond to embodiments.

The present invention controls writing of digital data of a composite color manual video signal of 1 field for 1 minute into a digital image memory αQ and reading from the image memory αq, and
A digital video processing device that forms and outputs a composite color output video signal based on digital data read from the image memory αq, wherein a color subcarrier phase at a predetermined position of a field start end of the input video signal is detected and a burst phase is detected. a burst phase detection unit aυ that forms 1-bit data of information; a write control unit (6) that writes digital data of the screen valid period of the input video signal and the 1-bit data to the image memory (10); A readout control unit side that reads out the digital data of the screen valid period and the 1-bit data of the memory aQ, a synchronization signal generation unit α4 that forms a composite synchronization signal in synchronization with the readout of the image memory q1, and the image memory A burst signal generator α9 extracts the 1-bit data read from αQ in synchronization with the color subcarry whose phase is inverted and forms a color burst signal for each L line; A digital/analog converter, that is, a D/A converter a0, which converts the digital data of the screen valid period into analog and outputs it; and an output signal of the converter (l) and the composite synchronization signal.

A technical measure is taken to include a signal synthesis unit α which synthesizes the color burst signals to form the output video signal.

[Effect]

According to the digital video processing leg device of the present invention configured as described above, the digital data of the input video signal during the screen effective period excluding the vertical retrace period and the horizontal retrace period and 1 bit output from the detection section αυ are processed. Since the burst phase information data of Based on the digital data of about 83% (52.7 μ5 ec) excluding the horizontal blanking period of <490 horizontal lines, compared to the case of writing all the data for 1 field, about 77. This will significantly decrease to 5%.

When reading the image memory αq, the read digital data is converted into an analog signal by the conversion unit tS, and the generation unit αX forms a composite synchronization signal in synchronization with the reading f of the image memory Ql.

In addition, a continuous wave signal with a color subcarrier frequency whose phase is inverted according to 1-bit data of burst phase information read out from the image memory αQ is extracted by the generator in synchronization with the readout of the image memory αq, and written into the image memory αQ. Each line of color burst signals synchronized with the color subcarrier phase of the input field I is generated by the signal generator α9.

Further, the color burst signal of the composite synchronizing signal 1 generating section α9 of the output signal 1 generating section α of the converting section Qf9 is transferred to the combining section αη.
A proper output video signal with a normal color subcarrier phase is reproduced without writing the digital data of the composite synchronization signal and the color burst signal into the image memory 4.

〔Example〕

Examples will be described with reference to FIGS. 1 to 12.

Figure 1 shows the configuration at the time of writing, and in the figure, (to)
13 is an A/D converter corresponding to the converter (3) in FIG. 13, into which the NTSC composite color input video signal Vi obtained by reception, tape playback, etc. is input, and is output from the multiplier section described later. Based on the timing pulse with a frequency of 3 fsc, the input video signal Vi is digitally converted, and digital data Di quantized to, for example, 8 bits is generated.
Output.

This is a video/chroma synchronization separation unit to which the input video signal Vi is input, and extracts the vertical and horizontal synchronization signals V, H and color burst signals of the input video signal Vi by 1 minute, and extracts the surface synchronization signals V, A color subcarrier signal SC with a frequency fsc synchronized with the H and color burst signals is output. Then, a timing pulse with a frequency of 3fsc synchronized with the subcarrier signal SC is output to the converter (to).

αυ is a burst phase detection unit to which the surface synchronization signals V and H of the synchronization separation unit 01 and the subcarrier signal SC are input;
The subcarrier signal SC is waveform-shaped into a rectangular pulse signal, and based on the timing control of the synchronization signals V and H, a predetermined position of the field start of the input video signal Vi of the L field, for example, several horizontal lines after the vertical synchronization line, is applied. The rectangular wave pulse signal is latched, and 1-bit data Bi of binary information of the burst phase at the predetermined position is formed and output.

αq is a rewritable digital image memory corresponding to the image memory (4) in FIG.
i and 1-bit data Bi are written.

(6) is a write control unit that controls writing to the memory (10), and based on the plane synchronization signals V, H of the sync separator a value and the subcarrier signal SC, a write command signal and an address signal with a frequency of 3fsc are sent to the memory OQ. Output.

Then, the input video signal QVi is synchronized with the input video signal Vi based on the timing pulse of the multiplier (a).
is quantized at a frequency of 3fc and converted into digital data Di, and the digital data D is transferred from the converter mark a to the memory αq.
i is output.

In the case of an NTSC television signal, as shown in Figure 3F, one frame screen consisting of two odd and even fields consists of 525 horizontal lines (=63.5μ5ec).
), and in this case, the horizontal and vertical blanking periods α in the shaded area are
, β (horizontal and vertical blanking periods)<490 horizontal lines of 52.7 μsec is the screen effective period.

Then, due to lack of write command signal and address signal of the control unit (2) synchronized with the input video signal Vi, the memory a
Only the digital data Di of the screen valid period excluding the odd or even 1-pull vertical and horizontal retrace periods is written to q.

That is, in the case of an odd field, the horizontal lines written in the memory σQ are the horizontal lines written in the memory σQ, excluding the vertical retrace period βa, as shown in FIG. As shown in Figure (b), Cζ<490/2 horizontal lines excluding the vertical retrace period βb are the horizontal lines written in the memory αq.

Also, each horizontal line to be written is as shown in Figure 5.
Only a period of <62.7 μsec excluding the horizontal blanking period α in which the color burst signal CBi is located is written into the memory (10).

By the way, in the case of an NTSC video signal, the phase of the color burst signal with the color subcarrier frequency fsc is alternately inverted line by line between the phase shown by the solid line and the phase shown by the broken line in FIG. Based on the phase shift of the scanning start timing with the odd field, the odd and even fields I, M, and Nth of the Nth frame are
+1 frame odd and even fields 1. In the two frames of IV, the phase of the color subcarrier signal is reversed between the Nth frame and the next N+1th frame, and the phase relationship between the synchronization signal and the lack of color subcarrier signal goes around in four fields.

Note that FIGS. 6(b) and 6(C) are subcarrier signals SC, a frequency 3f times the frequency fsc of the synchronous part Q, which is based on the color burst signal indicated by the solid line in FIG. 6(a).
The signal of s( is shown.

In addition, SC in FIGS. 7(a) to (d) is for each field I to
3 shows the reference color subcarrier phase immediately before the screen effective period (2), that is, the color subcarrier phase detected by the detection unit Oυ.

Since chroma reproduction is performed based on the color subcarrier phase of the burst signal CBi, the correct chroma cannot be obtained when reading from the memory Ql using only the digital data Di of the screen valid period of the input video signal Vi written in the memory σq. Cannot play.

Therefore, the detection unit a°C to which the input video signal Vi is input forms 1-bit data Bi of color burst phase information of 1 field to be written into the memory αq.
Bit data Bi is written to memory αq together with digital data Di.

That is, the detection unit αυ is configured as shown in FIG.
The horizontal synchronization signal H shown in FIG. 9B, which is separated and output from the synchronization separator α1 based on the input video signal Vi shown in FIG.
), the flip-flop (lla) receives the signal from the data input terminal (d) every time the horizontal synchronizing signal H rises, and the flip-flop (lla) receives the signal from the data input terminal (d).
) output signal from the Q output terminal (q) of the data input terminal (d
) changes every one horizontal line TH.

Furthermore, the color subcarrier signal SC in FIG. 10(a) output from the sync separator α is connected to a capacitor (Llb).

Resistor (IIc) and inverter (Lid), (LLe)
(Input to the D waveform shaping circuit (llf), at this time,
The output signals of the inverters (lid) and (lie) are shown in the same figure (
As shown in b) and (C), the color subcarrier signal SC is waveform-shaped into a rectangular pulse signal synchronized with the signal SC, and the pulse signal of the inverter (L le) is connected to the flip-flop (l la). is input to the data terminal (d) of.

Therefore, the output signal of the Q output terminal (q) of the flip-flop (Ila) is in phase with the color subcarrier signal SC at the rising edge of the horizontal synchronizing signal H in FIGS. 9(b) and 10(d). Based on Figure '9 (C) and Figure 10 (
e) The level is inverted every horizontal line TH as shown.

Furthermore, in the even field I of the Nth frame, for example, during the vertical retrace period at the beginning shown in FIG. 11(a), the flip-flop (1la) is activated based on the horizontal synchronizing signal H shown in FIG. The output signal of the Q output terminal (q) repeats level inversion as shown in the same figure (C), and the output signal of the same figure (d) is output from the synchronization separator a based on the separation and extraction Cζ of the input video signal Vi. The horizontal synchronizing signal V is delayed by a delay time τd by a delay circuit (l1g), and then inverted by an inverter (tth).
lLh) to a data input type flip-flop (lli
), as shown in (f) of the same figure, to the clock terminal (ck) of
Timing t of detection reference position of color burst phase information
A delayed inverted signal that rises a little later than s is output.

Then, due to the rise of the input signal of the clock terminal (ck), the flip-flop (Lli) is switched to the flip-flop (Lli).
The signal level of the data input terminal (d) connected to the Q output terminal (q) of the flip-flop (I
The output signal of the Q output terminal (q) of li) is shown in Fig. 11(f).
As shown in Iζ, it becomes high level in accordance with the color subcarrier phase SC at timing ts.

In addition, in the odd field ■ of the Nth frame,
Based on the input video signal Vi in FIG. 12(a), the output signal of the Q output terminal (q) of the flip-flop (lla) changes in level in the opposite phase to that in FIG. 11(C) as shown in ) in the same figure. , at this time, the burst phase at timing ts of the detection reference position of burst phase information becomes the inverted phase of field I, and the Q output terminal (q) of the flip-flop (lla) synchronized with the rise of the output signal of the inverter (llh)
), the flip-flop (
As shown in FIG. 11C, the output signal of 111) becomes low level lζ in accordance with the color subcarrier phase SC at timing ts.

Therefore, the color subcarrier phase SC at the timing ts of the field start of each field is detected by the detection unit αυ, and the Q output terminal (q) of the flip-flop (11i) becomes high level or low level depending on the detection result. The output signal is output to the memory αq as 1-bit data Bi of color burst phase information.

Based on the write control signal and address signal of the control unit α, 1-bit data Bi of the detection unit αυ is first written into the memory αq, and then digital data of the screen valid period from the conversion unit α is written. Di is written.

Next, the configuration at the time of reading from the memory αQ is shown in FIG. 2, and the control unit oscillates! The output signal ('13a) is multiplied by 3 in the 0x section (13b), and an address signal with a frequency of 3 fsc is outputted to the multiplication section (18b) to the digital memory 0q together with the read command signal.

Q4) This is a synchronization signal generation section into which the signal with a frequency of 3 fsc from the multiplication section (131)) is input as a timing pulse, and it generates and synthesizes horizontal and vertical synchronization signals in synchronization with the readout of the memory αq. A synchronizing signal SY is formed.

el) is an inverter that inverts the frequency fsc signal of the oscillator (13a); (a) is a switching circuit that is switched and controlled by the high level and low level of the 1-bit data BO read from the memory; 〇α9 is the output signal of the switching circuit (A) and the continuous wave signal of the frequency fsc whose phase has been inverted by In) < - (A).
) with a frequency of 3 fsc, the timing pulse is generated by the generator (14
) is a burst signal generator to which the composite synchronization signal SY of
A continuous wave signal is gate-extracted to form a color burst signal CBo whose phase is inverted for each horizontal line.

aQ is a D/A converter corresponding to the converter (5) in FIG. 13, and converts the digital data Do read from the memory αQ into analog based on the timing pulse of frequency 3fsc from the multiplier (18b). , outputs the video signal Vo for the screen valid period.

aη is a signal synthesis unit that adds and synthesizes the video signal Vo, the synchronization signal SY, and the color burst signal CBo, and based on the output signal of the normal and multiplier unit (tab), memory 0q is written into one field each. 1 bit data B
i f I-bit data Bo is first read out, and then the written digital data Di of the screen valid period is read out as digital data Mr.

Further, the digital data Do read from the memory is input to the converter qQ and converted into analog data, and the digital data Do is input to the converter qQ and converted into analog
The video signal Vo of the screen valid period is output from e to the synthesis unit α.

On the other hand, based on the output signal from the multiplier side, the generator 04)
generates horizontal and vertical synchronization signals during the horizontal and vertical retrace periods of each field synchronized with the reading of memory 4, and synthesizes both synchronization signals to form a composite synchronization signal SY, which is output to the synthesis section α. .

Also, based on the 1-bit data Bi, an oscillator (13a
) A continuous wave signal with a frequency fsc fixed at the oscillation phase of
is output to the generating section α9.

That is, a continuous wave signal with a frequency fsc and a phase corresponding to the burst phase information of the field written in the memory register is
It is output from the switching circuit (A) to the generating section α9.

Then, the continuous wave signal inputted at the timing of the position of the color burst signal of each horizontal line is gate-extracted by the generator α9, and at this time, based on the phase shift (ζ) of the gate extraction of each horizontal line, A color burst signal CBo whose phase is inverted is formed, and this burst signal CBo is outputted from the generating section α9 to the combining section Q7).

Then, the video signal Vo, the synchronization signal SY, and the burst signal CBo are added and synthesized by the synthesis unit αη, and the memory C
Based on the digital data DO issued from 1□ to 12,
An output video signal Vo of one field with regular signal formation is formed and output, and at this time, based on the color burst signal CBo of the generator α9, the output video signal VO is different from the written input video signal Vi of one field. The signals have the same color subcarrier phase.

Therefore, as is clear from Fig. 3, the memory αq
is the digital data Di of the screen valid period of the input video signal Vi of one field, that is, the horizontal of one field,
Only digital data Di of 83% and 98.4% signals in the vertical direction are written.

Therefore, as is clear from the table below, when the input video signal Vi is converted to 8-pin digital data at a frequency of 3 fsc, the required capacity of the memory αQ is 1110
This is a significant reduction to 185 bits, or 77.5% of the total period of digital data stored.

Note that the digital data Di written in the memory 4 is a symbol obtained by performing gentle processing such as screen synthesis on the input video signal Vi through analog signal processing, or a digital signal obtained by, for example, between the converter α mark and the memory αq. The signal may be a processed signal, and when digital signal processing is performed, the output timing of the 1-bit data Bi from the detection unit aυ may be delayed by that period.

Further, in the embodiment described above, the detection section aυ is formed of an analog circuit, but it may be formed of a digital circuit together with the synchronous separation section 0I, for example.

Furthermore, the multiplication portion H, (18b) in FIGS. 1 and 2 may be formed by a common circuit whose connection is switched by writing and reading.

Then, based on the output video signal vO of the combining unit αη,
Various special reproductions or scan conversions such as still image reproduction and strobe reproduction are performed.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

■The digital data of the screen valid period of the composite color input video signal of the field and the 1-bit data of the burst phase information output from the burst phase detection section are written into the digital image memory, and when the image memory is read out, , an output signal from a digital/analog converter that converts digital data read from the image memory into analog;
A composite color output video signal is formed by combining the composite synchronization signal formed by the synchronization signal generation section and the burst signal formed by the burst signal generation section based on 1-bit data of burst phase information read from the image memory. Therefore, it is possible to reproduce and form an output video signal with the correct color subcarrier phase based on the digital data read from the image memory without writing the digital data of the horizontal and vertical retrace periods to the image memory.
(2) The capacity of the image memory required to store images for a field can be significantly reduced compared to the conventional method, and the image memory can be used effectively.

[Brief explanation of the drawing]

Figures 1 to 12 show one embodiment of the digital video processing device of the present invention, Figure 1 and Figure 2 are block diagrams for writing and reading, respectively, and Figure 3 is a frame screen diagram of the NTSC system. Configuration explanatory diagram, Figure 4 (a), (l is odd number, waveform diagram of video signal during vertical blanking period of even field, Figure 5 is waveform diagram of video signal of atomic line, Figure 6 (a), (b) and (C) are waveform diagrams of the color burst signal, color subcarrier signal, and triplex signal, Figures 7 @) to (d) are diagrams explaining changes in color burst phase due to fields, and Figure 8 is a diagram of the color burst phase changes due to fields. Detailed block diagram of the burst phase detection section in Figure 1, Figures 9 (4) to (C), and 10.
Figures h) to (e) and Figures 11 (a) to (f). 12(a) to 12(C) are timing charts for explaining the operation of FIG. 8, and FIG. 13 is a block diagram of a conventional digital video processing apparatus. αq...Digital image memory, αη...Burst phase detection unit, (2)...Write control unit, (to)...Readout control unit, α→...Synchronization signal generation unit, αυ...・Burst signal generator, α...D/A converter, Q7)・
...Signal synthesis section.

Claims (1)

[Claims] (1) Controls the writing of digital data of one field's worth of composite color input video signals to and from the digital image memory, and controls the writing of digital data of one field's worth of composite color input video signals into the digital image memory, and also controls the writing of digital data of one field's worth of composite color input video signals, and outputs composite color output video signals based on the digital data read from the image memory. a burst phase detection unit that detects a color subcarrier phase at a predetermined position at a field start end of the input video signal to form 1-bit data of burst phase information; a write control unit that writes the digital data of the screen valid period and the 1-bit data into the image memory; a read control unit that reads the digital data of the screen valid period and the 1-bit data of the image memory; a synchronization signal generating section that generates a composite synchronization signal in synchronization with memory readout; Extracted in synchronization with reading, each 1
a burst signal generation section that forms a line color burst signal; a digital/analog conversion section that converts digital data of the screen effective period read from the image memory into analog and outputs the same; an output signal of the conversion section; A digital video processing device comprising: a signal synthesis section that synthesizes a composite synchronization signal and the color burst signal to form the output video signal.