JPH0231228A - Information processor - Google Patents

Abstract

PURPOSE:To realize the common use of a microprogram for the machine word instructions having different operands and the same actions by providing a means which processes the given machine word instructions with the use of the operand data. CONSTITUTION:A main memory 1 stores the machine word instructions to be executed and the operand data on these instructions and reads out the instructions with the addresses given from a program counter 5. At the same time, the memory 1 reads out the operand data based on the address given from an address register 11 and gives the operand data to a read data register 17. Then an access control means selects the operand data according to the type information included in the machine word instruction and processes the given machine word instructions with the use of the selected operand data. Thus it is possible to process the machine word instructions having the different operands and the same functions with use of the same microprogram.

Description

DETAILED DESCRIPTION OF THE INVENTION [Objective of the Invention 1 (Field of Industrial Application) The present invention relates to an information processing device that controls access to a plurality of operands using a microprogram 1IIIJ111.

(Prior Art) Conventionally, in a microprogram control type information processing device, the contents of a machine language instruction are usually realized by a microprogram consisting of a plurality of microinstructions. A microprogram corresponding to the contents of each machine JB instruction is prepared. Therefore, even if the instruction codes specifying the operations of machine language instructions are the same, if the operands are different, different microprograms are prepared for each operand.

For example, if the instruction code is an addition instruction, there are three different types of microprograms depending on the type of operand. These are the RR type, in which both operands are registers, the RM type, in which a register and memory are each operands, and the R1 type, in which a register and an immediate value in an instruction are each operands.

(Problems to be Solved by the Invention) As described above, in the conventional microprogram control type information processing apparatus, machine language instructions having the same operation with different operands are processed by different corresponding microprograms.

This has led to the problem of increasing the number of steps in the microprogram. In particular, as the number of machine language instructions to be executed increases as information processing devices become more sophisticated, the number of microprograms increases significantly.

Therefore, the present invention has been made in view of the above, and its purpose is to reduce the number of microprograms by standardizing microprograms for machine language instructions that perform the same operation with different operands. The object of the present invention is to provide an information processing device with improved performance.

[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides an information processor that processes machine language instructions through microprogram control! ! The apparatus has a plurality of types of operand data holding means for holding operand data, and access to the operand data holding means is performed using the same content included in a microprogram corresponding to a plurality of machine language instructions serving as the same camera unit. access vrm means for controlling access to the holding means in accordance with an access command; and a selection means for selecting according to the indicated type information.

(Operation) In the above configuration, the present invention reads operand data according to an access instruction included in the same microprogram for a machine language instruction having the same function, and reads out operand data included in the machine language instruction. It selects according to the type information and uses the selected operand data to process the given machine language instruction.

(Example) Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to an embodiment of the present invention. In the device shown in the figure,
Information indicating the type of operand included in the machine language instruction and access to main memory, which is one of the operands, is specified by il,
A desired operand can be selected from among a plurality of operands based on the information to be processed.

In FIG. 1, operand data of a machine language instruction executed by an information processing device is stored in a main memory 1 and a general-purpose register 3.
or an immediate in a machine language instruction.

Main memory 1 holds machine language instructions to be executed and their operand data. The main memory 1 reads machine language instructions from the program counter 5 via the AD bus 7 . The main memory 1 also reads out operand data according to the address given via the AD bus 7 from an address register (ADR) 11 that holds the access address of the operand data given via the D bus 9, or when the operand data is I'm getting into it.

Operand data stored in main memory 1 is stored in D bus 9.
The data is applied to the write data register (WDR) 13 via the DT bus 5 and held therein, and from this WDR 13 is applied to the main memory 1 via the DT bus 5.

The accessed operand data or machine language instruction is read to the DT bus 5 and applied to the read data register (RDR) 17 via the DT bus 5.

Read data register 17 holds operand data or machine language instructions read from main memory 1. The held operand data is applied via a gate circuit (G) 19 to the SY bus 1 which transfers the source operand. On the other hand, the held machine language instructions are held in the machine language instruction register 23.

The format of machine language instructions is shown in Figures 2(A) to 2(A).
It is configured as shown in D). Machine language instructions consist of four types. These types are identified by type information included in the instructions. Also, machine language instructions basically operate on a source operand and a destination operand, and use vJ! This is a two-operand type in which three results are stored in the destination operand. The destination operand is general purpose register 3 for all types, and the source operand is main memory 1, general purpose register 3. One of the immediates.

The first type of machine language instruction is the RR shown in FIG. 2(A).
There are all types. This RR type t is a type in which the source operand is the general-purpose register 3. therefore,
This RR type includes information ff1Rd that specifies general-purpose register 3 as the destination operand, and information R3 that specifies general-purpose register 3 as the source operand.
are combined. This RR all type type information is “0
It becomes 0h.

The second type is the R1 type shown in FIG. 2 (,B). This R1 type is a type in which the source operand is garbage day 1-I-. Therefore, this R1 type includes information Rd and immediate lllll11. The type information of this R1 type is "10°".

The third type is the type shown in FIG. 2(C). This RM type uses main memory 1 as the source operand. Therefore, this RM type includes information Rd and an address A drs in which source operand data on the main memory 1 is held. The type information of this RM type is 1111 IJ.

The fourth type is a type other than those described above shown in FIG. 2(D), and is, for example, a branch instruction. This fourth
The type information of the type is 1101 IT.

The machine language instruction register 23 to which these four types of machine language instructions are applied and held is configured as shown in FIG. In other words, the machine language instruction register 23
corresponds to each information of the machine language instruction mentioned above,
It consists of an instruction field OP, a destination field Rd, a type field (TYPE), and a source field F's/Ir*ll/Adrs/etc.

Returning to FIG. 1, in the machine language instruction register 23 configured in this way, when the above-mentioned R1 type instruction is held, the RI type immediate is gated! ! 625 to sY Babas 1.

General-purpose register number 3 is made up of a plurality of registers and stores operand data given via the D bus 9. Among the stored operand data, the signature A belland data is applied to the Sx bus 27. On the other hand, the source operand data is passed through the gate circuit 29
Given to Y Babasu 1.

The destination A operand data given to the SX bus 27 and the source operand data given to the SY bus 1 are transferred to the n-art logic manipulation unit (ALLI) 31.
Operations such as addition and logical sum are performed in accordance with information indicating the processing content of the machine language instruction. The calculation result is output to the D bus 9.

A microprogram consisting of microinstructions that generate control signals to perform such operations is
It is stored in a micro ROM (μROM) 33. μR
The microinstructions stored in OM 33 are given to microphone 0 instruction register 35 when executed.

The microinstruction register 35 holds microinstructions being executed. As shown in FIG. 4, this microinstruction register 35 is configured to hold microinstructions consisting of the first to sixth fields.

The first field (ALU) of the microinstruction is ALU3.
Do the 1st action! This is a field for IIJ111.

The second field <SX> specifies the output to the SX bus 27.
f, IJ III field. The third field (SY) is a field that controls the output to the SY bus 1. The fourth field (D> is a field that controls input from the D bus 9. The fifth field (M
C) is a field that is a feature of this embodiment, and is an access command field that commands access to the main menu 1. The sixth field (and others) is a field for controlling other than the above, for example, a field for controlling the sequence of a microprogram.

Next, regarding microinstructions having such a configuration, the configuration of a microprogram when the machine language instruction is, for example, an addition (ADD) instruction will be described with reference to FIG.

In FIG. 5, the 1-add Fr instruction is composed of six fields from the first field to the sixth field.

The first field executes the add microinstruction.

This is a microinstruction that instructs the ALU 31 to perform fraud processing.

The second field executes the id microinstruction. This indirectly specifies Destination Overand. That is, the contents of the register specified by the destination field of the machinist R command register 23 are
This is a microinstruction that is output to the bus 27.

The third field executes the is microinstruction. This indirectly specifies the source operand.

That is, it is a microinstruction that outputs the value of the general-purpose register 3/immediate/main memory 1 specified by the type field and source field of the machine language instruction register 23 to the SY bus 1.

The fourth field executes the id microinstruction. This indirectly specifies "Destination Oberand". That is, there is a microinstruction that hits the value transferred to the D bus 9 in the register specified by the destination field of the machine gl instruction register 23.

The fifth field executes a read microinstruction. This is a microinstruction that controls access to main memory 1. This field is a feature of the present invention, and access to main memory 1 is valid only when the type field of machine language instruction 23 is main memory 1. If the type field is general purpose register 3 other than main memory 1 or immediate, this microinstruction becomes a nop microinstruction.

The sixth field executes the end microinstruction 76. This is a microinstruction indicating that the addition instruction microprogram ends with this microprogram.

Next, a configuration in which access to A belland data can be controlled by machine language instructions and microprograms as described above will be explained with reference to FIG.

Figure 6 shows the S of the three source operand data mentioned above.
There is a diagram showing a configuration for controlling the output to the Y bus 1. Note that in FIG. 6, the same reference numerals as in FIG. 1 are the same, and the explanation thereof will be omitted.

In FIG. 6, a memory control circuit 41 is a circuit that controls the read operation and old loading operation of the main memory 1. This memory control circuit 41 includes AND gates 43 .
45, the main memory 1 is caused to perform read and write operations. That is, when the output of the AND gate 43 is "1'", the memory control circuit 41
The main memory 1 is commanded to perform a continuous output operation. On the other hand, if the output of the AND gate 45 is M I 11, it instructs the main memory 1 to perform an old loading operation.

The AND gate 43 has one input supplied with a read signal serving as the output of the decoder 47, and the other input supplied with a 1llell signal serving as the output of the decoder 49.

The AND gate 45 has one input supplied with the write signal which is the output of the decoder 47, and the other input supplied with the lea signal of the decoder 49.

The decoder 47 decodes the contents of the fifth field of the microprogram held in the microinstruction register 35. The decoder 47 outputs a read signal as a "1" level when the fifth field is a read microinstruction. Furthermore, if the fifth field is a write microinstruction, the decoder 47 outputs the write signal at the "1" level.

The decoder 49 receives the machine commands stored in the machine language instruction register 23! It decodes the value of the instruction's type field. When the type field indicates the RR type, the decoder 49 outputs the gr multiplied signal 111 as N level. Further, if the type field indicates the Ri type, the 1iua signal is output as the a I IT level. Furthermore, if the type field indicates the RM type, the l1el signal is output as a "1" level.

The decoder 51 decodes the contents of the third field of the microinstruction held in the microinstruction register 35. When the third field of the microinstruction is an IS microinstruction, the decoder 51 receives an isS signal "1".
Output as level.

Decoder 49 provides the 9j signal to AND gate 53 and the imn+ signal to AND gate 55.

The decoder 51 receives its isS signal AND gate t-53.

Give to 57.

The AND gate 53 controls the conduction of the gate circuit 29. That is, the AND gate 53 is II 1
11 level isS signal (lr (No. 5 is given,
The gate circuit 29 is made conductive.

The AND gate 55 controls the conduction of the gate circuit 25. That is, the AND gate 55 has 111
When 1ml of IT level isS signal is given,
The gate circuit 25 is made conductive.

The AND gate 57 is used to control the conduction of the gate circuit 19. That is, when the AND gate 57 receives the output of the isS signal AND gate 43 at the "1" level, it makes the gate circuit 19 conductive.

As explained above, one embodiment of the present invention has been constructed, and next, the operation of this embodiment will be explained.

First, 'Is processing depending on the instruction type is performed.

The value of the program counter 5, which holds the address of the machine language instruction to be executed, is output to the AD bus 7, which is an address bus to the main memory 1. and,
This address is transferred to main memory 1 and the instructions are read from the machine. The machine language instruction read here is addition (ADD).
Make it a command.

The read ΔDD instruction is set in the machine language instruction register 23 via the read data register 17. ADD
When a command is set in register 23 in the machine,
Although not shown, the corresponding microprogram is μRO.
It is read from M33 and set in the microinstruction register 5. Up to this point, it does not matter whether the source operand is general-purpose register 3, immediate, or main memory 1. μ
The same applies to the microprogram read from the ROM 33. That is, the microprogram shown in FIG. 5 is read out in common.

The subsequent processing is the same microphone[] program, but differs depending on the source operand. First, the RR type will be explained.

Depending on the read microprogram, the contents specified by the id microinstruction in the second field are output to the SX bus 27, although some of them are not shown. That is, the contents of one of the general-purpose registers 3 indicated by the gaystinacy field of the machine language instruction register 23 are output.

The contents specified by the is microinstruction in the third field are output to the SY bus 1. That is, the contents of one of the general-purpose registers 3 indicated by the type field and source field of the machine language instruction register 23 are output.

This operation will be explained in detail. First, since the third field of the microprogram is an is microinstruction, the S signal is "1"1 among the outputs of the decoder 51.
``Level, -1j, since the type field of the machine language instruction register 23 indicates the RR type, the decoder 49
makes the gr multiplied signal "1' level. As a result, the AN
The output of the D gate 53 goes to the "1" level, and the gate circuit 29 becomes conductive. As a result, the contents of the general-purpose register 3 are output to the SY bus 1 via the gate circuit 29. Although it is not shown which register of 3 is selected, the value of the source field of the machine Sn instruction register 23 is sent as address information to the address manual section of the general-purpose register 3.Then, the value of the source field is The value of the corresponding general-purpose register 3 is output.

Since the operation of the ALU 31 is addition starting from the add microinstruction of the first field, the ALU 31 performs addition processing and outputs the result to the D bus 9.

The value output to the D bus 9 is input to the location specified by the id microinstruction in the fourth field. However, it is input to one of the general-purpose registers 3 indicated by the destination field of the machine language instruction register 23. In the fifth field, since the type field of the machine language instruction 23 indicates general-purpose register 3, the read microinstruction is ignored and becomes a nop microinstruction.

This operation will be explained in detail. The fifth field of the microinstruction register 35 holds a read microinstruction 75. Therefore, among the outputs j of the decoder 47,
The read signal goes to the "1" level.

On the other hand, the type field of the machine language instruction register 23 is R.
Since the R type is indicated, the decoder 49 has the gr multiplied signal °゛1''1'' level. The 1ell signal remains at the "0" level. Therefore, the outputs of the AND gates 43 and 45 both remain at the "°0" level. Therefore, memory control circuit 41 does not perform a read operation from memory 1. In other words, the read microinstruction is treated as a nop. The sixth field is an end microinstruction, which indicates that the AI)Da instruction ends.

The RR type of the ΔDD instruction is executed by the above-mentioned process 1.

Next, the R1 type will be explained. It is basically the same as the RR type.

The contents specified by the id microinstruction in the second field are output to the Sx bus 27 by the microprogram. In other words, the contents of one of the general-purpose registers 3 indicated by the eye destination field of the machine language instruction register 23 are output.

The contents specified by the is microinstruction in the third field are output to the SY bus 1. That is, the immediate value held in the source field of the machine language instruction register 23 indicated by the type field of the machine language instruction register 23 is output.

This operation will be explained in detail. First, since the third field of the microprogram is an IS microinstruction, the S signal among the outputs of the decoder 51 is "1".
become the level. On the other hand, since the type field of the machine language instruction register 23 indicates the R1 type, the decoder 4
9 makes the in signal 1111 lbs. This results in
The output of the AND gate 55 becomes the 1n level, and the gate circuit 25 becomes conductive. As a result, the immediate value held in the source field of the machine language instruction register 23 is output to the SY bus 1 via the gate circuit 25.

Since the operation of the ALU 15 is addition starting from the add microinstruction of the first field, the ΔLU 15 performs addition processing and the result is output to the D bus 9. The value output to the D bus 9 is input to the location specified by the id microinstruction in the fourth field.

That is, the machine ah f? It is input to one of the general-purpose registers 3 indicated by the destination field of the i-instruction register 23. In the fifth field, since the type field of the machine language instruction register 23 indicates immediate, the read microinstruction is ignored and becomes a nop microinstruction.

This operation will be explained in detail. The fifth field of the microinstruction register 35 holds a read microinstruction. Therefore, behind the output of the decoder 47, rea
The d signal goes to the "1" level. On the other hand, since the type field of the machine language instruction register 23 indicates the RI type, the decoder 49 sets the lff1m signal to the "1" level. The lem signal goes to the #O11 level. Therefore, the outputs of AND gates 43 and 45 both remain at 0''. Therefore, the memory control circuit 41
No read operation is performed. In other words, the read microinstruction is treated as a nop. The 6th field is e
With the nd microinstruction, this allows the ADD instruction to be changed! It shows that.

Through the above processing, the R1 type ADD instruction is executed.

Finally, the RM type will be explained.

The contents specified by the id microinstruction in the second field are output to the SX bus 27 by the microprogram. That is, the contents of one of the general-purpose registers 3 indicated by the destination field of the machine language instruction register 23 are output. For SY Babas 1, enter i in the third field.
The contents specified by the s microinstruction are output. In other words, since the type field of the machine language instruction register 23 indicates main memory 1, the read data register 17
The source operand is output via .

This operation will be explained in detail. First, the type field of the machine language instruction register 23 indicates the RM type. Therefore, the decoder 49 parses the 10111 signal.
''' level.Furthermore, the fifth field is read.
Holds microinstructions. At that point, the read signal on the other side of the output of the decoder 47 becomes 1111+ level.

Therefore, the output t of the AND gate 43 goes to the "1" level. Therefore, the meter control circuit 41 performs a read operation from the main memory 1. At 1jb, the read microinstruction is executed. Operand data is read from memory 1 and set in read data register 17.

At this time, since the third field is an IS microinstruction, the iS signal among the outputs of the decoder 51 becomes the "1" level. As a result, the output of the AND gate 57 becomes the "1" level, and the gate circuit 19 becomes conductive.

As a result, the contents of the read data register 17 are output to the SY bus 1 via the gate circuit 19.

Since the add microinstruction in the first field in the ALLJ15 operation is an addition, the ALU15 performs addition processing and outputs the result to the D bus 9. The value output to the D bus 9 is input to the location specified by the id microinstruction in the fourth field. Machine language instruction register 23
is input into one of the general-purpose registers 3 indicated by the destination field. The sixth field is an end microinstruction, which indicates that the ADD instruction ends.

The RM type of ADD instruction is executed by the above processing.

As mentioned above, in the RR type and RI type, the rea
Since the d microinstruction is masked by the AND gate 43, the memory control circuit 41 does not perform read processing to the main memory 1. On the other hand, in the RM type, the output of the AND gate 43 is set to the "1" level from the read microinstruction and the type field.
performs read processing. In this way, the ADD instruction can be processed by one type of microprogram regardless of the type of operand.

Further, in the above embodiment, the processing for a read microinstruction is explained in C, but the same can be done for a write microinstruction. That is, if the fifth field of the microprogram is a write microinstruction, the decoder 47 sets the write signal to the 14111 level. At this time, if the type field is in the main memory 1''c, the decoder 4
9 sets the iei signal to the "1" level, so the output of the AND gate 45 becomes the "1" level. As a result, the memory control circuit 41 performs write processing to the main memory 1.

If the h1 type field is other than main memory 1, the decoder 49 leaves the ie+m signal at the 110 II level. Therefore, the memory control circuit 41 does not perform the tampering process.

In the embodiment described above, the eye destination A belland is fixed in general-purpose register 3, and the source operand is general-purpose register 3. Although the information processing device can select from among the immediate and main menus, the destination operand and source operand are general-purpose registers. Immediate, select from main memory 1).'C;b doesn't matter. Even if you do this,
This can be achieved by adding a type field to the obscene language instruction and adding a field for instructing destination memory access to the microinstruction register 35 in the same way as the above method.

Further, although the above-described embodiment is an information processing device with a non-pipeline structure, it can be similarly implemented with an information processing device with a pipeline structure. For example, the pipeline can perform ■instruction fetch, ■decode, and ■operand address calculation/A.
It is the same as the A-mat, which has three stages of information processing (perrando edge/execution/update) (even if there is one, the microinstruction format is the above). Therefore, the microprograms are the same and can be implemented in the same way.

Furthermore, in the above embodiment, the operand type is an independent field in the format of the machine language instruction, but there is also an information processing unit 4 in which the operand type is indicated in the instruction code. For example, the RR type instruction code for the addition instruction is H'
0A (hexadecimal), RI type instruction code is ll-1
-The instruction code of the CAlt type is H'4A. Even in such an information processing device, by decoding the instruction code, it is possible to distinguish whether the operand type is a general-purpose register, immediate, or main memory. Therefore, it can be realized in the same way as the above embodiment.

[Effects of the Invention] As explained above, according to the present invention, operand data is read out according to the ACKHIS instruction included in the same microprogram corresponding to machine language instructions of the same function, and the read operand data is read out. Since the selection is made according to the type information included in each machine language instruction and corresponds to the type of operand, it is possible to process machine language instructions with the same function with different operands in the same microprogram. It is possible to standardize programs. This makes it possible to reduce the number of microprograms. As a result,
It is also possible to downsize the device by reducing the storage area for the microprogram.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an information processing device according to an embodiment of the present invention, FIG. 2 is a format diagram of machine language instructions executed by the device shown in FIG. 1, and FIG. 1st
FIG. 4 is a diagram showing the configuration of the machine language instruction register in the Vt position shown in the figure. FIG. 4 is a diagram showing the configuration of the microinstruction register in the device shown in FIG. 1. FIG. FIG. 6, which is a diagram showing an example of a microprogram, is a diagram showing a configuration for controlling operand access of the device shown in FIG. 1. 1... Main memory 3... General purpose register 23... Machine language instruction register 35... Micro instruction register 19.25.29... Gate circuit 41... Main control circuit 43.45, 53,55.57...AND goo 1-4
7.49.51... Decoder Figure 4 Figure 15 Deputy to valve block Yasuo Miyoshi

Claims (1)

[Scope of Claim] An information processing device that processes machine language instructions under microprogram control, characterized in that a plurality of types of operand data holding means for holding operand data and access by the operand data holding means have the same function. access control means for controlling according to an access command that instructs access to the holding means, which is included as the same content in a microprogram corresponding to a plurality of machine language instructions; and operand data read from the holding means by the access control means. and a selection means for selecting according to type information included in a machine language instruction and indicating the type of the operand data holding means.