JPH02311017A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To attain high circuit integration comprising efficient composite logic gates by using a gate array including a prescribed ratio of 1st and 2nd cells, and also including a couple of bipolar transistors(TRs) used selectively, and arranging plural basic cells in a lattice form. CONSTITUTION:Logic gate circuits requiring only 1-2 fanouts whose load capacity CL is smaller than a prescribed value Ca such as inverter circuits N1-N3, NAND gate circuits NAG 1, 2 and a NOR gate circuit NOG 1 are constituted by a 1st basic cell BC 1 being a basic cell BC. Moreover, logic gate circuits requiring lots of fanouts whose load capacity LC is larger than a prescribed value Cb such as a NAND gate circuit MNA 1 and NOR gate circuit BNO 1 are constituted by a 2nd basic cell BC 2 being a basic cell BC. Furthermore, a composite logic gate circuit requiring 8 fanouts whose load capacity CL is greater than a prescribed value Cc such as a NOR gate BNO 1 consists of 2 BiCMOS, the emitter size is expanded to improve the drive capability.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a semiconductor integrated circuit, for example,
The present invention relates to a technique that is particularly effective for use in bipolar 0MO8 (hereinafter abbreviated as Bl-CMO8) gate arrays.

[Conventional technology]

The B1/CMO8 composite logic gate circuit, which is composed of a pair of output bipolar transistors in a totem pole configuration and a 0MO8 (phase [ff1M・os >ta logic gate circuit), has a relatively large drive capacity and low attenuation. - Therefore, the B1/C'MO5 logic gate has come to be applied to various semiconductor devices, such as gate array devices, memory devices, and microcomputers.

By the way, regarding gate arrays using 8110MO8 logic gates, please refer to Japanese Patent Publication No. 59-139724.
There is a number.

Furthermore, regarding the basic cell used in the B1 eMoS gate array device, Japanese Patent Publication No. 61-17
No. 1150 1 Japan Patent Association Publication No. 59-193627, Bernard C, C.
o1e) From K, elect o=kus/7 Oprah,
4.1988 (Electronics /F@b
ruhrV 4.1988), pp65-66, “Msis by Seventh Alley Hitsu L/:
7-Tocate Utilization Blind (AMCC',
BiCMO8ARRAY ) (ITS RECOD
EGATE UTILIZATION), and Nakuri et al.
NEC Technical Report V by Nal (asiba et al)
o1.39 No-10/1986pp138-143
“Low Power High 5peed BI
There is CMO8Gate-Array)J.

Furthermore, a gate array is a type of semiconductor integrated circuit device that can realize a wide variety of semiconductor integrated circuit devices by applying wiring processes for each type to master wafers that have been produced in large quantities in advance. called a device. This method has the advantages of lower costs due to large-cap production of the master wafer, shorter development period due to automatic wiring design and a shorter manufacturing process that involves only side placement.

[Problem to be solved by the invention]

The conventional B1-CMOS gate array as described above has the following problems.

In other words, as shown in FIG. However, when a relatively small load capacitance CL is coupled,
Conversely, the transmission delay time tpd becomes longer than that of the CMO8 logic gate circuit.

On the other hand, the transmission delay time t of the B1/CMO8 logic gate circuit
As shown in FIG. 7, pd has a similar load dependence depending on its driving capacity, that is, the emitter size ES of the output transistor.In other words, the output transistor has a larger ivy size ES and a larger driving capacity. In this case, the transmission delay time tpd becomes smaller in a region where the load capacitance CL is large than when the emitter size ES is made small, and conversely becomes larger in a region where the load capacitance jlcL is small.

In other words, the logic circuit has a load capacitance tcL coupled to the output terminal of each logic gate circuit, which is 7% depending on the unout.
By selectively combining CMO8 logic gate circuits or Bi.CMO5 logic gate circuits and optimizing the driving ability of each logic gate circuit, the transmission delay time tpd can be minimized.

However, the basic cell of the conventional 81 CMOS gate array does not include a bipolar transistor to substantially enlarge the emitter size ES of the output transistor of the Bi-CMO8 logic gate circuit and increase its driving capability.
Furthermore, no effort was made in the layout and distribution of each basic cell so that the emitter size of the output bipolar transistor could be substantially expanded. For this reason, it is difficult to optimize the drive capacity of each logic gate circuit according to the load capacitance, and the overall transmission delay time tpd of the logic circuit constituted by the gate array cannot be reduced as desired. It was found that high-speed operation of logic circuits is inhibited.

The purpose of this invention is to
Efficiently convert O8 logic gate circuit and Bi@CMO8 composite logic gate circuit to 11! An object of the present invention is to provide a basic cell of a gate array that can be constructed and a layout method thereof.

Another object of the present invention is to achieve higher integration of gate arrays and to increase the speed of logic circuits constituted by the gate arrays.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the attached drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, the gate array is basically CMO8II'4
It contains a first cell used to configure a basic KBi/CMO8 logic gate circuit and a second cell used to configure a basic KBi/CMO8 logic gate circuit in a predetermined ratio.
-CMO8 The circuit includes a pair of bipolar transistors that are selectively used when a large driving capability is required in the logic gate circuit, and is composed of a plurality of basic cells arranged in a grid pattern.

[For production]

According to the above means, by optimizing the ratio of the first and second cells included in the basic cell, the CMO8 logic gate circuit and the B1/CMO5 logic gate circuit are optimized according to the required driving ability. Logic gate circuits can be configured efficiently without waste. This improves the usage efficiency of the gates included in the gate array. Since gate usage efficiency is improved, the number of circuit elements in the gate array can be reduced and the gate array can be highly integrated.

Further, the logic circuits formed in the gate array may include a 0M08 circuit, a MIBl-0M08 circuit including an output bipolar transistor with an output bipolar transistor size of 3 μi, and the first Bl-
Output bibolar transistor 2 with emitter size larger than emitter size of output bipolar transistor of 0M08 circuit
selected from among the second Bi-0M08 circuits including the transistors. That is, the logic circuit has a circuit configuration that allows its output load capacity to be charged and discharged as quickly as possible. As a result, by adopting the above design method, the operating speed of the logic circuit configured in the gate array is increased.

〔Example〕

FIG. 2 shows a layout diagram of a gate array to which the present invention is applied. Further, FIG. 1 shows a layout diagram of one embodiment of the basic cell BC of the gate array of FIG. 2. In FIG. In the present application, a basic cell is defined as a basic unit on a layout including a plurality of semiconductor elements. The basic cells BC forming the gate array shown in FIG. 2 and the circuit elements shown in FIG. Ru.

In FIG. 2, the gate array includes, although not particularly limited to, a plurality of external connection terminals PAD, which are signal input/output terminals arranged at the periphery of the rectangular semiconductor substrate SUB, and a plurality of external connection terminals PAD arranged at the center of the semiconductor substrate SUB. #! includes an internal logic circuit that is arranged as follows and includes a plurality of basic cells BC, and an output buffer circuit I10 that is arranged between the internal logic circuit and the external terminal pad. FIG. 2 exemplarily shows a wiring channelless type gate array. The basic cells BC included in the gate array are not particularly limited, but all have the same configuration, for example, as shown in FIG. ~NM5 and four bipolar transistor regions BTI~BT4 and t, of which the PMO8 areas PMI~PM3 each include three P-channel MO8FETs with relatively large conductance; teeth,
The NMO8i region NM4 includes three N-channel O8FETs each having relatively large conductance;
includes one N-channel O8FET with relatively small conductance, and the bipolar transistor regions BTI to BT4 each include one pibo-2 transistor with a predetermined emitter size, for example, 1×3 μd. include.

In each basic cell BC, the distance between the source S and drain D of each P-channel MO8FET constituting the PMO8 region PM1 is not particularly limited.

Gates G made of polysilicon are respectively formed.

These gates G are connected to the corresponding N of the NMO8 region NMI.
It is extended between the source and drain of the interchannel O8FET. As a result, the gates of each P-channel MO8FET in the PMO8 region PMI and the corresponding N-channel inter-O8FET in the NMO8 region NMI are commonly coupled. The three P-channel MO8FETs and N-channel MO8FETs provided in the PMO8 region PMI and the NMO8 region NMI are regarded as this basic cell BCf)gl cell, and are a three-person CMO8 logic gate circuit consisting of three sets of 0MO8s or equivalent. A two-person CMO8
It can be used to configure a logic gate circuit and a CMOS inverter circuit (in other words, a 1-input CMO8 logic gate circuit).

Similarly, each P channel MO8F of PMO8 area PM2
The gates G of the ETs are commonly coupled to the gates G of the corresponding N-channel MO8FETs in the NMO5 region NM2. These PMO8 area PM2 and NMO8 area N
The three P-channel MO8FETs and N-channel MO8FETs provided in M2 are also connected to this basic cell BC.
It can be used to configure a three-man power logic gate circuit consisting of three sets of 0MO8, or a two-man power logic gate circuit and a CMOS inverter circuit corresponding thereto.

On the other hand, each P channel MO8FE of PMO8 area PM3
The gates G of T are commonly coupled to the gates G of the corresponding N-channel MO8FETs in the NMO8 region NM4, and are further commonly coupled to the gates G of the corresponding N-channel MO8FETs in the NMO8 region NM3.
They are commonly coupled to the gates G of the O8FETs. PM
Three P channels MO8 provided in O8 & area PM3
6 provided in FET and NMO8 regions NM3 and NM4
N-channel MO3FETs have N M OS area N
Together with one N-channel MO3FET provided in M5 and four bipolar transistors provided in bipolar transistor regions BTI to BT4, it is regarded as the second cell of this basic cell BC, and is a two- or three-person Bl-CMO3 logic Gate circuit or B1-CMOS
Inverter circuit (in other words, 81/CMO with l input
8 complex logic gate circuits).

In the PMO8 regions PMI to PM3, each P-channel MO8FET is formed by doping each gate with an impurity and introducing 1 boron into the semiconductor substrate. In the NMO8 regions NM1-NM5, each N-channel O8FET is formed by introducing phosphorus or arsenic into the semiconductor substrate using each gate as an impurity introduction mask.

In the gate array of this example, Bl -CMO8
Although the logic gate circuit is not particularly limited, it can selectively have two levels of driving ability.

That is, when a relatively small driving capacity is required for the Bi-CMO3 logic gate circuit, two bipolar transistors formed in the bipolar transistor regions BTI and Br3
The transistor is an output transistor. On the other hand, Bi-
When a relatively large driving capacity is required for the CMO5 logic gate circuit, a pair of biborad 2 transistors formed in the biborder 2 transistor regions BT3 and Br4 is used as an output stage composed of bipolar transistors formed in the regions BTI and Br3. are connected in parallel to two biborad transistors. 8 shows a schematic representation of the circuit elements included in the basic cell BC shown in FIG. 1. FIG. is shown. Also,
4 to 6 (a) and (b) show the CMOS inverter circuit Nl and the CMOS included in the logic circuit of FIG.
Nutgate circuit NAGI.

B1/CMOS Nant gate circuit BNAI and B1-C
A circuit diagram of the MOS NOR gate circuit BNO10 is shown. In these figures, the MOSFET with an arrow added to the channel (back gate) part is a P-channel MOSFET, and the MOSFET with no arrow added is an N-channel MOSFET.
Distinguished from ET. Furthermore, all the bipolar transistors shown in the figure are NPNm) transistors. In addition,
In FIGS. 11 and 3, detailed explanations of the specific calculation conditions of the logic circuit and the logic conditions of each input signal and output signal will be omitted since they are not directly related to the present invention.

In FIG. 3, an input signal A supplied from a logic circuit (not shown) is inverted by a CMOS inverter circuit Nl, although not particularly limited, and then supplied to the first input terminal of a CMOS nutgate circuit NAGI. Input signals B and C are supplied to the second and third input terminals of the CMOS Nant gate circuit NAGI, respectively, from a logic circuit (not shown). The output signal of the CMOS Nant gate circuit NAGI is inverted by the CMOS inverter circuit N2 and then supplied to the input terminal WI1 of the B1-CMOS Nant gate circuit BNAI. The second and third input terminals of this B1 CMOS Nant gate circuit BNAI are supplied with an input signal I and an input signal E, respectively, from a logic circuit (not shown). B1-
The output signal F of the CMOS Nant gate circuit BNAI is B
1. It is supplied to the Ml input terminal of the CMOS NOR gate circuit BNOI, and is also supplied to other circuits of the logic circuit. The output signal F of the B1-CMOS Nant gate circuit BNA1 is supplied to the input terminals of a total of three logic gate circuits, of which there are three input terminals. Note that fan-out refers to a circuit that is connected to the output terminal of one circuit, and
It is defined as the number of inputs to the next stage circuit that are duplicated by that circuit.

Here, the CMOS inverter circuit N1 has a circuit power supply voltage VCC and a ground potential GND as shown in FIG.
P-channel MO8FETQ1 and N-channel MO8 whose source-drain paths are provided in series between them.
Contains FETQII.

The gates of these MO8FETs Qt and Qll are commonly coupled and serve as input terminal 1 of the CMOS inverter circuit Nl. Further, the commonly connected drains of the MO8FETs Q1 and Qll are used as the output terminal 0 of the CMOS inverter circuit Nl. From this K, the output signal O of the CMOS inverter circuit N1 is set to a low level such as the ground potential of the circuit when the input signal l is set to a high level, and when the input signal l is set to a low level, the output signal O of the CMOS inverter circuit N1 is set to a low level such as the ground potential of the circuit.
It is considered to be a high level such as.

The CMOS inverter circuit N2 has the same circuit configuration as the CMOS inverter circuit N1.

In this embodiment, the CMOS inverter circuit MN1
MO8FET Q1) I 1% of the basic cell BCI is configured by the first P-channel MO8FET provided in the PMO5 region PMIK, but is not limited to 1%, and is
8FETQI 1 is constituted by a first N-channel O8FET provided in the NMO8 region NMI. Similarly, MO8FE of CMOS inverter circuit N2
TQI is not limited to *, but the PMO of basic cell BC
Each of the MO8FETs is configured by a second or third P-channel MO8FET provided with an 8-area PMIK.
QI 1 is the ts provided in the NMO8 region NMI.
Each of them is composed of two or third N-channel MO8FETKs.

Next, the CMOS Nant gate circuit NAGI connects the power supply voltage VCC of one circuit and the ground potential G as shown in diagram N5.
P-channel MO8FETQ2 and N-channel MO whose source-drain path is provided in series between ND
The source drain path of MO8FBTQ2, including 8FETQI 2 to Q14, further includes a KP channel MO8F
The source drain paths of ETQ3 and Q4 are provided in parallel configuration. The gate of MO8FETQ2 is MO8FET
It is commonly coupled to the gate of Q12 and serves as the first input terminal 11 of the CMOS Nantes gate circuit NAGI. Similarly,
Each gate of MO8FETQ3 and Q4 is 8l
Commonly coupled to the gates of 08FETQI 3 and Q14, respectively, and connected to the CMOS Nantes gate circuit NAGI
tpJ2 and third input terminals I2 and 13.

As a result, the output signal 0 of the CMOS Nant gate circuit NAGI is set to a low level like the ground potential GND of the circuit when all the input signals 11 to i3 are set to a high level, and when any of the input signals 11 to i3 is set to a low level. When it is set, it is set to a high level like the circuit power supply voltage VCC.

In this example, a CMOS Nant gate circuit NAG
I P Channel M OS F Jli: T Q 2
~Q4 is configured by the first to third P-channel MO8FETs provided in the PMO3 region PM2 of the basic cell BCI, although not particularly limited thereto.

Further, the N-channel MO8FETs Q12 to Q14 are the first-channel MO8FETs provided in the NMO8 region NM2 of the basic cell BCI.
It is composed of a third ON channel MO8FET.

B1-CMOS Nant gate circuit gBNA1 is shown in Figure 6-
), the circuit includes totem-pole output bipolar transistors T1 and T2 whose collector-emitter paths are connected in series between the power supply voltage VCC of the circuit and the ground potential GND.

The commonly coupled node of the emitter of the output transistor TI and the collector of the output transistor T2 is B1.CM
It is set as the output terminal 0 of the OS Nant gate circuit BNAI. 11 source voltage V of the base of the output transistor Tl and the circuit
Three P-channel MO8FETs Q5 to Q7 whose source-drain paths are parallel are provided between CC. Furthermore, between the base of the output transistor TI and the circuit ground potential GND, there are three N-channel MOS F E transistors whose source-drain paths are connected in series.
TQ15 to Q17 are provided. These MO8FE
TQ5 to Q7 and Q15 to Q17 constitute a three-man powered CMOS Nant gate circuit similar to the above-mentioned diagram ll&5.

On the other hand, three N-channel MO8FETs Q18 to Q20 whose source/drain paths are connected in series are provided between the base of the output transistor T2 and the output terminal 0. Further, an N-channel MO8FETQ21 whose gate is commonly coupled to the output terminal 0 is provided between the base of the output transistor T2 and the circuit ground potential GND. The gates of MO8FETQI 8 to Q20 are commonly coupled to the corresponding gates of MO8FETQI 5 to Q17, respectively, and are connected to 1g1 to third input leakage 11-''- of the Bl/CMOS Nantes gate circuit BNAI, respectively.
It is said to be 13. As a result, the output signal 0 of the B1 CMOS Nant gate circuit BNAI is equal to the power supply voltage VCC of one circuit when both the input signals i1 to i13 are at high level.
When any of the input signals 11 to i3 is set to a low level, it is set to a high level that is lower by the base-emitter voltage of the output transistor T2 than the ground potential of the circuit by the base-emitter voltage of the output transistor T2. It is considered to be Roku level.

In this embodiment, the output transistors TI and T2 of the B1/CMOS Nant gate circuit BNAI are respectively constituted by bipolar transistors provided in the bipolar transistor regions BTI and Br3 of the basic cell BCI, although not particularly limited thereto. In addition, P channel AIMO8FETQ5~Q7 and N channel MO5
FETQ15 to Q17 are first to third P-channel MO8FETs and N-channel/l/M provided in PMO8 region PM3 and NMO8 region NM3 of basic cell BCI.
Each is configured by an O8FET.

Further, the N-channel MO8FETQI 8 to Q20 are respectively configured by first to third N-channel 2w10SFETs provided in the NMO8 region NM4 of the basic cell BCX, and the N-channel MO8FETQ21 is configured by one N-channel MO8FET QI provided in the NMO8 region NM5. Consists of N-channel MO8FETK.

By the way, in the embodiment shown in FIG. 3, the fan-out fo of the B1 CMOS Nantes gate circuit BNA1 is set to 3, so the output stage of the B1 CMOS Nantes gate circuit BNA1 is 2 times by a pair of transistors TI and T2, respectively.
``C1 is formed.B1・CMOS Nantes gate circuit BN
When a relatively large driving capacity of the AIK is required, that is, when the 77-in-out fo is set to 7 or more, as shown by the dotted line in Figure #I6 (a), the output 2
The output transistors T3 and T2 are connected to the output transistors T1 and T2.
4 are respectively provided in parallel form. Although not particularly limited, these output transistors T3 and T4 are connected to the bipolar transistor regions BT3 and Br of the basic cell BCI.
Each of the two bipolar transistors is constructed of a pair of bipolar transistors provided at 4.

In Figure 3, BI building CMOS Noah gate circuit BNO
The second and third input terminals of I are supplied with inverted signals of the input signal G and the input signal H by the CMOS inverter circuit N3 from a logic circuit (not shown), respectively. B
1-The output signal of the CMOS NOR gate circuit BNOI is as follows:
It is supplied to the first input terminal of the CMOS Nant gate circuit NAG2 and also to a circuit (not shown) of the logic circuit. The output signal of the B1.CMOSMOS-to-circuit BNO1 is supplied to the input terminals of a total of eight logic gate circuits, of which there are eight input terminals. Above C
The second input terminal of the MOS NOR gate circuit NAG2 is supplied with an input signal I from a logic circuit (not shown), and the third input terminal thereof is supplied with an output signal of the CMOS NOR gate circuit N0GI. The first input terminal of this CMOS NOR gate circuit N0GI is connected to the CMOS
An output signal of the impark circuit N3 is supplied, and an input signal J is supplied to its second input terminal from a circuit (not shown) of the logic circuit.

Here, the CMOS inverter circuit N3 is the CMOS inverter circuit N3.
The circuit configuration is the same as that of the inverter circuits N1 to N2, and although not particularly limited, the basic cell BC20PMO8 region PM
It is composed of a first P-channel MO8F)i;T provided in IK and a [1 N-channel MO3FET provided in its NMO5 region NM1. At the same time, CMO
The S Nant gate circuit NAG2 has the same circuit configuration as the Nant gate circuit NAG1 described above, and includes, but is not particularly limited to, three P-channel MO8FETs provided in the PMO8 region PM2 of the basic cell BC2 and the NMO8 region NM.
It is composed of three N-channel MO8FETs provided in 2.

Next, as can be inferred from the above-mentioned Nant gate circuits NAGI and NiO2, the CMOS NOR gate circuit N0GI is provided in series between the source voltage VCC and the ground potential of the circuit. MO8
Two N-channel MO8Fs in parallel configuration with FETs
In this example, two P-channel MO8FEs constitute a CMOS NOR gate circuit N0Gl, including ET.
T is not particularly limited, but is the PM of the basic cell BC2.
It is composed of second and 1g3 P-channel MO8FETs provided in the O8 region PMI, and second and third N-channel MO8FETs provided in the 70NMO8 region NMI.

B1-CMOSMOS-to circuit BNO1 is on the axis of Fig. 6)
As shown in , the circuit power supply t! The basic configuration is two output transistors TI and T2 arranged in a totem pole configuration between EVcc and ground potential. In the preceding stage of the output transistor T1, there are three P-channel MO8FETs Q22 to Q2 that constitute a CMOS NOR gate circuit.
4 and 3 N-channel MO3FETs Q25~Q27
are provided, and between the collector and pace of the output transistor T2, three N-channel MO8FETs Q28 to Q30 whose source/drain paths are in parallel form are provided.
is provided. Further, one N-channel MO8FETQ31 whose gate is coupled to the collector of the output transistor T2 is provided between the base of the output transistor T2 and the circuit ground potential GND. These transistors T1 and T2 and each MO8FETQ22
~Q31 is the PMO8 area PM3 and N of the basic cell BC2
It is constituted by each circuit element provided in MO8 region N region N-3NM5 and bipolar transistor regions BTI and BT2. In the embodiment of FIG. 3, B1-
Since the fan-out fo of the CMOS NOR gate circuit BNOI is 8, the output transistors TI and T2 have
A pair of output transistors T3 and T4 are each provided in parallel configuration. Needless to say, these transistors T3 and T4 are formed by a pair of biborder 2 transistors provided in the bipolar 2 transistor regions BT3 and BT4 of the basic cell BC2. The basic cell BC shown in FIG.
For individual use [The wiring state is shown when configured. The t-source wiring Vcc and GND shown in the figure can be formed of first-layer aluminum wiring. Furthermore, connections between circuit elements can be formed using first-layer aluminum wiring, second-layer aluminum wiring, and the like.

In the above, an example has been described in which the two bibor transistors T1 and T3 (T2 and T4) are formed individually and connected in parallel, but this can be changed as shown in FIG. 6(e). That is, two emitters E1 and B2 may be provided and connected to one bipolar transistor BiP.

FIG. 6(6) shows an example of a layout diagram of the bipolar transistor BiF of FIG. 6(C). As can be seen from the figure, the bipolar transistor BIP includes a pace region B of Pm formed in the collector region C of the N-type and two N+ emitter regions E1. It can be formed to include B2.

As described above, the gate array of this embodiment includes a plurality of basic cells BC arranged in a grid pattern.

These basic cells BC are a three-person powered 0MO8 logic gate circuit, a two-person powered 0MO8wI logic gate circuit, or a CMOS inverter circuit (in other words,
1 input CMO8lil! ! 2 sets of first cells configured by combining 5 gate circuits) and a B1-CMOS inverter circuit (in other words, a 1-input 81-CMO8 logic gate circuit or B1-CMOS inverter circuit powered by two or three people)
a pair of bipolar transistors that are selectively used when a relatively large driving capability is required for the B1.0 MO8 logic gate circuit, each comprising a set of second cells constituting a complex logic gate circuit; Includes each.

The transmission delay time tpd of the CMO3 logic gate circuit is the seventh
As shown in the figure, when the fan act fo is small and the load capacity CL is made relatively small, B1・0MO8
It is made smaller compared to a logic gate circuit, and its load capacity [C
When L is made relatively large, it is conversely made large compared to the 81.CMO8 logic field gate circuit. On the other hand, B1-0M
The transmission delay time tpd of the O8 logic gate circuit exhibits similar load dependence as the output transistor size ES of the O8 logic gate circuit is made smaller. Therefore, in the logic circuit shown in FIG.
As shown in FIG. In addition, the Nant gate circuit BNAI
Like the NOR gate circuit BNOI, its load capacitance CL
A logic gate circuit that requires a relatively large number of fan acts such that, for example, exceeds cb is connected to the second
It is composed of cells. Furthermore, Noah gate circuit B
For a B1/CMO8 composite logic gate circuit, such as the NOI, which requires eight fan-outs whose load capacitance tcL exceeds Cc, the two output transistors, which are in a totem pole configuration, are each configured in parallel. The driving capability is increased by increasing the emitter area ratio ES.

In other words, the transmission delay time tp of the 0MO8 logic gate circuit
d(MOS) is expressed as shown below.

jpd(MO5)-t□+Vx,! -C/ID ・
・・・・・・・・・・・・ (1) VLy: Logic threshold ID: MO8 drain 1! Flow to: Delay time independent of load capacitance C1, X/I
Contains a function of D, where X indicates a positive real number.

Average transmission delay time tp of B1/0MO8 logic gate circuit
d(B I CMO5) (Tomi(tPIIL+tPLH
)/2) is.

It is expressed as the following formula.

tpd (BiCMO5)-ts◆vLT-CL/(n
β・ID)...(2) VLT: Logic threshold ID: Drain current β of MO5: Common emitter current amplification factor of bipolar transistor t□: Y(n) with delay time independent of load capacitance C,
/2ID It is expressed as the sum of Z(n)/n-β-ID.

n: emitter area, for example, emitter area ratio when IX3μd is 1; Y(n) and 2(b) are expressed as shown below.

Y(n)Vmi+ (2n Ccm◆2nCmm◆CH
I◆CPD) 10VLT (4n Ccm+ 2Cpo
)71g-VLt (n Ctub “CN”)
Vm: Base voltage of bipolar transistor.

Ccm: Collector-base capacitance of bipolar 2 transistor.

CB11: Base-emitter capacitance of Bibo 2-transistor.

C5ub: Capacitance between the director and the substrate of Pipo2 transistor.

CPD: Drain capacitance of PMO8FET.

CHD: Drain capacitance of NMO8FET.

C) fil: Source capacitance of NMOS FET.

These capacitances CCI to CN8 correspond to parasitic capacitances tccms to CHI shown in FIG. 12, which will be described later.

In the above, the capacity fccm is.

Cc+s-CcitxCcms and 1 capacity CIN is Cmx
“Corresponds to Cm1s = Caws.

In addition, the conditions are: ambient temperature Ta = 25°C 1sVCC"
' s v , MOSFET is, for example, 1.
It is formed by a 3 μm process, and its gate length is 1.
2 μm, and its gate width is 30 μm.

On the other hand, a bipolar transistor has an emitter area of 1×
The 3 μm's internal frequency is 70 Hz and the ground current amplification factor is 100.

As can be easily understood from the above equation (1), the transmission delay time tpd (MOS) of the 0M08 circuit increases as the drain current 1o, that is, the conductance gm increases, the slope (sof) (V
ht-CL/ID) decreases. On the other hand, Equation 1 (as you can understand from the smell), the transmission delay time tpd (B1-CMOS) of the B1/0M08 circuit increases as the emitter area ratio n of the bipolar transistor increases, its slope (vL
i-CL/n・β・) decreases. By the way, %n
The slope in the case of 5a2 (Bl-0MO8(ES:2)) is the slope of V2 in the case of Hw l, and in the case of nm4 (Bl-0MO8(ES:2))
The slope of i-0MO8(ES:4)) is 1/4 of the slope of nml.

Furthermore, in equation (1), the delay time to that does not depend on the load capacitance cL decreases as the drain current ID increases. Furthermore, in the equation (2), the delay time t1 that does not depend on the load capacitance Cm increases as the 8-star area ratio n increases, as shown in FIG.

Therefore, in the gate array according to the invention,
The type of logic circuit used is P-channel and N-channel MO8FET built into the gate array.
0M08 as determined by the device parameters of and the device parameters of Bibo 2 transistor.
The circuit is determined by the graph of the transmission delay time tp4 vs. load capacitance C of the first Bt-0M08 circuit with an area ratio of 1 and the circuit (jH2Bi-0M08 circuit with an area ratio of 1 or more). In other words, each logic Circuit load capacity tCL
The type of logic circuit that can charge and discharge the fastest
M08 circuit, 1st BI/0M08 circuit and jB2B1-
One of the 0M08 circuits is selected by referring to the graph of transmission delay time versus load capacitance CL.

In actual gate array design, CM08 circuit, 1B1- 0
Transfer delay time tpd vs. load capacity fjk Ct of the M08 circuit and the second Bi/0M08 circuit.

relationship is required. Then, the value of the load capacitance CL of the logic circuit of interest is calculated, and from the relationship between the transmission delay time tpd and the load capacitance cL of the corresponding logic circuit and the value of the load capacitance f Cx calculated above, An appropriate circuit configuration is selected.

As a result, in the gate array of this embodiment, the circuit elements of each basic cell BC are utilized without waste, thereby increasing the element utilization efficiency and, as a result, increasing the density. In addition, depending on the driving ability required for each logic gate circuit,
CMO8! The transmission delay time tpd is optimized by efficiently selecting the logical gate circuit or the Bi-CMO8 logic gate circuit, and by switching the drive capability of the Bi-CMO8 logic gate circuit in stages. As a result, the operation speed of logic circuits and the like formed by the gate array is increased.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a gate array. That is, (1) The basic cell of the gate array is basically a CMO
It includes a first cell used to configure an 8 logic gate circuit and a second cell used to basically configure a Bi-CMO8 logic gate circuit in a predetermined ratio, and a Bi-CbiO8 logic gate circuit. A pair of bipolar transistors are selectively used when a relatively large drive capability is required for the CMO5 logic gate circuit and the B1 and CMO8 logic gate circuits, thereby depending on the drive capability required for each logic gate circuit. The effect is that the logic gate circuit can be configured efficiently without waste.

(2) In the above item (1), according to the drive capacity required for the Bi-CMO8 logic gate circuit, the bipolar transistor is connected in parallel to the output transistor of the Bi-CMO8 composite logic gate circuit. The advantage is that the drive capacity can be optimized.

(3) Items (1) and (2) above provide the effect that the number of circuit elements in the gate array can be substantially reduced and its integration can be increased.

(4) Items (1) and (r) above provide the effect of reducing the transmission delay time of the logic circuit formed by the gate array and speeding up its operation.

In the above embodiment, one basic cell BCK including four bipolar 2 transistors BTI to BT4 was mainly described, but the present invention is not limited thereto, and one basic cell including two bipolar 2 transistors BCK A similar effect can also be achieved by devising the layout. Although some of the reference numerals in the drawings described below overlap with the reference numerals given to FIGS. g1 to 9, they should be understood as different. Another embodiment is shown, showing an optimal layout diagram of four basic cells l3C1-BC4, each containing two bipolar 2 transistors. 4 of the layout of basic cells BC1 to BC4 shown in the figure? Before explaining the image, first, the characteristics of the basic cell BCI shown in FIG. 10 will be explained.

The basic cell BCI consists of two bipolar transistors B1
and B2, a P-channel MO8FET region Pi and an N-channel MO8FET region N1 arranged between the bipolar transistors B1 and 82, and a P-channel MO8FET region M
O8FET regions P2 and B3 and N-channel type MO8F
In region ii Pi including ET regions N2 to N6, a gate array G consisting of two polysilicones is formed, and its pole G extends over region Nl. As a result, two PMO8FETs are placed in area P1, and two PMO8FETs are placed in area N1.
Two NMO5FETs are formed.

In addition, three gate electrodes made of polysilicon are formed in each of the regions P2 and B3, and these gate electrodes are connected to the regions N2 and B3. N4 and area N3. It will be extended to NS. As a result, regions P2 and B3 each have three PMO8FETs, and regions N2. N3. N4. N
Three NMO8FETs are formed in each of the transistors 5 and 5. Furthermore, one gate electrode G made of polysilicon is formed in region N6, and one NMO8FET is formed. FIG. 11 shows a diagram of the basic cell BCI.

The MOSFETs formed in the regions PI and NIK have a gate length of 1.2 μm and a gate width of 15 μm, respectively, and the MOSFETs formed in the regions P2. P3. The MOSFETs formed in N2 and N3 each have a gate length of 1.21'm e gate @30μ
It is assumed that m. Therefore, P and N in regions Pl and N1
The driving ability of the channel MO8FET is in the regions P2 and N2.
Or B3 and N3 P and N channel MOS F E
It is made smaller than the driving capacity of T. For example, MOS FET shown as Q100 to Q105 in FIG.
and B1. Consider a case where a circuit as shown in FIG. 12 is formed using a bipolar transistor indicated by B2. Is the gate width of CMOS inverter INV reduced? ,=PMO5FETQ100 and NMOSi'
Constructed by g'rqt O1. On the other hand, the bipolar CMOS inverter circuit BINV is
The output of the inverter INV drives its input. This bipolar CMOS inverter BINV is
Toten ball type bipolar output transistor B1
and B2. PMO8FETQI O2 and NMO8FE to drive the base of bipolar transistor B1
CMOS inverter composed of TQ103 and NMO8F that drives the base of bipolar transistor B2
Includes ETQI O4 and Q105.

A PMO whose source/drain path is connected between the power supply terminal VCC and the base of Bibo 2 transistor B10.
As the 8FET, a PMO8FETQ102 with a wide gate width is used. Since this PMO8FETQ102 has high driving ability, the capacitance parasitic to the base electrode of the bipolar transistor Bl, the base-collector fsJ]iccms
Base-emitter capacitance CIH and PMO8FETQI
02's drain capacitance CPD is charged at high speed. Output rise delay time tPL of bipolar CMO8 circuit
H is the common emitter ta of bipolar transistor B1
Amplification factor β and drain current mIp of PMO8FETQ102
A term that is inversely proportional to the product of o and proportional to the load capacity cL<
Tday÷÷・CLxeVbt: logic threshold) and a term inversely proportional to drain current IPD (A/Ipo-A: positive real number), therefore, output rise delay time tPL
H becomes smaller by increasing the drain current IPD of PMO8FETQ102, that is, by increasing the gate width of PMO8FETQI02.

On the other hand, the source/drain bus is connected between the output terminal out and the base of the bipolar transistor B2.
MO8FET is NMO8FETQI with wide gate width
04 is used. Since this NMO8FETQ104 has a high driving ability, the capacitance parasitic to the base electrode of the Bibo 2 transistor B2, the base-collector M capacitance tCca!
-Base-emitter capacitance Cl1m and NMO8FET
The source capacitance CHBe of Q104 is charged at high speed. Bipolar/CMO8 circuit output fall delay time tpn
z is 關CL s (β: bibolar transistor B
2 emitter grounded current amplification factor %IND: NMO8FET
Drain bus of Q104) and BA) rD (B: positive real number).
nL is the drain current N of NMO8FBTQI・04
Increasing D means that NMO8FgTQ104
The larger the gate width, the smaller the gate width. In addition, the above A and B are the above parasitic capacitances CCII, Cl1ll, Cp
o, CNl1. Can5. CIl*#Logic threshold VLT, Ivy ground current amplification factor β.

Collector-to-substrate capacitance t of Bibo 2 and transistor B2
It is expressed as a function of C8U II and the drain capacitance tCND of NMO8FETQ104.

On the other hand, an NMO5FET Q10 is provided between the base electrode of Bibo 2 transistor Bl and the ground potential GND.
NMO8FETQ10 provided between the base electrode of the transistor B2 and the ground potential GND.
5 is provided to discharge the capacitance parasitic to each base electrode, so its gate width may be made small.

As can be understood from the figure, the CMOS inverter INV
Since the output 0 of only drives the input of the bipolar/CMOS inverter BINV formed in the same basic cell BCI, its output load capacitance CLI is equal to the output load capacitance C of the bipolar/CMOS inverter BINV.
Assuming that L2 is a large value, it is considered to be a smaller value than the value of L2. Therefore, since the load capacitance CLI of CMOS inverter INV is small, CMOS
The transmission delay time tpd of the inverter INV is:

It can be considered that the load capacitance CL shown in FIG. 7 is determined by the CMO8 characteristics of the portion smaller than Ca. In other words, since the output load capacitance CLI of the CMOS inverter INV is reduced, even if the driving capacity of the P and N MO8FETs constituting the CMOS inverter INV is reduced, that is, even if the gate width is reduced. , CMOS inverter INV
The transmission delay time tpd is considered to be an acceptably small value. In other words, the area P
MOSFET with small gate width formed in 1 and N1
The transmission delay time characteristics of the 0M05 circuit can be effectively utilized by designing the circuit so that the 0M08 circuit configured as shown in FIG.

In this way, a plurality of MOS FETs with narrow gate widths are actively incorporated inside the basic cell BCI, and their M
By specifying the application of the 0M03 circuit formed from OSFETs, an optimal design with respect to propagation delay time is performed. Furthermore, by arranging the MOSFET with a narrow gate width in the region between the bipolar transistors B1 and B2 in the basic cell BCI, the area occupied by the basic cell BCI can be effectively utilized.

The basic cell BCI is formed to be suitable for a wiring channel-less wrinkled gate array, so as shown in FIG.
It is provided within I. The wiring provided in the basic cell BCI is mainly the first layer full ξ Ecum wiring (ALI) and/or
Alternatively, it is desirable to use polysilicon wiring, because as shown in the Mto diagram, the power supply voltage line Vcc and ground potential line GND formed by the first layer aluminum wiring (ALI) extend above and below the basic cell BCI. Because He exists. Furthermore, when the signal input line to the basic cell BC1 and the signal output line from the basic cell BCI cross the power supply voltage line vcc or the ground potential line GND, those input/output lines are formed with second-layer aluminum wiring. be done. If the input/output lines do not intersect with the VCC line or the GND line, that is, if they are provided perpendicularly to the polysilicon gate electrode formed in the basic cell BCI, those input/output lines are connected to the first layer aluminum wiring. and/or formed of polysilicon wiring.

Next, the layout of each element in the basic cell Bl will be explained with reference to FIG. 1θ. Bipolar transistors B1 and B2 are arranged above and below within basic cell BC1, and are easily connected to power supply line VCC and ground line GND. Due to this, biport 2 to 2
Since the connection between the collector C of the transistor B1 and the power supply line Vcc and the connection between the emitter E of the bipolar transistor B2 and the ground line GND are made over short distances, the collector parasitic resistance of the bipolar transistor B1 and the bipolar transistor B2 caused by the connection wiring are reduced. The main resistance of the emitter is reduced. Similarly, MO with widened gate width
Region P2°B3 and region N2.B3 where SFETs are provided. N
3 is also arranged near the power supply line VCC and the ground line GND. Thereby, those areas P2. P3.
When forming an 0M08 circuit using the N2 and N3 MOSFETs, the source regions of these MOSFETs can be connected to the power supply line VCC or the ground line GND over a short distance, so that the source resistance is reduced. Furthermore, area P2 (B3) and area N4 (N5).

The layout of region N2 (N3) and region N6 is a bipolar CMOS inverter/B as shown in FIG.
1. NY) 2) SpQ 102~Q 105M)
You will notice that the connection relationship is similar to that of CA D when configuring a bipolar CMO8 logic circuit.
d@51gm) facilitates wiring design.

Moreover, the above wiring area WA is a commercially available KPMO8F.
ET formation region P1. The distance between B2 and B3 and the NMO8FET formation regions Nl to N6 is widened.

Therefore, the latch-up phenomenon can be prevented. Furthermore, bipolar transistor Bl and regions P1 and B2
between and bipolar 2 transistor B2 and regions Nl, N2
A wiring area WA is also provided between N6 and N6. Even if minority carriers are injected into the substrate due to saturation of the bibolar transistors B1 and B2, the influence on the MOSFET is reduced due to the presence of the wiring area WA.

Also, each Biborad 2 Insister Bl.

The base electrode B of B2 is the MOSFET coupled to it.
Area P3 (B2), N6 so that the connection with
．． It is provided in the direction in which N5 (N2) exists.

Next, the mutual layout of the basic cells BCI to BC4 will be explained using diagram @10. That is, the basic cell BCI and the basic cell BC2 have mirror symmetry with respect to the two-dot chain line X in the figure. As a result, bipolar transistors B1 . B2 and the bipolar transistor B3 in basic cell BCZ. B4 is placed nearby. Furthermore, the basic cells BCI, BC2 and the basic cell BC
3. BO2 has mirror symmetry with respect to the two-dot chain line Y in the figure. These four basic cells BCI to BC4 are considered as a unit cell block UCB. The unit cell blocks UCB are regularly laid out in a grid pattern in an internal logic circuit forming area on the semiconductor substrate SUB to form a master chip of the gate array. By making the basic cells BC1, BC2 and the basic cells BC3, BO2 mirror-symmetrical with respect to the two-dot chain line Y, the MOSFETs and bipolar transistors to be connected to the ground line GND in each basic cell are connected to the unit cell block UCB. They are gathered in the center of the area, that is, in the area along the two-dot chain line Y. Therefore, as shown in the figure, if the ground 2in GND is formed along the line YK, the two basic cells BCI and BO2 (
Since one ground line GND can be used in common for BO2 and BO2)K, the number of ground twin GNDs required is reduced. Power supply 2 in Vccs, Vcc
The geese are arranged above and below the unit cell block UCB, respectively, as shown. Thereby, it is possible to prevent the mutual conductance gm from decreasing, which would occur if the power supply wiring passes over the MOSFET.

These power supply 2-in Vcc1e Vcc line and ground line GND are formed of the first layer aluminum wiring ALI.

Next, an example of how the basic cells BC1 and BC2 shown in FIG. 1O are utilized will be explained based on FIG. 13(&) and Φ-n.

Figure 13 (&) shows the circuit of Figure 13 (b) as a basic cell BC.
O8F between P and N channels built into 1 and BO2
In FIG. 0, which is an example of implementation using ET and bipolar transistors, the portion indicated by a dotted line indicates aluminum wiring and/or polysilicon wiring. The black circle is the connection between the gate and wiring, MOSFET
Also, reference symbol A indicates the connection between the source, drain, base, emitter, and collector of a bipolar transistor and wiring (including Vcc and GND lines).

The white circles labeled B, C, D, E, F, G, and out indicate signal input/output terminals. Since the logical conditions of the signals and output signals are not directly related to the present invention, a detailed explanation thereof will be omitted. Also, Fig. 13(A)
6CMO5 (y barter times M) is shown in Figure 13).
CIV1. CIV2゜CIV3,0MO8sy)”DO
cND, CMOS NOR circuit CNRI, CNR2 and B
Since reference symbols corresponding to the respective forming parts of the ICMOS NAND circuit BND are given, a detailed explanation will not be given, but the characteristic points will be described below.

As can be understood from FIG. 13-), input terminals A to F and G are connected to wiring areas WA (first
0) above, the basic cell BCI.

K is connected to the gate electrode in BO2.

Further, the output terminal out is taken out from the wiring formed in the wiring area WA.

Thereby, the signal delay time due to the input/output wiring resistance can be suppressed as much as possible. Note that input wiring for inputs C and D is not shown in order to prevent the drawing from becoming complicated.

Furthermore, in the basic cell BC2, CMOS inverter circuits CIVI to CIV"3 and a CMOS NAND circuit CN
D is configured, the bipolar transistors B3 and B4 in the basic cell BC2 are connected to the above 0M08 circuits CIVI to CIV3 and CN made in the basic cell BC2.
However, by making basic cell BCI and basic cell BC2 mirror-symmetrical with respect to line X as shown in FIG. 2 registers Bl and B3 (B2
and 84) are laid out close to each other, so that the transistor B
Parallel connection of 1(B2) and 83(B4) is made possible by the short wiring length. In addition, in the same figure (a), B1CMO
It is assumed that the S NAND circuit BND has a large number of fan-outs, but if the number of 7 unacts is small,
Bipolar transistors Bl (B2) and 83 (B
4) does not need to be connected in parallel.

Therefore, the basic cells BC1, BO shown in FIG.
Layout arrangement 2 makes it possible to use a semiconductor element such as a MOSFET bipolar transistor that is not used in one basic cell as part of a circuit configured in another basic cell. In other words, one logic circuit can be formed by a semiconductor element in one basic cell and a semiconductor element in another basic cell. This makes it possible to effectively utilize the semiconductor elements within the basic cell. Although the bipolar 2 transistors B1 to B4 have been described above, the MOS formed in the regions PI, Nl, PI, Nl
The same is possible for FET, and the areas Pi, Nl, Pi
, Nl P and N channel MO8FETs are used to form a three-manpower CMOS NOR circuit CRN.

Referring again to FIG. 13(a), the output of the CMOS inverter CIVI drives the input of the CMOS NOR circuit CNR2 of the basic cell BCI.

In other words, the output wiring M of the CMOS inverter CIVI extends from the right end of the basic cell BC2 to the left end of the basic cell BCI, and the output load capacitance cL is considered to be relatively large, but the CMOS inverter CIVI is a PMO8FET with a wide gate width. and NMO8FET, the propagation delay time can be made relatively small.

A MOS FET with a wide gate width can also be used for such applications.

FIG. 14 shows z of the basic cell B03 shown in FIG.
-z' shows the old cross-sectional view.

As shown in the figure, this structure includes a gate 32. made of polycrystalline silicon. N-well 50 and N-well 52.
P type diffusion layer 35 as source/drain of PMO8FET. N as source and drain of NMO5FET
type diffusion layer 36°N type diffusion layer 40 constituting the emitter of the NPN bipolar transistor B5. The bipolar transistor B5 includes a P-type diffusion layer 41 forming the base and an N-type diffusion layer 42 forming the collector thereof.

This structure can be formed using well-known semiconductor manufacturing techniques. For example, P-type isolation regions 102 and 102'' can be formed in semiconductor substrate 100 by boron diffusion into semiconductor substrate 100, while N+-type buried regions !81, 101' and 101
” can be formed by diffusion (introduction) of antimony into the semiconductor substrate 100. Diffusion of these dopants at 1200° C. for 40 minutes, for example, in the regions 101, 101, i02 and 102
available for initial formation. After that, N-''
The epitaxial layer is formed using a common epitaxial deposition process (for example, at 970°C).

10 minutes), the zero-order N
W quell regions 50 and 103 and P quell regions 31 may be formed in the epitaxial layer by ion implantation of phosphorous and boron, respectively. to LO
60KeV, dose f4. using CO8 technology S i O * BJA as an ion implantation mask. □X
In order to perform boron ion implantation of 10 B atoms/i, a nitride film (S 31
125KeV using N4) as an ion implantation mask.
, dose amount 3×10”at.

ms/i. This ion implantation process is performed at, for example, 1000°C x 30°C.
A diffusion step of 0 minutes can be followed, so that the respective regions 101, 102, etc. and the Fell region 5
0.51 and 103 are expanded to provide the structure shown in FIG. Following this, nine MOS and two bibor transistors are formed in the open areas of the 5103 layer 70 using conventional transistor formation techniques. Finally, a phosphorus-silicate glass (PSG) 31%80 coats the device for protection and is deposited at 480° C. for 10 minutes.

Note that reference number 42 is an N wire connecting the aluminum wire 60 as a collector electrode and the N+ type buried layer 101 with low resistance.
This is an "ffi layer. Reference number 90 is N+ type polycrystalline silicon, which is used to form an N+ emitter region. Aluminum interconnections 60 formed in PMO3 and NMO8 are used as source/drain electrodes. Furthermore, the 14th
The figure corresponds to a cross-sectional view in which aluminum wiring 60 has been provided. In addition, bipolar transistor B5
Although the pace electrode is not shown in the figure, it is actually present.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, in FIG. 1, the basic cells BC do not all have to have the same circuit configuration. and the second cells, that is, the PMOS region PM3, the NMO8 regions NM3 to NM5, and the bipolar transistor regions BTI to BT4, are determined by the ratio of the C included in the logic circuit constituted by this gate array.
It can be changed appropriately depending on the ratio of the MO8 logic gate circuit and the bipolar logic gate circuit. In addition, P channel MO8FE included in each PMO8 area and NMO8 area
The number of T- and N-channel MO8FETs can vary, such as two or four, depending on the average number of inputs of the logic gate circuits included in the logic circuit constituted by this gate array, for example. The NMO8 region NM5 may be, for example, a resistor means, or if a larger driving capability is required for the Bi-CMO8 composite logic gate circuit, the number of bipolar transistor regions may be increased. In this case, the basic cells BC do not need to be arranged in a grid pattern, and the gate array can be arranged in the basic cells B as described above.
In FIG. 3, the second cell of each basic cell BC may partially contain a CMOS logic gate circuit, if a B1 CMO8 logic gate circuit is not required. Furthermore, the configuration of the basic cell BC shown in FIG.
Various embodiments can be adopted, such as the specific circuit configuration of the Bz-CMO8 logic gate circuit shown in , (b).

In the above explanation, the invention made by the present inventor has mainly been applied to a logic circuit constituted by a Bi-CMOS gate array, which is the background of the invention, but it is not limited thereto. For example, it can be applied to various digital devices such as microcombustion devices configured with similar gate arrays.
The present invention provides at least a CMO8 logic gate circuit and a B1
- It can be widely applied to gate array integrated circuits having a basic configuration of CMO8 logic gate circuits or digital devices constructed from such gate array integrated circuits.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. In other words, gate array integrated circuits are basically CM
It includes a first cell used to configure an O8 logic gate circuit and a second cell used to basically configure an 81-CMO8 composite logic gate circuit in a predetermined ratio, and also includes a B1 CMO8 logic gate. It includes a pair of bipolar transistors that are selectively used when a relatively large drive capacity is required in the circuit, and is configured with multiple cell masters arranged in a grid, so it is optimized according to the drive capacity. CMO8 logic gate circuit and Bl
- A CMO8 composite logic gate circuit can be configured efficiently without waste. This makes it possible to reduce the number of circuit elements in gate array integrated circuits and increase their integration density, as well as reduce the transmission delay time of logic circuits, etc. configured by gate array integrated circuits, and speed up their operation. It is possible.

[Brief explanation of drawings]

FIG. 1 is a layout diagram showing an embodiment of a basic cell included in a gate array to which the present invention is applied, and FIG. 2 is a plan view showing an embodiment of a gate array including the basic cell of FIG. 1. , FIG. 3 is a circuit diagram partially showing an embodiment of the logic circuit constituted by the gate array of FIG. 2, and FIG.
FIG. 5 is a circuit diagram showing an example of a CMOS inverter circuit included in the logic circuit of FIG. 3; FIG. 5 is a circuit diagram showing an example of a CMOS Nant gate circuit included in the logic circuit of FIG. 3; FIG. 6(a) shows the Bi/C included in the logic circuit of FIG.
The circuit diagram showing an example of the MOS NAND gate circuit BNAI (Figure 6) is the B1-CMOS NOR circuit BNO in Figure 3.
6(c) shows a modified diagram of the bipolar transistor, FIG. 6(d) shows a device plan view of FIG. 6(c), and FIG. 7 shows a CMO8 logic circuit diagram. Gate circuit and B1/CMO
8 is a characteristic diagram showing the relationship between load capacitance and propagation delay time of a composite logic gate circuit, FIG. 8 is an equivalent diagram of the basic cell BC in FIG. 1, and FIG. 9 is an equivalent diagram shown in FIG. 8. FIG. 10 shows a layout diagram of the basic cells BCI to BC4, and FIG. 11 shows the layout of the basic cells BCI in FIG. 10. The equivalent diagram is shown, ff112 is an explanatory diagram showing an example of use of each MO8FET and bipolar transistor in the basic cell BCI shown in FIGS. 10 and 11, and FIG. 13(a) is
An example of the connection diagram of the basic cells BC1 and BC2 in FIG. 10 is shown.
Showing the circuit diagram formed by CI, BC2, the 13th
Figure (c) shows the basic cell Bc1. MOSFET in BC2
FIG. 14 shows a cross-sectional view of the device along the line zz' in FIG. 10. BC, BCl, BC2...basic cell, PMI to PM3
... PMO8 region, NMI to NM5... NMO8 region, BTI to BT4... bipolar transistor region, G... gate, SUB... semiconductor substrate. N1~N4...CMOS inverter circuit, NAGl~
NAG2...CMOS Nant gate circuit, N0G1.
・・CMOS NOR gate circuit, BNAl...Bi・C
MOS Nant gate circuit, BNOl...B1/CMO
S Noah gate circuit. Q1~Q7...P channel MO8FET, Q11~
Q21...N channel MO8FET%Tl~T4・
...NPN type bipolar transistor. + Fig. 8 Fig. 9 Fig. 10 Fig. 1:lLj t5L4 No. 11
Figure 12 Figure 14

Claims (1)

[Claims] 1. A semiconductor integrated circuit includes: a semiconductor substrate having a main surface; and at least a pair of basic cells formed on the main surface, each of the basic cells having a rectangular shape. , and includes a pair of bipolar transistors and a plurality of MOSSFTs, the pair of bipolar transistors included in one of the basic cells.
The transistor is disposed close to one side of the basic cell, and is connected to the pair of bipolar transistors included in the other basic cell.
A semiconductor integrated circuit characterized in that the transistors are arranged in mirror-symmetrical positions with respect to the certain side, with the pair of bipolar transistors in the one basic cell being arranged in mirror symmetry.