JPH02309821A - Fano type successive decoder - Google Patents

Abstract

PURPOSE:To improve the error correction capability by providing a forward replica exclusive OR circuit (EX-OR) between 2-way flip-flops(FFs), providing a replica memory, storing a backward replica into the replica memory and reading the replica. CONSTITUTION:A replica memory 5 is provided and a forward replica generating circuit of an internal code section 3 is constituted by providing a forward replica EX-OR between 2-way FFs. When a forward replica is generated, a backward replica is generated and stored in the replica memory 5 and the backward replica stored in the replica memory 5 is read and given to a path retrieval section 2 via the internal code section 3. Thus, even when a generation matrix at the sender side is prolonged to improve the error correction capability, the internal processing time is quickened to increase the error correction capability.

Description

[Detailed Description of the Invention] [Summary] Regarding the Fano-type sequential decoder, ■The processing time of forward replicas and backward replicas between clocks can be shortened, the internal processing time can be shortened, and the generation matrix on the transmitting side can therefore be lengthened. With the aim of providing a fan-type sequential decoder that can improve error correction performance, a replica memory is provided, and the forward replica generation circuit of the internal code section is replaced with an exclusive OR circuit (hereinafter referred to as E) for the forward replica.
An X-OR) is provided between the bidirectional flip-flops (hereinafter referred to as bidirectional FFs), and when a forward replica is generated in the internal code section, a backward replica is generated at that time. A backward replica stored in the replica memory is read out from the replica memory and inputted to the internal code section, and a forward replica and a backward replica are provided from the internal code section to the path search section.

[Industrial Application Field] The present invention transmits data on the transmitting side and a signal in which the data is made into a generation matrix by an encoder such as a Wonzencraft type encoder or a Matsushi type encoder, and approximates the data on the receiving side. This paper relates to an improvement of a fan-type sequential decoder that realizes maximum likelihood decoding.

As a fan-type sequential decoder, internal operation can be made faster,
High correction ability is desirable.

[Conventional technology]

FIG. 7 is a block diagram of a conventional fan-type sequential decoder, and FIG. 8 is a block diagram of a conventional internal code section.

1 in FIG. 7 is a symbol memory, which contains data on the transmitting side and
A signal obtained by converting the data into a generation matrix by an encoder is received and stored.

Reference numeral 2 denotes a path search unit which performs calculations on the received signal read out from the symbol memory 1 and the forward replica or backward replica generated by the internal code unit 3' to find the most probable decoded data, bit by bit. It is given to

3 is an internal code section, which converts the n bits determined by the generation matrix of the transmitting side of the decoded data obtained by the path search section 2 into the forward,
The path search unit 2 stores the data in a shift register consisting of bidirectional FFs that can change the direction backward, encodes it using a coefficient multiplier and EX-OR, and uses it as a forward replica and a backward replica.
The decoded data of n bits which have been applied to the path memory 4 and accumulated is sequentially applied bit by bit to the path memory 4.

4 is a path memory which stores the decoded data from the internal code section 3' and outputs it sequentially when the memory capacity is full.

At time t0, the fan-type sequential decoder using this fan algorithm sequentially directs the most likely decoded data found by the path search unit 2 one bit at a time forward and backward into the internal code unit 3''. The most probable decoded data at time t1, one clock minute after time t0, is sequentially applied to an n-bit shift register consisting of bidirectional FFs that can be converted, and using the forward replica generated by the internal code section 3°. Search for (this is called looking forward).

However, if it is determined at time t1 that there is an error in the decoded data before time tl, in order to go back to time t or earlier, the decoded data is sequentially read out bit by bit from the path memory 4, and the internal code section 3 It is encoded in the path search unit 2 as a backward replica (this is referred to as looking backward).

In this way, the motion of looking forward and the motion of looking back are repeated, and the most probable data string is output from the path memory 4 as the decoding result.

The control of each part described above is performed using the control block diagram 6.

Next, the internal code section 3' will be explained using FIG. 8.

Figure 8 shows that the generation matrix in the encoder on the transmitting side is A (x) =
It shows the internal code part in the case of a0+a+x+azX"+HH, a, x", and the constraint length is n.

In the figure, reference numeral 11 denotes an EX-OR for the forward replica, which has the number of taps of the generation matrix minus two, and numeral 12 denotes an EX-OR for the backward replica, which has the number of taps of the generation matrix minus one.

Reference numeral 10 denotes a bidirectional FF, which has the same number of taps as the generation matrix and constitutes a shift register, and as shown in FIG.
1, and the selector 21 selects the A side when moving forward, and selects the B side when moving backward.

13 is a forward replica multiplier that multiplies by 1 or O corresponding to the coefficient of the generator matrix on the transmitting side; the number of taps of the generator matrix -
There is one.

Reference numeral 14 denotes a backward replica multiplier that multiplies the coefficients of the generator matrix on the transmitting side by 1 or O, and has the same number of taps as the generator matrix.

Then, when generating a forward replica, the bidirectional FF10 selects the A side with the selector 21, and the FF of each bidirectional FF10
The data stored in 20 is multiplied by a predetermined 1 or O in multiplier 13, exclusive ORed in EX-ORII, and the result is provided to bus search unit 2.

In addition, the forward replica at time t1 and the probable data obtained by searching at that time are multiplied by 1 or O by the multiplier 11 corresponding to the coefficient 37, and the result is one EX-OR.
The exclusive OR at step 12 is equal to the backward replica at time t2, and this is given to the bus search unit 2 as the backward replica.

Also, when generating a previous backward replica, bidirectional FF10
The selector 21 selects the B side, and the data stored in the FF 20 and the data sequentially read from the path memory 4 and stored in the FF 20 of the bidirectional FF10 are multiplied by a predetermined 1 or 0 in the multiplier 14, and EX - OR12 performs an exclusive OR and provides it to the bus search unit 2.

[Problems to be solved by the invention] In order to improve the error correction capability of the Fano-type sequential decoder,
Although it is necessary to lengthen the generation matrix on the transmitting side and increase the constraint length, the number of EX-OR IIs for forward replicas and EX-ORs 12 (7) for backward replicas increases as a result of the confusion.

When this number increases, the processing time by the EX-OR 11 for the forward replica and the EX-OR 12 for the backward replica becomes longer, and this processing must be performed within one clock, making it impossible to speed up the internal processing.

That is, in the internal code section of the conventional example, there is a problem that the generation matrix on the transmitting side is made too long and the error correction capability cannot be improved.

The present invention is a Fano-type sequential method that can shorten the processing time of forward replicas and backward replicas within one clock, shorten the internal processing time, and therefore lengthen the generation matrix on the transmitting side and increase the error correction ability. The purpose is to provide a decoder.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

As shown in FIG. 1, there is a symbol memory 1 that receives and stores data on the transmitting side and a signal in which the data is made into a generation matrix by an encoder, a received signal read out from the symbol memory 1, and an internal encoder 3. An example of transmission of the decoded data obtained by the bus search unit 2, which calculates the most probable decoded data by performing calculations on the forward replica or backward replica generated by the bus search unit 2 and supplies it bit by bit to the internal code unit 3. The n bits determined by the generation matrix are stored in a shift register consisting of bidirectional FFs that can change direction forward and backward, encoded using a coefficient multiplier and an exclusive OR circuit, and are sent to the bus search unit as a forward replica and a backward replica. 2, and a bus memory 4 which stores the decoded data from the internal code section 3 and sequentially outputs it. In the type sequential decoder, it is assumed that a replica memory 5 is provided, and a forward replica generation circuit of the internal code section 3 is provided with an EX-OR for the forward replica between the two-way FF0.

When the internal code unit 3 generates a forward replica, a backward replica at that time is generated and is stored in the replica memory 5.
The stored backward replica is read from the replica memory 5 and inputted to the internal code section 3, and the forward replica and backward replica are provided from the internal code section 3 to the bus search section 2.

[For production]

By providing a forward replica EX-OR between two-way FF0, only one EX-OR process can be performed during one clock, and the forward replica generation circuit As for EX-O for forward replica
R is provided between the bidirectional FFs, and in order to increase the error correction ability, the generation matrix on the transmitting side becomes longer, and the EX-O for forward replicas becomes longer.
Even if the number of R increases, the internal processing time can be made faster.

Also, the backward replica generated at the internal code section 3 at the time is based on the forward replica generated at time t-1, one clock earlier, and the probable data obtained by the path search section 2 at that time. Focusing on the point that it is equal to the exclusive OR of the coefficient a corresponding to the n-th bit of the code multiplied by l or O by a multiplier, when a forward replica is generated, a backward replica is generated. , the backward replica is stored in the replica memory 5, and the stored backward replica is read out from the replica memory 5 and sent to the path search section 2 via the internal code section 3.
By giving , the internal processing time can be increased even if the generation matrix on the transmitting side becomes long in order to improve the error correction ability.

That is, it is possible to lengthen the generation matrix on the transmitting side and increase the error correction capability of the Fano-type sequential decoder.

〔Example〕

FIG. 2 is a block diagram showing the configuration of a Fano sequential decoder according to an embodiment of the present invention, FIG. 3 is a block diagram of a first internal code section according to an embodiment of the present invention, and FIG. 4 is an implementation of the present invention. FIG. 5 is a block diagram of the second internal code section of the example, FIG. 5 is a block diagram of the third internal code section of the embodiment of the present invention, and FIG. 6 is a block diagram of the fourth internal code section of the embodiment of the present invention. It is a diagram.

Figure 2 shows the path memory 4 of the principle block diagram shown in Figure 1.
The replica memory 5 and the replica memory 5 are provided in one memory 7. Since the replica memory and the path memory read and write data at the same timing, the 2-bit wide R
The control section 6 controls each section, and the operations other than the internal code section 3 are the same as those already explained in the conventional example, so a description of the operations will be omitted.

By providing the replica memory 5, the configuration of the internal code section 3 is changed from the conventional one, and it is conceivable that the configuration is based on a Matsushi type encoder and a Wonzencraft type encoder. The internal code section 3 will be explained below.

3 and 4 are constructed based on a Matsushi type encoder, and FIGS. 5 and 6 are constructed based on a Wonzencraft type encoder.

The generation matrix of the encoder on the transmitting side in the cases of FIGS. 3 and 5 is A (x) = 3o + alx + azx"+ .
・The constraint length is n+1 for a and x', and the generation matrix of the encoder on the transmitting side in the cases of FIGS. 4 and 6 is A(x) −1
+x"+x'+x'+x'+x'+x" and the constraint length is 9, which is basically the same as in Figures 3 and 5, so the following explanation will be based on Figures 3 and 5. The diagram will be explained.

Also, in the figure, 30.31 to 35 and 60.61 are bidirectional FFs shown in FIG. multiplier,
40.41~44,90°95 is EX-OR,47,4
8, 64, 65 are FF, 45.46, 62.63 are selectors, select side A when moving forward, and select side B when moving backwards.
Choose a side.

In the case of FIGS. 3 and 4, EX-R90, 95, which takes the exclusive OR with the output of the multiplier 10.80, is used as a bidirectional FF.
60, so that one EX-OR process only needs to be performed during one clock, thereby shortening the internal processing time.

A bidirectional FF 60 and a multiplier 70. EX-OR9
0 is used to generate a forward replica, and it is given to the path search unit 2 via the selector 62, and at that time, the multiplier 71 and E
A backward replica is generated using the X-OR 90, provided to the path search unit 2 via the selector 63, and written to the replica memory 5 via the bidirectional FF 60.

The rear replica read from the replica memory 5 is the bidirectional FF 60. FF65. It is given to the path search unit 2 via the selector 63, and at this time it is sent to the multiplier 80 (equivalent to a coefficient of 80).
The output of is multiplied by 1 or 0 in the multiplier 81, and the exclusive OR of this multiplied value and the backward replica is performed by EX-OR9.
5, and bidirectional FF60. as a forward replica. FF
64. It is provided to the path search unit 2 via the selector 62.

Note that in this internal code section, the multiplier 80 (corresponding to coefficient a0)
The output is the decoded data to be sent reversely to the path search unit 2.

In this way, one of the forward replicas will be
Since only one EX-OR process has to be performed, even if the generation matrix becomes long, the internal processing time can be reduced.Also, since the backward replica only needs to be read from the replica memory 5, even if the generation matrix becomes long, the internal processing time can be increased. Since the processing time can be made faster and the generation matrix of the code section of the transmitter can be made longer, the error correction capability can be increased.

In Figures 5 and 6, E of the forward replica in one clock is shown.
In order to shorten the processing time by X-OR, the time t0
In the bidirectional FF 30 and the multiplier 50. EX-O
Using R40, A (x) = a, + a, x + az
x"10--°a n-2X sA (x) -1
+x2+x'+x'+x", and at time t, using bidirectional FF 31. Multiplier 51. EX-OR 41, B(x) = A (x) +a , -, xn-1, B
(x)=A(x)+x' is calculated and provided to the path search unit 2 as a forward replica via the selector 45, and at time t2, the bidirectional FF 32. Multiplier 52. EX-
Using OR42, G (x)=B (x)+anx”, G
(x) =B (x) +x' is calculated and given to the path search unit 2 as a backward replica, and is also written to the replica memory 5 as a backward replica by the bidirectional FF 33 at time t.

Also, when reading from replica memory 5, bidirectional FF3
3. The FF4B is given to the path search unit 2 as a backward replica via the selector 46, and at this time, the bidirectional FF30 (
The rear output of FF, -z) is multiplied by 1 or 0 in the multiplier 53, and the EX-OR 43 calculates the exclusive OR of this multiplied value and the rear output of the output 33.
．． It is provided to the path search unit 2 via the selector 45 as a forward replica.

In this way, the EX-OR required to generate a forward replica between one cross is no longer required because the EX-OR 41 is provided between the two-way FFs 31 and 32, and it is not as much as in the case of Fig. 3. However, it is possible to speed up the internal processing time.

As for the backward replica, as in the case of FIG. 3, it is only necessary to read it from the replica memory 5, so the internal processing time can be increased, and the generation matrix of the code section of the transmitter can be lengthened, so the error correction ability can be improved. It can be increased.

(Effects of the Invention) As explained in detail above, according to the present invention, if the EX-OR for the forward replica is provided between the two-way FF0 and the replica memory 5 is provided, the backward replicas are stored in the replica memory 5. Since the internal processing time can be increased and the generation matrix on the transmitting side can be made longer, the error correction capability can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block diagram showing the configuration of a Fano sequential decoder according to an embodiment of the present invention, and FIG. 3 is a block diagram of the first internal code section of an embodiment of the present invention. Block diagram: FIG. 4 is a block diagram of the second internal code section of the embodiment of the present invention; FIG. 5 is a block diagram of the third internal code section of the embodiment of the present invention; FIG. 6 is a block diagram of the third internal code section of the embodiment of the present invention. FIG. 7 is a block diagram of a conventional Fano sequential decoder; FIG. 8 is a block diagram of a conventional internal code section. In the figure, 1 is symbol memory, 2 is bus search section, 3 is internal code section, 4 is path memory, 5 is replica memory, 6 is control section, 7 is memory, 10.30.31 to 35, 60.61 is a bidirectional flip-flop, 13.14, 50. 51 to 54 are multipliers, 11.12,
40.41 to 44, 90.95 are exclusive OR circuits, 47.48, 64.65 are flip-flops, 45, .
46, 62, and 63 indicate selectors. :I hl.

Claims (1)

[Claims] A symbol memory (1) that receives and stores data on the transmitting side and a signal in which the data is generated as a generation matrix by an encoder; a received signal read from the symbol memory (1); a path search unit (2) that performs calculations on the forward replica or backward replica generated by the code unit (3) to obtain the most probable decoded data and supplies it bit by bit to the internal code unit (3); ) The n bits of the decoded data determined by the generation matrix on the transmitting side are stored in a shift register consisting of a bidirectional flip-flop that can change direction forward and backward, and are processed using a coefficient multiplier and an exclusive OR circuit. an internal code unit (3) that sequentially supplies the encoded n-bit decoded data to the path search unit 2 as a forward replica and a backward replica, and sequentially supplies the accumulated n-bit decoded data bit by bit to the path memory (4); and the internal code unit (3) In a Fano sequential decoder consisting of the path memory (4) which stores and sequentially outputs the decoded data of the An exclusive OR circuit for replicas is provided between the bidirectional flip-flops, and when a forward replica is generated in the internal code section (3), a backward replica is generated at that time and stored in the replica memory. (5)
The stored backward replica is read out from the replica memory (5) and inputted to the internal code section (3), and the forward replica and backward replica are sent from the internal code section (3) to the path search section ( 2) A Fano-type sequential decoder is characterized in that the following is applied.