JPH02307143A - Constitution system for address conversion buffer - Google Patents

Abstract

PURPOSE:To decide an address conversion buffer (TLB) registering way even if the reading/writing actions of the TLB are impossible at one time by saving the information required for decision of a writing way when an ordinary TLB is read. CONSTITUTION:When an information processor carries out an instruction to give an access to a main storage, the TLB 1 and 2 are read out and compared with the access information 3. Then the hit conditions excluding the coincidence of space identifiers and the hit conditions of only the space identifiers are produced separately from each other by the address comparators 5 and 7 and held in the registers 8 and 9 respectively against a TLB mistake, i.e., a state where any way has no hit. When a TLB mistake occurs actually, the values of both registers 8 and 9 are inputted to a way deciding circuit 10 together with the value of the common segment bit contained in the access information. Thus a way to be registered is decided. Thus it is possible to decide a way for registration of the TLB even if both reading/writing actions of the TLB are impossible at one time.

Description

[Detailed Description of the Invention] [111 Required] Address Translation Buffer (TLB) Configuration Method When configuring an address translation buffer consisting of multiple ways using a RAM in which reading and writing are performed using a common circuit, reading and writing can be performed simultaneously. The aim is to eliminate the inconvenience caused by the lack of a space identifier in the TLB, and a circuit that compares whether all information other than the space identifier in the TLB matches the access information, a register that holds the result, and a space identifier in the TLB. A circuit that compares whether or not it matches that of the access information, and a register that holds the result are provided in correspondence with each way, and the information held in each of the registers is used to
It is constructed by providing a circuit for determining whether or not the corresponding information exists in the TLB (hit), and a means for registering the access information in the corresponding way when the circuit determines that it is a "hit".

[Industrial Field of Application] The present invention relates to an address translation buffer (hereinafter also referred to as TLB) for converting a logical address into a physical address at high speed in an information processing device, and in particular, to an address translation buffer (hereinafter also referred to as TLB) for converting a logical address into a physical address at high speed, The present invention relates to a circuit system for configuring a multi-way TLB using the formed RAM.

[Prior Art] When converting a logical address into a corresponding real address, an address conversion method using a TLB is used to perform the conversion process at high speed.

As shown in FIG. 3, the TLB has multiple entries 50-1.
It is composed of a plurality of ways (WAY) 51-1 to 51-n with .about.50-n (TLBz entries). Each TLB entry includes an LA area 54 and an RA area 55 that store the logical address (LA) of the address to be registered and the corresponding real address (RA), and an ID area that stores the logical address space information ID of that address. 53 and C8 area 52 (this C8
(The area will be described later).

To convert a logical address to the corresponding real address, use
By scanning the logical address of each entry in the TLB, detecting the logical address space information of the corresponding address and the entry with the logical address, and reading the real address (RA) stored there, the logical Addresses can be translated into corresponding real addresses.

As the system becomes larger and multiple TLB ways are provided as shown in Figure 3, if there is a common segment area that indexes a common real address from multiple logical address spaces, , an inconvenient phenomenon occurs in which a plurality of ways constituting the TLB are hit at the same time.

Next, this phenomenon will be explained with reference to FIGS. 4 and 5. Figure 4 shows the configuration of the logical address space.
a) is the unit immediately after initialization program load (IPL).
FIG. 3B shows the configuration of the logical address space (#0) and the multiple logical address space (#0 to #n), respectively. STO is a register in which the start address of the segment table of each corresponding logical address space is stored.

A common segment bit (CS bit, not shown) is provided in the segment table entry (STE>) of each logical address space (#0 to #n). When there is an area that indexes a common real address, that is, a common segment area (C8 area), the STE C that indicates that area
The S bit is set to “l”, otherwise it is “0”.
” is set.

Since the logical address immediately after IPL operates in a single logical address space, normally all S
The CS bit of the TE is set to ``MO''. Afterwards, a translation table (not shown) for other logical address spaces is enabled, but at that time the common real address is not transferred from any logical address space. If there is a C8 area to index, for example, logical address A of each logical address space #0 to #n
If both of them index a common real address, the CS bit of the STE of address A is set to "1", as shown in FIG. 3(b).

On the other hand, the number of TLB entries included in the TLB is limited, and by registering only necessary logical addresses, they are stored together with their corresponding real addresses, logical address space information IDs, and the like. In other words, even if the CS bit of the STE in the original logical address space that stores the logical address stored in the TLB is changed to "1",
Unless it is re-registered, the CS bit of the TLB entry storing that logical address will not be changed to "1".

Therefore, regarding the logical address of the C8 area, the following 5th
As explained in the figure, a phenomenon in which multiple ways of TLB entries are simultaneously hit occurs.

Immediately after IPL, logical addresses operate in a single logical address space, so logical addresses A, B, etc. are registered in the TLB along with corresponding real addresses Ar, Br, etc., as shown in Figure 5(a). Even if the
#0) is stored.

In this state where the CS bit of each TLB entry is 0'', after the logical address space moves to the multiplexed state as shown in FIG. 4(b), for example, the TLB is Suppose that an index is performed.

When the CS bit is “0”, TLB indexing is performed using logical address space information ID and logical address (LA), so there is no TLB entry with ID #l and logical address (LA) A. , a TLB entry mismatch occurs as shown in FIG. 5(b).

Therefore, regarding the logical address A of the logical address space #l, the well-known LRU (Least Recently
Registration with the TLB is performed by the Used method or other methods. At this time, the logical address A of the logical address space #1, together with its corresponding real address Ar and the logical address space information ID (#1), is set to the way ( Suppose that it is stored in a different way (for example, way) than the way (for example, way). This case occurs, for example, in the case of the LRU method, when the oldest address exists in the way.

At this time, Wei. TL of logical address space #0 in
The CS bit of the B entry is “0”, whereas the CS bit of the TLB entry of logical address space #l in way
The S bit is set to "1". CS bit is “
1", based on the common segment principle, it is possible to ignore this and access this TLB entry from any logical address space, even if the logical address space information IDs are different. (This Therefore, in the C8 area, the same real address corresponds to the same logical address.) In this state, when the TLB is indexed by logical address A of logical address space #0, in way. Naturally, humans occur.

On the other hand, in way, since the CS bit is '1'', the logical address space number #1 in the ID area is ignored and the logical address values are compared. As a result, logical address spaces #0 and #1 are compared. Logical address A matches, and a hit also occurs in way. That is, logical address A in logical address space #0 is a way. and way.

It will be a hit in both areas.

In the conventional multi-way TLB having logical address space information and CS bits, as described above, there was a problem in that a plurality of ways simultaneously hit a logical address in one C8 area. In this case, since there is no hardware error, it is obviously inconvenient to determine that there is a hardware failure. In order to eliminate this problem, when a simultaneous hit occurs in multiple ways, it is determined that it occurred under the above-mentioned circumstances, and the way is determined. TL for
B purge method and C in STE of logical address space
Methods have been proposed in which the TLB is purged when the S bit is set to "1," but these methods complicate the logical address conversion process and impede the speeding up of TLB reading. There was a problem.

To deal with such problems, in particular, in addition to the logical address and physical address pair in the TLB entry, a space identifier (
In a TLB consisting of multiple ways with space ID) and common segment bits, in the case of common segment access, when registering an entry, the STO
A technique for preventing simultaneous hits in multiple ways is disclosed in ``Japanese Unexamined Patent Publication No. 173359/1986, which performs a comparison while ignoring matching entries, and if there is a matching entry, it is registered in that entry.
Disclosed by J.

[Problems to be Solved by the Invention] The above-mentioned technique according to Japanese Patent Application Laid-Open No. 61-173359J will be further explained as follows.

That is, the TLB has a multi-way configuration, and the logical address and real address of the address to be registered, logical address space information of the address, and common segment bit are written in the TLB entry of each way.

This TLB has a common segment bit (C8)
When registering a logical address with 1, the comparison is performed ignoring the STO match, and if there is only one way that matches, it is registered in that way, and if multiple ways match,
It is registered in any one of the ways, and if it does not match any way, the registered way is determined by a method such as LRU logic.

Such control prevents simultaneous hits on multiple ways when reading the TLB.

RAM (Rand
om Access Memory) is generally used, but by sharing the write and read circuits in the RAM, the amount of circuitry constituting the RAM can be reduced. However, a RAM with such a configuration cannot be read and written at the same time.

Conventionally, in order to downsize information processing devices, when a TLB was configured using the above-mentioned RAM and the above TLB registration method was applied, reading and writing to the TLB could not be performed at the same time, so the TLB was not registered. There was a problem in that it was not possible to determine which way to register when doing so.

In view of such conventional problems, the present invention has been developed to
By saving information for determining the write way when reading B, it is possible to provide a method that allows determining the way in which the TLB should be registered even if reading and writing to the TLB cannot be performed simultaneously. The purpose is

[Means for Solving the Problems] According to the present invention, the above objects are achieved by the means described in the claims.

That is, the present invention provides an address translation buffer composed of multiple ways using a RAM that performs reading and writing by a shared circuit, in which all information other than the space identifier in the address translation buffer matches the access information. a register that holds the output result of the comparison circuit; a comparison circuit that outputs that effect when the space identifier in the address translation buffer matches that of the access information; A register that holds the output results of the circuit is provided corresponding to each way, and the information held in each register is used to ensure that the logical addresses match and the space I
D matches, or if the logical addresses match and the common segment bit of the segment table entry indicates that a common segment exists, then the corresponding information is This address translation buffer configuration method includes a circuit that determines that the desired information exists in the translation buffer, and a means for registering access information in the corresponding way when the circuit determines that desired information exists in the address translation buffer. be.

[Production use] FIG. 1 is a diagram illustrating the present invention in detail.

In the figure, 1 is the TLB way. , 2 indicate TLB ways, both of which are composed of RAM, but reading and writing cannot be performed at the same time. 3 is access information, which consists of a logical address, a space identifier, a common segment bit, etc. 4 and 6 are address comparison circuits during normal TLB successive output, and each is a way. and way, output the hit signal. The above circuits are also included in the conventional address translation buffer circuit, but the present invention further includes address comparison circuits 5 and 7 for determining the write way in the event of a TLB miss, and a register 8 and 7 for holding the result. 9. By providing a circuit 10 that determines the way to be registered based on the value of the register and the value of the common segment bit in the access information, it is possible to register the TLB in one cycle.

That is, when an instruction to access the main memory is executed in the information processing device, TLBs 1 and 2 shown in FIG. 1 are read out and compared with access information 3. If either way is hit, the main memory is accessed using the physical address of the hit way. At this time, in preparation for the case where no way is hit (TLB miss), the comparator circuit 5.
7, a hit condition excluding the spatial identifier match and a hit condition including only the spatial identifier are separately generated and held in registers 8 and 9. When a TLB miss actually occurs, the way to be registered is determined by inputting the value of register 8.9 and the value of the common segment bit in the access information to decision circuit 10.

[Embodiment] FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, and shows a TLB configured by a RAM (however, reading and writing cannot be performed at the same time) and a comparison circuit. In the figure, 11 is a TLB space identifier field, 12 is a common segment bit field (C
3B), 13 indicates a logical address field, and 14 indicates a physical address field. Further, 15 is a register that holds the current space identifier, 16 is a register that holds the logical address specified by the instruction, and 19 is a register that holds the current common segment bit. Previous 8 access information. Furthermore, 17 is a space identifier comparison circuit, 18 is a logical address comparison circuit, and 20 and 21 are each 1
Registers 7 and 18 are held, 22 is a hit detection circuit when reading TLB, and 23 is a hit detection circuit when registering TLB.

The hit detection logic when reading the TLB in the hit detection circuit 22 is as follows: [TLB hit] = [logical address match] & [(space I
D match) + (Common segment bit in TLB =
1)]. In addition, the hit detection logic at the time of TLB registration in the hit detection circuit 23 is as follows: 1:TLB hit]=[Logical address match]*&[(space ID match)**[: Common segment in STE
bit = 1)]. However, * is the value of the comparison result held in the registers 20 and 21. Also, & in the above formula is a logical product (
AND), + represents logical sum (OR). STE
The inner common segment bit is held in register 19.

Using the above hit detection logic when registering TLB, TLB
The registration way is determined as follows.

■ If there is a way that is hit at the time of TLB registration, register that way.

■ If there is no hit way, register it according to a well-known registration way determination method such as LRU.

[Effects of the Invention] As explained above, according to the present invention, the weight of the RA is reduced by sharing the read and write circuits.
In the case where the TLB is configured using M and consists of multiple ways that have a space identifier (space ID) and common segment bits in addition to a pair of logical address and physical address in the entry, the common segment・
In the case of access, Japanese Patent Laid-Open No. 2003-111100 states that when registering an entry, it is possible to ignore the matching of STOs and perform a comparison, and if there is a matching entry, register it to that entry, thereby preventing simultaneous hits in multiple ways. 61-173
It becomes possible to apply the technology described in 359,
Since it is possible to prevent a plurality of ways from hitting simultaneously when TLBs are successively issued, TLB purge becomes unnecessary.

Another advantage is that a hardware failure can be detected when multiple ways are hit simultaneously when TLBs are successively issued.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the details of the present invention, FIG. 2 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 3 is a diagram explaining the configuration of the TLB, and FIG. 4 is about the logical address space. FIG. 5 is a diagram illustrating a conventional TLB read operation. ■・・・・・・TLB way. , 2...TLB
Way 1.3...Access information, 4-7...
...Address comparison circuit, 8.9...Register, 10...Way determination circuit, 11...
Space identifier field, 12... Common segment bit field, 13... Logical address field, 14... Physical address field.
Field, 15.16. 19.20. 21...
...Register, 17... Space identifier comparison circuit, 18... Logical address comparison circuit, 22...
...Hit detection circuit when reading TLB, 23...
・・Hit detection circuit during TLB registration

Claims (1)

[Scope of Claims] An address translation buffer consisting of multiple ways configured using a RAM in which reading and writing are performed by a shared circuit, wherein all information other than a space identifier in the address translation buffer matches access information. a comparator circuit that outputs an output to that effect when a space identifier in a register that holds an output result of the comparator circuit and an address conversion buffer match that of the access information; A register that holds the output results of the above is provided for each way, and the information held in each register is used to determine whether the logical addresses match and the space IDs match, or , when the logical addresses match and the common segment bit of the segment table entry indicates that a common segment exists, it is determined that the corresponding information exists in the address translation buffer. An address translation buffer configuration method comprising: a circuit; and means for registering access information in a corresponding way when the circuit determines that desired information exists in the address translation buffer.