JPH0230629B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clamp circuit for video signals, etc., and can clamp video signals subjected to dispersal modulation without waveform distortion.
The purpose is to realize a high-performance clamp circuit with a simple circuit.

A conventional example will be described below with reference to the drawings.

FIG. 1 is a circuit diagram of a conventional clamp circuit using diodes. Note that the clamp circuit shown in FIG. 1 is a clamp circuit that clamps at a peak value.
A circuit that clamps at a peak value does not require a switching pulse for clamping, so it has the feature of simplifying the circuit configuration, and is often used for clamping video signals.

As shown in FIG. 1, the cathode of diode 1 is connected to contact 2, and the anode is connected to contact 3. Contact 2 is connected to constant voltage power supply terminal 5 via resistor 4.
and is grounded via a resistor 6 and an electrolytic capacitor 7 connected in parallel. The input terminal 8 is
This is a terminal for inputting a signal to be clamped, and is connected to the contact point 3 via a capacitor 9. Further, the contact 3 is connected to an output terminal 10 for outputting a clamped signal, and is also grounded via a resistor 11.

Figure 2 a and b are waveform diagrams of the composite video signal input to the input terminal 8 of the clamp circuit in Figure 1, Figure 2 c
is a waveform diagram of the composite video signal output from the output terminal 10 when the composite video signal of FIG. 2b is input. As shown in FIGS. 2a and 2b, the composite video signal includes a horizontal synchronizing signal 12 and a vertical synchronizing signal 13.

The potential at contact 2 of the clamp circuit shown in FIG. 1 is determined by the potential at terminal 5 and the ratio of resistors 4 and 6.
In the clamp circuit shown in FIG. 1, when the composite video signal shown in FIG. The potential of contact 2 is determined so that the potential decreases and diode 1 becomes conductive. When diode 1 becomes conductive, capacitor 9 is charged and the potential at contact 3 increases. When the potential at contact 3 rises to approximately the potential at contact 2, diode 1 is turned off. As a result, the first
The clamp circuit shown in the figure raises and fixes the potential at the tip of the synchronizing signal, which is the lower peak point of the composite video signal input to the input terminal 8, to the potential at the contact point 2. Since the input waveform of the composite video signal increases after the vertical synchronization signal 12, the diode 1 remains in the off state. Since the charges accumulated in the capacitor 9 do not move, the video signals up to the next vertical synchronizing signal 12' are outputted from the output terminal 10 with fluctuations equal to the fluctuations in the input waveform. In other words, when the composite video signal shown in FIG. 2a is inputted from the input terminal 8 to the clamp circuit shown in FIG. Output in the state. As described above, a clamped signal is obtained from the output terminal 10, but the following points should be noted in order to obtain good characteristics.

1. The output impedance of the stage before input terminal 8 must be sufficiently low.

2. The input impedance after the output terminal 10 is sufficiently high.

3. Select a resistance value for the resistor 11 so that the diode 1 becomes conductive at the vertical synchronization signal 12, which is the lower peak point of each input waveform, and make it as large as possible within that range.

4. Diode 1 must have low resistance and steep rise characteristics when in the on state.

However, even if the above points are taken into account, the characteristics of the clamp circuit shown in FIG. 1 are still unsatisfactory. for example,
If a composite video signal as shown in Figure 2a is directly FM-modulated, the spectrum will concentrate at the leading edge of the synchronization signal, so to prevent this, dispersal modulation may be applied to the video signal as shown in Figure 2b. When a video signal is input to the clamp circuit shown in FIG. 1 in order to demodulate this dispersal modulation, the waveform near the vertical synchronizing signal 13 is distorted as shown in FIG. 2c. In the future, it is expected that teletext broadcasting using vertical retrace intervals will become commonplace, so the waveform distortion described above will become a problem.

This phenomenon occurs in the diode 1 that can be obtained in reality.
This is because the characteristics of are different from ideal characteristics. Third
The figure is a characteristic diagram comparing diode 1 and an ideal diode. In the graph of FIG. 3, the vertical axis indicates the amount of current I flowing through diode 1,
The horizontal axis indicates the potential E of the contact 3 of the clamp circuit shown in FIG. Ideal diode current-voltage characteristics 14
When the voltage E drops to the threshold voltage 15, the current I suddenly starts flowing. However, in the current-voltage characteristic 16 of the diode 1, even if the voltage E drops to the threshold voltage 15, the current I does not suddenly flow, and as the voltage E becomes lower than the threshold voltage 15, the current I starts to flow in large quantities. As described above, the rise characteristics of the diode 1 actually obtained differ greatly from the rise characteristics of an ideal diode.

In view of the above drawbacks, the present invention provides a clamp circuit that has better characteristics than conventional clamp circuits and can be implemented with a simple circuit.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a circuit diagram of a clamp circuit which is the basis of the present invention, and the same parts as those in the circuit of FIG. The feature of the circuit shown in FIG. 4 is that an NPN type transistor 16 is used instead of the diode 1 shown in FIG.
Its base is connected to contact 2, its emitter is connected to contact 3, and its collector is connected to constant voltage power supply terminal 5.

The potential of contact 2 is determined by the potential of terminal 5 and the ratio of resistors 4 and 6. Therefore, when the video input signal shown in FIG. 2a is input to the input terminal 8 of the clamp circuit shown in FIG. 4, the potential of the contact 3 decreases at the tip of the synchronization signal. When the potential of contact 3 becomes lower than the potential of contact 2 to some extent, transistor 16 operates. Contact 2
When the base current of the transistor 16 flows,
A collector current of the transistor 16 flows from the terminal 5 at a magnitude more than several tens of times the base current. Then, the sum of the base current and the collector current flows to the contact 3 as an emitter current of the transistor 16 and charges the capacitor 9. transistor 16
Let h _FE be the current amplification factor of transistor 16
The current flowing through the contact 3 and charging the capacitor 9 during operation is approximately h _FE times that of the diode 1 shown in FIG. That is, when comparing the clamp circuit in FIG. 4 with the clamp circuit in FIG.
This means that it has been improved to h _FE . As a result, the transistor 16 in the clamp circuit shown in FIG. 4 has better startup characteristics than the diode 1 in the clamp circuit shown in FIG. It can be realized.

According to the configuration shown in FIG. 4, when compared with the conventional example, the start-up characteristics are improved, or there remains a point at 15 in FIG. 3 that should be considered as a problem that should be further improved.

FIG. 5 is a circuit diagram of a clamp circuit in an embodiment of the present invention. The clamp circuit of FIG. 5 is an improved version of the clamp circuit of FIG. 4. As shown in FIG. 5, the PNP type transistor 17 has its base connected to the contact 18 and the transistor 16
and to the terminal 5 via the contact 18 and the resistor 20. Also, transistor 17
The emitter is also connected to terminal 5, and the collector is connected to contact 3.
It is connected to. Therefore transistor 16,1
7 and resistors 19 and 20 constitute an inverted Darlington connected transistor.
When the composite video signal shown in FIG. 2a is input to the input terminal 8, the potential of the contact 3 decreases at the vertical synchronization signal 12. When the potential of contact 3 becomes lower than the potential of contact 2 to some extent, transistor 16 operates. Due to the operation of transistor 16, current flows through resistors 19 and 20, and the potential of contact 18 decreases, causing transistor 1
7 works. The current amplification factor of transistor 17 is
When h _FE ', a current that is h _FE ' times the collector current of the transistor 16 flows from the transistor 17 to the contact 3 and charges the capacitor 9. That is, when the current amplification factor of the transistor 16 is h _FE , a current that is h _FE ·h _FE ' times flows through the contact 3 compared to the case of the diode 1 in the clamp circuit shown in FIG. As a result, the impedance of the transistors 16 and 17 in the clamp circuit of FIG. 5 during operation is improved to 1/(h _FE ·h _FE ') compared to the diode 1 of the clamp circuit of FIG. 1. Since the impedance is reduced to 1/(h _FE · h _FE ') times, the rise characteristics of transistors 16 and 17 of the clamp circuit shown in FIG. 5 are greatly improved compared to the conventional clamp circuit, and A clamp circuit with superior characteristics compared to other circuits can be realized.

As described above, in place of the diode 1 in the clamp circuit of FIG. By connecting the terminal to contact 2, connecting the collector or a terminal equivalent to the collector to terminal 5, and connecting the emitter or a terminal equivalent to the emitter to contact 3, a simple circuit with superior characteristics compared to the conventional clamp circuit can be achieved. A clamp circuit can be realized.

Note that the above clamp circuit clamps at the lower peak value of the waveform, but a circuit that clamps at the upper peak value of the waveform can also be realized by replacing the PNP type transistor with an NPN type transistor and replacing the NPN type transistor with a PNP type transistor.

Furthermore, the characteristics of the clamp circuit shown in FIG. 5 can be further improved by replacing transistor 16 or 17 with a Darlington-connected transistor to increase the equivalent current amplification factor.

As described above, the present invention uses a transistor or a Darlington-connected transistor in place of the diode in the conventional clamp circuit using diodes, thereby achieving higher performance than the conventional clamp circuit with a simple circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a conventional clamp circuit, Figure 2 a, b, and c are waveform diagrams of a composite video circuit, Figure 3 is a characteristic diagram of a diode, and Figure 4 is a diagram of a clamp circuit that is the basis of the present invention. Circuit Diagram FIG. 5 is a circuit diagram of a clamp circuit in one embodiment of the present invention. 1...Diode, 4, 6, 11, 19, 20
...Resistor, 5... Constant voltage source, 7, 9... Capacitor, 8... Input terminal, 10... Output terminal, 16,
17...Transistor.

Claims (1)

[Claims] 1. One end of a first resistor 6 and a first capacitor 7 connected in parallel are connected to a first predetermined potential source, and the other ends of the first resistor 6 and capacitor 7 are connected to a second
is connected to a second predetermined potential source via a resistor 4, and the other ends of the first resistor 6 and the capacitor 7 are connected to the first
a second transistor 16 such that the collector of the first transistor 16 is connected to the base of the first transistor 16 in an inverted Darlington connection.
The base of the second transistor 17 is connected to the first or second predetermined potential source via the third resistor 20, and the emitter of the second transistor 17 is connected to the base of the transistor 17. The base is connected to the coupled first or second predetermined potential source, the emitter of the first transistor 16 is connected to the collector of the second transistor, and this connection point is connected via the fourth resistor 11. , when the emitter of the second transistor 17 is connected to the first predetermined potential source, to the second predetermined potential source, and when the emitter of the second transistor 17 is connected to the second predetermined potential source, A clamp circuit configured to be connected to a first predetermined potential source, and to connect the emitter of the first transistor 16 to an input terminal via a second capacitor 9, and to obtain an output from the connection point.