JPH02305227A - Variable length code inverse converter - Google Patents

Abstract

PURPOSE:To decrease the capacity of a ROM required for the circuit considerably by utilizing it that the number of n-bit basic code words is smaller than the number of code words to be represented in n-bit, dividing the decoding into the tentative decoding and the final decoding, and providing a p-notation and binary conversion circuit between them. CONSTITUTION:An input code word bit string is fetched in a 30-bit shift register, fed to a latch circuit and the 12-bit data is fed to a tentative decoding circuit. The tentative decoding circuit 12 consists of 6 same circuits to decode a basic code word for each block in 5-bit. Then a 12-bit signal outputted from a ROM 14 is fed to a 12-bit output shift register. Simultaneously the information representing how many bit of code word is decoded is fed to a latch signal generating circuit from the ROM. The code word fed to the output shift register is converted serially and outputted by one bit each.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable length code inverse conversion device applied to the transmission or recording of digital signals.

[Conventional technology]

Various methods have been developed for recording codes used when recording and reproducing digital signals on optical disks, magnetic disks, etc. as recording density increases. This converts the information data bit string to be recorded into a format suitable for recording.
The following properties are required.

(1) Minimum magnetization reversal interval T min It is desirable that T m1n be large in order to be less susceptible to the band limitation of the recording/reproducing system.

(2) Maximum magnetization reversal interval Tmax In order to obtain a self-clock function and extract clock information, it is desirable that Tmax be small.

(3) Detection window width Tw Represents the degree of margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and is preferably large.

Usually, a run length limited (hereinafter abbreviated as RLL) code is often used as a recording code. R.L.
For the L code, the minimum value of the number of runs of 0° between 1° and "1'" in the code bit string after conversion is d, the maximum value is 1, the basic data word length is 01, the basic code word length is m1 code. The number of word lengths is r ma
As x, (d, k, n, m, rmax)
It is called a sign. Using these parameters, Tmj
It can be expressed as n= (d+1) ・Tw Tmax= (k+1) ・Tw Tw−(m/n)+T (T: 1-bit length of data word). Among these R and LL codes, variable length codes are suitable for high density, as they can achieve the same level of performance with a smaller code word length and number of code words than fixed length codes.

In order to use a recording code, a decoding device is required to convert the code word back into a data word.This can be achieved by constructing a combination of gate circuits, or by using the input code word bit string as an address signal and converting the data into a data word. There is a method of accessing a ROM in which word bit strings are written. (d, k,
m, n, rrnax') code, RO
Using M, its capacity ■ is V = 2”””・r
mjx ” m bits.In variable-length codes, in order to achieve word synchronization, information on how many pins the code word has been inversely converted is required. Normally, this is also written in the ROM, but this memory For example, Figure 2 does not show the correspondence table between data words and code words (
4, 19, 2, 5, 6) codes, the conventional decoding circuit is configured as shown in Figure 7, and the required R, OM capacity is ■=2.
30.12 to 1.3×1010 humans.

[Problem to be solved by the invention] Generally, when the code word length n is increased, Tm1n and Tmax.

Either Tw can be improved. As mentioned above, when a code with better performance is sought in order to increase the density of a variable length code, both the code word length and the number of code words become large. For this reason, if a decoding circuit is constructed using a ROM, the capacity thereof increases, resulting in a problem that it is not practical.

Further, in general, the number of basic code words of a variable length code is much smaller than the number of binary codes expressed by n bits, which is the basic code word length. In other words, 2° codes can be expressed with binary n bits, but in the RLL code, the number of runs of “0” between “1” and “l°” in the code word is the minimum value (d ) and the maximum value (k), for example, in the (4., 19. 2. 5. 6) code shown in FIG. 2, the six basic code words shown in FIG. 3 are restricted. Since this code has n=5 and can represent 32 codes, it has redundancy accordingly.

Therefore, in order to solve the above-mentioned problems, the present invention ('d
, k, m, n, 1-max) code is intended to reduce the capacity of a ROM used in a variable-length code inverse conversion device.

[Means to solve the problem]

The variable length code inverse conversion device of the present invention has a basic data word length of m
When the basic codeword length is n bits, 1≦r≦
For an integer r r nnax, convert an r''m-bit data word into an r''n-bit codeword, and create a binary code bit string of ``1'' and ``1'' generated by connecting the converted codewords. In a decoding device that inversely converts each code word of a variable-length RLL (run length limited) code, which limits the number of runs of 0''' between 6 to 6 or less, to its corresponding data word, means for dividing into r max blocks of n bits, means for temporarily decoding each block into q bits, and r max of the result of the temporary decoding.
It comprises means for converting the q-bits into a binary number by regarding them as a p-adic number of r max digits, and means for finally decoding the binary number into a data word.

[For production]

With the above configuration, it is possible to configure a variable length code inverse conversion device that requires a small memory capacity.

〔Example〕

Below, the configuration for realizing the present invention (4,19°2,
5. 6) Taking a code as an example, explanation will be given based on the drawings.

This code has basic data word length m = 2, basic code word length n
=5, codeword length number r max-6, and Tmjn==
2.0, Tmax=8.0, and Tw=0.4.

FIG. 1 shows a block diagram of the decoding circuit. The input codeword bit string is taken into a 30-bit input shift register and sent to a latch circuit. Furthermore, these 30 bits are sent to a temporary decoding circuit. The temporary decoding circuit is composed of six identical circuits, and temporarily decodes the basic code word for each 5-bit block. Temporary decoding method and RO used for final decoding
The contents of M will be explained.

First, 3-bit codes are assigned to the six types of basic code words shown in FIG. 3 from [1og26]+1=3.

How to allocate the eight types of 3-bit codes is arbitrary, but the method shown in FIG. 3 is used here. The temporary decoding circuit outputs a 3-bit code for each block according to this correspondence. By dividing the code words in FIG. 2 into 5 bits and replacing them according to FIG. 3, a correspondence table between temporary decoded words and data words can be obtained. A part of it is shown in Figure 4. Next, the 3 bits corresponding to 1 block of this temporary decoded bit string are regarded as 8 hex digits.

In other words, the temporary decoded bit string is considered to be a 6-digit hexadecimal number. Since this has 66=46656 patterns, it is converted into [6·log26]+1=16 bits by the hexadecimal-binary conversion circuit. Finally, the ROM is accessed using this 16-bit bit string as an address signal.

As can be seen from Figure 2, when r2>rl, 5r
A 1-bit code word may be equal to 5r1 bits from the beginning of the 5r2 bits 1 to 5 code words. For example, the first 5
A code word whose bits are 10000' is selected and shown in Figure 5. In this way, the first 5 bits in the input shift register are 10000 (the corresponding basic temporary decode word is 00
1”), it cannot be immediately decoded as “00”’, and it is necessary to give priority to the code word with a longer word length.To achieve this by arranging the data in the ROM, do the following: do.

The correspondence with symbols when the basic temporary decoded word is viewed as hexadecimal digits is shown in FIG. The first three bits of the temporary decoded word are “00”
There are only four provisional code words of "1"("1" in hexadecimal) shown in FIG. 5. Below, these four will be considered.

(A) The six-digit hexadecimal address whose beginning is "l" in hexadecimal is 7776 to 15551 in decimal notation, where the data "o" is written.
oooooooooooooo". (,B) For addresses whose beginning is hexadecimal □ "10", put data "010000000000" here. However, if the address overlaps with (A), put this data. (C) Addresses whose beginning is hexadecimal 'l OO' are 7776 to 79910, and data "10" is placed here.
0100000000” (. However, if the address is (A
) and (B), this data will be given priority. (D) Addresses starting with hexadecimal "10001" are 7776 to 7787゜ Data here is ゛'1110
10110000". However, if the address is (A),
If the data overlaps with (,B) and (C), this data will be given priority. The results are shown in Figure 6. The beginning of the temporary decoded word is 6
Cases of decimal numbers 2 to 5 are assigned in the same way. In this way, the required ROM capacity can be reduced to 2-”=0.006
It can be reduced to %.

Next, the 12-bit signal (not all bits are necessarily data words) output from the ROM is sent to a 12-bit output shift register. At the same time, information on how many bits of the code word have been decoded is sent from the ROM to the latch signal generation circuit, so that, for example, when a 10-bit code word is converted, a new 10-bit code word is added to the input shift register.
When a bit is input, the next latch signal is generated. The code word sent to the output shift register is serially converted and output bit by bit. However, although not shown in Fig. 1, the output shift register has an input amplifier I/
A clock of 215 times that of the register and latch signal generation circuit is supplied, and the output shift register is configured to shift by 4 bits while the input shift register shifts by 10 bits.

Next, as another example of the present invention, (5, 1, 6, Z.

6.4) A case where the present invention is applied to a code will be explained. This (5,16,2,6,4) code has basic data word length m = 2, basic code word length n = 6, and code word length number r□
ax = '1, Tm1n = = 2.0, T m a
It is a variable length code with x = 5.7 and Tw = 0.33. FIG. 8 shows a correspondence table between data words and code words. As shown in FIG. 1, the decoding device has a 24-bit input shift register and an 8-bit output shift register. Further, the 12 temporary decoding circuits in FIG. 1 become four. The basic number of code words is 7, which is q-[1og27]+
], =3, provisional decoding is possible. The correspondence table (part) of this basic code word, basic code word number, and output data word is as shown in FIG. In Figure 11, the first 3 bits of the temporary decoded word are “
TOO” (corresponding basic code word is “000100”)
) is a memory map in which the address is the bit string after hexadecimal-to-binary conversion, and there are no duplicate addresses. Other cases can be found in the same way. With this code, the R and OM capacities can be reduced to 2=2=0.024%. The circuit operation is (
4゜1.9. 2. 5. 6) It is the same as the explanation using the symbols.

As mentioned above, if the number of basic codeword patterns is p, p is a binary number of q-110g2pl do1p'tsul- ([] is the Kakarasu code), which uniquely identifies any of the basic codeword patterns. Runs by specifying. Next, the output r max ” 'q pits from this temporary decoding means are converted into r n+ax digit p
By considering it as a base number and converting it into a binary number, it can be further reduced to [r max·]00g2I] +] bits. Therefore, the input code word is not directly used as an address signal, but is tentatively decoded into a q-pit code for each block of n bits. Then, if we access the ROM using the result of p-adic-binary conversion as an address signal and perform final decoding on the total rmゎ...q bits of the temporary decoding results, the ROM capacity iV required for decoding is as follows. , 1/2′”ax
'n [r""Iog, p:] ' can be reduced to +1. [Effects of the Invention] As explained above, the present invention utilizes the fact that the basic number of n-bit code words is smaller than the number of code words that can be represented by n bits in a variable-length code inverse conversion device, and performs decoding using temporary decoding. and final decoding, and a p-adic-to-binary conversion circuit is provided between them (p is the number of basic code word patterns), the ROM capacity required for the circuit can be reduced significantly, and high-density recording can be achieved. Even if the scale of recorded codes increases as the technology advances, a decoding circuit can be configured with a small ROM capacity, and its practical value is extremely high.

[Brief explanation of drawings]

Figure 1 is a block diagram that does not show the configuration of the present invention, and Figure 2 is a (4
, 19, 2, 5, 6) Correspondence table between code data words and code words. FIG. 3 is a correspondence table between basic code words and provisional decoded words of the (4, 19, 2, 5, -6) code. Figure 4 shows (4,, 19°2,
5. 6) Part of the correspondence table between code data words and temporary decoded words. FIG. 5 shows a code word whose first 5 bits are "10000" and a corresponding data word. Figure 6 is (4,,1,9゜2
．． 5.6) Part of the memory map of R and OM used for final decoding of the code. FIG. 7 is a block diagram showing the configuration of a conventional decoding device that uses an input code word bit string directly as a ROM address. FIG. 8 is a correspondence table of data words and code words for the (3, 16,, 2,, 6° 4) code. Figure 9 is (3°1.6
．． 2.6.4) Correspondence table between basic code words and provisional decoded words. FIG. 10 is part of a correspondence table between data words and provisional decoded words of the (3,]6.2.6.'4) code. Figure 11 shows (3°1.6.
2. ``6.'4) Part of the ROM memory map used for final decoding of the code. 10.20・・・・・・・・・・・・・・・・・・・・・
... Input shift register 11, . 21...
・・・・・・・・・・・・・・・・・・・・・・・・
...... Latch circuit 12...
・・・・・・・・・ ・・・・・・・・・・・・・・・
......Temporary decoding circuit 13
・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・P-adic-binary conversion circuit 14, 22・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・R'OM15.23・・・・・・・・・
・・・・・・・・・・・・・・・・・・Output shift register 1.6.24・・・・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・・Latch signal generation circuit (4, 19° data word 2, 5. 6) Code data word and code word correspondence table Code word iooooooooo. oooooiooooo. 010000'100000C100 010000010000'000 ooioooootoooooo. ooiooooooooooo. ooooooooooooooo. oooooiooooooooo. oioooootoooooooooooo. oioooootoooooooooooo. oioooooiooooooooooooo. oo i'oooo i oooooo i oooo
. oooooooooooooooooooo. ootooooooiooooo1oooo. ootoooooooooooooooooo. ooootooooto, ooootoooooo. oooooooooooooooooooo. 000100001.00000000000ooo
toooooo toooo toooo. oooooooooooooooooo. oooo t oooo i oooo i oooo
. o 1ooooo i oooo toooooo 1o
ooooo. (111.1001011) 01000
oioooooiooooooooooooooo01000
0010000100C)0000o i 00000
1 00000 toooooo01000001
000000QOOOOOO0100000010000
01000.00otoooooooooooooo
oooooio. ooooooo1oooooooooooo
oioooiooo'ootoooooooo00100
00100000010'OO00ooioooooto
ooooooooooooooooooooooooooooooo
ooooooo0001000001000000'00
00ooootooooiooooooo. ooooooooo
ootoooooooooooooooooooo
ooooooooootoooo001.0000.100
001. OOOOOOOOoooooooo. toooooo
ioooooooooooooooooooooo
oooooiooooooooooooooooo
1 o o o o o o o to. o o'o o
o o o o oooooiooooo 1oooooo
i”oooooooo i 00000 1 0000
000000000010000100001'000
00o o o o i o'o'o o o o o o
o o o o o o o ooooooooooo
oooooootoooo00010000100000
1.00000ooooiooooo1ooo'ooooo
ooo00o1000001000010000000
00100001000000.00000 0 0
0 0 0 0 0 0 0 0 0 0 0 '0
1 0 0 0 00'00010000100001
0.00000 0 0 0 1. 0 0 0 0
0 0 0 0 'O 0 0 0 0 0 0010
000100001000010000C)000(1
11110101111') ' 0f(1111
11'000110) 01000010000
1'00001000000010000000001
00'0O1000001,000010000000
0'00010000100000100.00010
0'0OOOOooooo 1000010000001
ooooooooooo. 00001'00001000000.0100001
．． 000000000100000100001000
0・0100OOQO000010000010000
10000,0C)1. OO, 0OOo, o, ooi,
ooooooi ooooootoooot oooooo. oooooiooooo1oooo○1.0OOOO, O1
,0000000001'0OOOO10000010
0000000000oooo i ooooooot
0000100001000000oooo io
oooooo t oooooo t o,,oo'o1o
ooooo. oooo t oooooooo t oooo io
ooo i o, ooo. ooooo 10'OO(] 10000100000
1000000000001QOOO10000100
00001'00000ooooooiooooo 1oo
oooioooootoo, ooo. 000001000010000001000010.
000000'0OO100001000000100
00000000oooooo1ooooooioooooi
ooooo'1oooo. nnn 01110nnnn1 n0nnl n[
'l 00n(']1nnn'On□ oooooiooo, oooioooootooooooio
ooooo. 00000100000100000'1OOOOOO
C100'0000'001000000100001
00000000000000001000010o0
0100001000000oooooo i ooo
o 1ooooo i ooooooooooo. DC10000100CIO100000tO0000
00000DO000010000010000100
0'0100000 000001000001000
010000000000 000000100001
000010000100000)00000.010
00010000'10000000000t ooo
o i oooo i oooo i oooo, o
i ooooo. t oo, oo t oooo 1oooo i oo
oooo toooo. 100001.00001000010.000000
00000100C) 010000100000100
0010000001000010000100000
10000010.00001000010.0001
0000010000.0000000[,0QOO1
000010000001, C100O100OOOO1
000010000, 100000010000000
0001,0O001000001000010000
jO00000100001000001000010
000Q100000[0000j000'0O100
0010,0OC100O0000iQOOO1000
0010000010000100000IQOOOOI
000.0010000010000000.000
10000.1. OOOOOOO100001,000
01,OQ OOO10'oO'010. O'O, OO
O100001,0,000000000LOOOOO
10000100001000010,00000[0
000010'0OO10000jO00001000
00LOOOOO100OO100OO1000000
000001'0OO00'1OOOO1000001
0000100000 ( )
1oooooooo 1.0000 toooo
o t oooo i oooooo000 1 000
0 1 0000 toooooooooooo i
oooo i oooo 1oooo i oooo
oo00100001.00001000001000
00ooioooooiooooo1oooooooooo
oiooooooooooooooooooooo
i ooooooo i ooooo i ooooooo
oooo00010C)00100000000000
0000ooooooooooooooooooooo
oooooiooooooooooooooooooooooooooo
ooooo1ooooooiooooooooooooo
o000000000'OOOOOOOO1000000
0ooiooooooooooooooooooo
ootoooooooooooooooooooooo
ooioooooiooooooooooooooo
ooooooooooooooooooooooooo
ioooo 1oooooooooooooooooo
oo (ooo)C)0100
(011) Data word (data) Temporary decoded word (address) 10"01 10 1'Ojl OOO 1, oioo, i LO1110 1100'00 ooi oo. oio oo. 011 C) 00 01.0 101 000 01C) 000 000 0. o O. o o o. 0 0 0 0 匡o
o 0 0 Q
0 0 - vO-0←mouth OC) -s -< 8 goes around] 11tootc+'+ o o o o o o (o o o)
oiooooo (oto)oooooo Go (110) Heptan symbol 1 J 1 1, 01.000 101 1, 00 oio oo. oio 1oo oo.

Claims (5)

[Claims] (1) When the basic data word length is m bits and the basic code word length is n bits, for an integer r such that 1≦r≦r_m_a_x, an r・m bit data word is converted into an r・n bit code word. variable-length RLL (run length limited) that limits the number of runs of “0” between “1” and “1” in a binary code bit string generated by the connection of code words after conversion to d or more and k or less. In a decoding device that inversely transforms each code word of a code into its corresponding data word, an input code word is converted into each n
means for dividing into r_m_a_x blocks of bits; means for temporarily decoding each block into q bits;
1. A variable-length code inverse conversion device comprising means for converting the binary number into a binary number by regarding it as a p-adic number of _x digits, and means for finally decoding the binary number into a data word. (2) The number of basic codewords of n bits, which is the basic codeword length, is p
and when the temporary decoding means outputs a q-bit code corresponding to the p patterns for each n-bit block, q=[log_2p]+1 ([ ] is a Gaussian symbol). A variable length code inverse conversion device according to claim (1). (3) The p-adic-binary conversion means converts [r_m_a_x
The variable-length code inverse conversion device according to claim 2, wherein the variable-length code inverse conversion device outputs log_2p]+1 bit. (4) The final decoding means outputs an r m bit data word pattern that is uniquely specified by the total [r_m_a_x·log_2p]+1 bit code output from the p-adic-binary converting means. A variable length code inverse conversion device according to claim (3). (5) The variable length code inverse conversion apparatus according to claim (1), wherein the temporary decoding means is constituted by a memory or a gate circuit, and the final decoding means is constituted by a memory.