JPH01221924A - Variable length code inverse converter - Google Patents

Abstract

PURPOSE:To remarkably reduce the capacity of ROMs by performing a processing by separating to temporary encoding and final encoding by utilizing the fact that the number of basic code words of (n) bits is less than that of code words possible to be represented in (n) bits in a decoder for a variable length RLL code. CONSTITUTION:A (4, 19, 2, 5, 6) code in which the number of run of '0' of a binary code word string with basic data word length (m)=2, basic code word length (n)=5, the number of code word length rmax=6, and connecting the code words after conversion with each other is limited to a value over 4 and less than 19 is taken as a sample. The number of basic code words is remarkably less than that of a binary code represented in the (n) bits that is the basic code word length. It is based that the number of run of '' of the binary code word string is limited. Assuming the number of basic code word patterns as (p) and (q) as the minimum integer to satisfy p<2<q>, it is possible to designate either the basic code word patterns by the (q) bits. By performing the temporary decoding of an input code word to a code of (q) bits and making access to the ROM setting the sum rmax.(q) bits of the results as an address signal, and performing the final decoding, the capacity V of the ROM is reduced by 12X12<18> bits from 12X2<30> bits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a variable length code inverse conversion device applied to the transmission or recording of digital signals.

[Conventional technology]

Various methods have been developed for recording codes used when recording and reproducing digital signals on optical disks, magnetic disks, etc. as recording density increases.

This converts the information data bit string to be recorded into a format suitable for recording, and requires the following properties.

(1) Minimum magnetization reversal interval TmIa It is desirable that T1. be large in order to avoid the influence of band limitations of the recording and reproducing system.

(2) Maximum magnetization reversal interval T□,X In order to obtain a self-clock function and extract clock information, it is desirable that T1.8 be small.

(3) Detection window width TW Represents the degree of margin against time axis fluctuations such as jitter of the reproduced signal and peak shift due to waveform interference, and is preferably large.

Usually, a run length limited (hereinafter abbreviated as RLL) code is often used as a recording code. RLL
For the code, the minimum value of the number of runs of “0” between “1” and “1” in the code bit string after conversion is d1, the maximum value is 1, the basic data word length is n1, the basic code word length is m1, the code word length is r man the number
As (d.

k + n 9m + r mmx ) code. Using these parameters, it can be expressed as T, , = (d+1)-Tw T,, = (k+1)-Tw TW = (m/n) ·T (T: 1-bit length of data word). Among these RLL codes, variable length codes are suitable for high density, as they can achieve the same level of performance with a smaller code word length and number of code words than fixed length codes.

In order to use a recording code, a decoding device is required to convert the code word back into a data word, but this can be achieved by using a combination of gate circuits, or by using the input code word bit string as an address signal and converting the data into a data word. There is a method of accessing a ROM in which word bit strings are written. (d, ni, m, n
+rm,. ) code, if a ROM is used, its capacity V becomes ■=2r...°n .rmax.m bits. In addition, in variable-length codes, information on how many bits of the code word have been inversely converted is required in order to achieve word synchronization, and this is usually also written to the ROM (but we will consider this without considering the amount of memory). For example, in the case of a (4, 19, 2, 5, 6) code whose correspondence table between data words and code words is shown in Table 1 below, a conventional decoding circuit is configured as shown in Fig. The ROM capacity is V=2''·12 bits.

[Problems to be Solved by the Invention] Generally, by increasing the code word length n, any of Tm1m+7'ffi, . . . Tw can be improved. As mentioned above, when a code with better performance is sought in order to increase the density of a variable length code, both the code word length and the number of code words become large. For this reason, if a decoding circuit is constructed using a ROM, the capacity thereof increases, resulting in a problem that it is not practical.

[Means for Solving the Problems (and Effects)] In order to solve the above problems, the present invention provides (d).

The purpose of this is to reduce the capacity of a ROM used in a decoding device for (k, m, n+ rmax ) codes.

Generally, the number of basic code words of a variable length code is much smaller than the number of double codes expressed by n bits, which is the basic code length.

In other words, two codes can be expressed using n binary bits, but
In the RLL code, the number of runs of "0" between "1" and "l" in the code word is limited to both the minimum value (d) and the maximum value (k). Table 1 shows (4,
In the 19°2.5.6) code, the six basic code words shown in Table 2 are. Since this code has n=5 and can represent 32 codes, it has corresponding redundancy. Here, the number of basic codeword patterns is p,
If q is the minimum integer that satisfies p<2', then any one of the basic code word patterns can be uniquely specified with these q bits.

Therefore, instead of using the input code word directly as an address signal, n
Each block of bits is provisionally decoded into a q-bit code. Then, if the ROM is accessed using the temporary decoding result total r0.8 ・q bits as an address signal and final decoding is performed, the ROM capacity V required for decoding is V=2r...°q ・rm*x It becomes "m bits" and can be reduced to 2-r""-(n-Q).

〔Example〕

Below, the configuration for realizing the present invention (4°19.2,
5.6) Taking a code as an example, it will be explained based on the drawings.

This code has a basic data word length m=2 and a basic code word length n=5.
, the codeword length number r-*x=6, and T,1°=2.0,
Tffi,,=8.0. It is a variable length code with T,=0.4. FIG. 1 shows a block diagram of the decoding circuit. The input codeword bit string is taken into a 30-bit input shift register and sent to a latch circuit. Furthermore, these 30 bits are sent to a temporary decoding circuit. The temporary decoding circuit consists of six identical circuits, and temporarily decodes the basic code word for each 5-bit block. The method of temporary decoding and the contents of the ROM used for final decoding will be explained based on Table 1. 1st
The table is a data word-code word correspondence table for the (4, 19, 2, 5, 6) code.

Table 1 (4, 19, 2, 5, 6) Code data word-code word correspondence table Data word Code word (Go) 10000 (1110101110) ' 0100001
000010000010000000 (111011
0101) 0100OO100OOOO100
OOOOOOOOOQO (1110110111)
otooooioioooooooiooooooooo
o.

(1110111000) 01000010
000001000(+0000000(010111
111) 010000 (IIQ(100010
0001000000 (1111000001)
0100000100000100000.000
000 (1111000101) 01.00
000010000100000100000 (111
1000110) Q100OOOO100O
O100OOOOOOOOOO (1111000111)
0100000010000 units 1000
0100000 (1111001011) , ,
01000000010000000000000
00(11110(Hllll) 001000
0100001000000100000 (11110
10010), 00100001000001
00000100000 (1111010011)
0O100001000'0010000000
0000 (111110101101) ,010
0001000010000100000100000
00 (111110110101) 01000
．． 010000100000001000010000
0 (111110110111) 0j0000
100000100001000001000000(
111110111000) 0100001.0
0000100001000000100000 (11
1111001010), 0100000100
00010000100000000000 (1111
11001011), 010000010000
010000010000100000 (111111
0 units 1100) 0100000100000
10000010000000000 (1111110
10011) 0IOQOOOO100OO10
0OOOO100OOOOOOOO(111111011
101) 0O100OO100OO100OO
O100OOQ100OOOO (11111111101
1)' 000.010000100001011
0010000000000 (11111111111
1) Oi00000100001000001
00000000000toooooooooooo
oooooooiooooooooooooooooooo
ooooooooooooooooooooooooo
2 Table basic code word (temporary code word) 3 Table data word Temporary code word 4 Table code word Data word toooo oooooo oto.

1oooo oooooo oooooo too
io.

Table 5 Addendum
ta(a) 001000000000001000・
=001000000000001111111010
110000(b) 001000000000000
000...0010000001111111111
00100000000 (excluding address (a)) (C) 001000000000000000.00
1000111111111111 01000000
0000 (excluding addresses (a) and (b))
(d) 001000000000000000...
00111111111111111 000000
000000 (excluding addresses (a), (b), and (c)) First, 3-bit codes are assigned to the six types of basic code words shown in Table 2. How to allocate the eight types of 3-bit codes is arbitrary, but Table 2 is used here. The temporary decoding circuit outputs a 3-bit code for each block according to this correspondence. By dividing the code words in Table 1 into 5 bits and replacing them according to Table 2, a correspondence table between temporary decoded words and data words can be obtained.

Some of them are shown in Table 3. Next, the ROM is accessed using these 18-bit temporary decoded bit strings as address signals, and the address to which the data words in Table 3 are sent will be explained.

As can be seen from Table 1, when r2>rl,
A 5r+ bit codeword may be equal to 5r bits from the beginning of a 5r2 bit codeword. As an example, select a codeword whose first 5 bits are "10000" and
Shown in the table. In this way, the first 5 in the input shift register
The bit is '10000' (the corresponding temporary decoded word is '00
1'' (actually, this is the input to the ROM), it is not possible to immediately decode it to 10000'', and it is necessary to give priority to code words with longer word lengths. This can be achieved by arranging data in the ROM as follows.

For example, in the data for a 9-bit temporary decoded word, the first 9 bits are the 18-bit address 2, which is the temporary decoded word.
”=6 O’s are added to the end of the corresponding data word for all 512 words for a total of 12 bits.

However, as a result of allocating addresses in the same way for the 3r-bit temporary decoded word where r>3, if there are duplicate addresses, the data of the temporary decoded word with the longer word length is given priority (.In this way, A part of the created memory map is shown in Table 5.This is the case where the first 3 bits of the provisional decoded word are "001".Other cases can be obtained in the same way.Furthermore,
Information on how many bits of the code word have been decoded is also stored in the ROM.

In this way, the required ROM capacity can be reduced to 2-'2. In the case of a general variable length code, r
- The data for the q-bit provisional decoded word is rea*x whose first r-q bit is the provisional decoded word. Address 2 of q bit (r"°"-r)° All 9 words have corresponding data. Add mφ (rlmax r) O's to the end of the word so that the total is realm m bits. If addresses overlap, give priority to the data for the code word with the longer word length. .

Next, the 12-bit signal output from the ROM (not all bits are data words) is sent to a 12-bit output shift register. At the same time, information on how many bits of the code word have been decoded is sent from the ROM to the latch signal generation circuit, and when a 10-bit code word is converted from (r, , -r), q, the input The next latch signal is generated when ten new bits are input to the shift register. The code word sent to the output shift register is serially converted and output bit by bit. However, although not shown in FIG. 1, the output shift register includes an input shift register and (r-,,-r).
-q A clock 275 times that of the latch signal generation circuit is supplied, and the output shift register is configured to shift by 4 bits while the input shift register shifts by 10 bits.

[Other Examples]

Next, apply it to the (5, 16, 2, 6, 4) code. This code has basic data word length m = 2, basic code word length n = 6, code word length number r□8 = 4, T, , = 2.0, Tffi
, , =5.7, T, =0.33.

Table 6 shows a correspondence table between data words and code words. The configuration of the decoding device is shown in Figure 1, with 24 input shift registers.
The output shift register is 8 bits. or,
The 13 temporary decoding circuits in FIG. 1 become four. The basic number of code words is 7, which can be provisionally decoded with q=3.

The correspondence between the basic code word and the provisional decode word is shown in Table 7. Therefore, the correspondence table (part) of temporary decoded words and output data words is as shown in Table 8. Table 9 shows the first three tentatively decoded words.
bit is “100” (corresponding basic code word is “0001”)
00''), and there are no duplicate addresses.

Other cases can be found in the same way. In this code, ROM
Capacity can be reduced to 2-12. The circuit operation is (4, 19,
2, 5, 6) This is the same as the explanation using the symbols.

Table 6 (3, 16, 2, 6, 4) Code data word-code word correspondence table Data word Code word (,0111) 0000100000
00 (101111) oo1oooooo
ootoooo6o.

(110001) ””00010000010
0000000 Table 7 Basic code word (temporary decoded word) 000000 (OOQ) No.
8 Table data word Temporary decoded word 10QI 0(10(101st
9 Table address data (a) 1
00100100000 1111
1010(b) 100100000000...10
0100000111 1100010010010
1000000...100101000111 1
1001000100110000000...100
110000111 11001100(c) 10
0000000000 ・100000111111
01100000 [Effects of the Invention] As explained above, the present invention utilizes the fact that the basic number of n-bit code words is smaller than the number of code words that can be represented by n bits in a variable-length RLL code decoding device, and performs decoding on a temporary basis. By separating decoding and final decoding, we were able to significantly reduce the ROM capacity required for the circuit. For this reason, even if recording becomes more dense and the scale of recorded codes becomes larger, a decoding circuit can be configured with a small ROM capacity, and its practical cost is very high.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the present invention. FIG. 2 is a block diagram showing the configuration of a conventional decoding device using ROM.

Claims (4)

[Claims] (1) When the basic data word length is m bits and the basic code word length is n bits, convert an r m bit data word to an r n bit code word for an integer r such that 1≦r≦r_m_a_x 2, which is caused by the connection between code words after conversion.
Inverse converting each code word of a variable length RLL (run length limited) code that limits the number of runs of “0” between “1” and “1” in a base code bit string to d or more and k or less a decoding device for dividing an input codeword into r_m_a_x blocks each having n bits;
1. A variable length code inverse conversion device comprising: means for temporarily decoding each block into q bits; and means for finally decoding r_m_a_x·q bits as a result of the temporary decoding. (2) The number of basic codewords of n bits, which is the basic codeword length, is p
and when the temporary decoding means outputs a q-bit code according to the p patterns for each n-bit block, q is the smallest integer satisfying p<2^q. A variable length code inverse conversion device according to claim 1. (3) The final decoding means outputs a data word pattern of r_m_a_x·m bits that is uniquely specified by the code of total r_m_a_x·q bits output from the temporary decoding means. 2. The variable length code inverse conversion device according to item 2. (4) The variable length code inverse conversion apparatus according to claim 1, wherein the temporary decoding means is constituted by a memory or a gate circuit, and the final decoding means is constituted by a memory.