JPH0230237B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a switching device in a digital communication system that accesses toll subcarriers.

The type of communications switching equipment for which the present invention finds utility is based on the building blocks of a series of multiplexers and concentrators, all capable of satisfying several subcarriers and signal types. These building blocks can be included in a highly flexible range of configurations to meet customer switching equipment specifications.

It is an object of the present invention to provide a new switching device for controlling switched connections between traffic channels and highway group terminations in a much more efficient manner than the known prior art.

Yet another object of the present invention is to propose a novel and highly useful scheme for controlling switching connections between traffic channels and highway group terminations, in particular the use of loopland control registers.

According to the present invention, there is provided a switching device in a digital communication switching system comprising selection means configured to interface between a plurality of time division multiplexed highway groups and a plurality of channel digital traffic communication paths. and the selection means is configured to implement a plurality of different switched connection modes enabling bi-directional communication between the channel digital traffic communication path and the time division multiplexed highway group; a control microprocessor controlled to effectuate said bi-directional communication within a group and within said channel digital traffic communication path, regardless of whether operating input/output data rates of a particular switching connection mode are compatible or not; be.

The invention will be better understood from the following description of embodiments in conjunction with the accompanying drawings.

Referring to the figure, the selection means includes four 1 Mbit/s time division multiplexed TDM groups GOT and GIN;
32Kbit/second, 64Kbit/second or 1Mbit/second
A programmable general purpose bus selector PUBS provides a universal interface between an incoming channel CI and an outgoing channel COT of up to 6 subcarriers operating between any of three different channel speeds in seconds.

The programmable general-purpose bus selector PUBS is controlled by the microprocessor interface MFI, which is used to configure various connection configurations and to control these connections via 16x7 bit registers. Used when reading the configuration.

Since both data and signals are switched by the programmable general purpose bus selector PUBS, there is considerable utility in subcarrier multiplexing and common channel signaling.

Programmable general purpose bus selector PUBS is 40
Figure 1 shows a block diagram of the multiple interfaces, which are integrated into a dual-in-line case of pins.

The 1MHz signal is output from the master clock (not shown) of the telecommunications exchange, where is the frame signal, is the reset signal, is the signal to select a particular configuration of the group, VS is the power supply, and is the chip/chip signal.
enable signal, is read enable signal,
WE is the write enable signal. The meanings of these signals will be described later. Bus ADD/
DATA is the transfer path for addresses and data between the microprocessor and the programmable general purpose bus selector PUBS. Group GOS relates to time division multiplexed (TDM) transmissions to time division multiplexed highway TDMH, while group GIN relates to time division multiplexed transmissions from time division multiplexed highway TDMH.

At channel speed, traffic to the programmable general purpose bus selector PUBS is routed to the signal line CIN.
programmable general-purpose bus selector
The traffic output of PUBS is sent to the outgoing channel COT at the channel rate.

When referring to the general block diagram of FIG. 2, one should recall the multiplexer applied to the programmable general purpose bus selector PUBS. Programmable general-purpose bus selector PUBS, and future subcarrier traffic, loop modem LM
The subcarrier traffic interface STI terminates at the subcarrier traffic interface STI. The microprocessor control interface MCI shown is directly connected to the control highway CH and the signal interface
SI and programmable general purpose bus selector PUBS
connected to both. Programmable general-purpose bus
Selector PUBS is a time division multiplex highway
Connected directly to the TDMH, there are four signals and traffic appropriately selected from any one of six pairs of input/output signal lines to or from the programmable general purpose bus selector PUBS. A plurality of line modules are provided, two of which are shown, LM1 and LM2.

A block diagram of the programmable general purpose bus selector PUBS is shown in FIG. The programmable general-purpose bus selector PUBS has four main areas:
It will be understood that it consists of a timing area TIA, a control area CA or traffic area TRA, and a group interface area GIA.

The timing domain TIA provides a clock timing signal T to the programmable general purpose bus selector PUBS and also provides a time division multiplexed address TA from the timing generator TG. This timing generator TG is supplied with a 1MHz master clock signal and a frame signal FM.
A more detailed block diagram of the timing area TIA is shown in FIG.

The control area CA is equipped with a control and status register CTR and is connected to the bus ADDR/DATA.
and other control signals, i.e. readout signals.
RE, write enable signal, chip enable signal, signal and reset signal
Connected to RESET. Control area CA is used as control interface CI and status interface SI. Furthermore, a detailed block diagram of the control interface CI is shown in FIG.

The group interface area is associated with the connection of the time division multiplex highway TDMH (FIG. 2).

Two highway groups, i.e. highway input
GIN and highway group output GOT each consist of four independent signal lines G0 to G3. unit
GLS stands for group loop round selector means and unit GOSR stands for group output selector means and remaining retiming means GOSR. A more detailed block diagram of the group interface area GIA is shown in FIG.

The traffic area TRA relates to connections for channel traffic. The incoming channel CIN and the outgoing channel COT each consist of six independent signal lines G0 to G5. Unit TOB represents a plurality of output buffers, and unit TR represents a traffic retiming means. Traffic input sampling is handled by the unit TIS, and loop-round multiplexing means are handled by the unit TIS.
Represented by LM1 and LM2. A more detailed block diagram of the traffic area TRA is shown in FIG.

[Overview] Programmable general-purpose bus selector PUBS has 6
It is configured to interface the signal lines C0 to C5, which are one "channel termination," to the signal lines G0 to G3, which are four "group terminations." Channel traffic transmission speed is 32K bits/
seconds, 64K bits/second, or 1M bits/second. Each group consists of 32 channels of time division multiplexed time slots forming one frame. The group frequency is 1MHz and the frame repetition frequency is
It is 32KHz. The group frequencies are all related to the frequency of the mask clock signal, which is typically 1 MHz.

The allocation of time slots in a group is determined by the framing pulse FMG, which needs to occur only once when synchronizing the programmable general-purpose bus selector PUBS, but can conveniently be generated every frame or every other frame. may be generated.

[Programmable control function] Channel assignment to time slots is
Determined by programming the programmable general purpose bus selector PUBS via the control interface CI. The programmable general purpose bus selector PUBS has 14 programmable registers with 4 address lines and 2 read-only registers.

Control information can be loaded or read via the seven bidirectional data lines by controlling the read enable signal, write enable signal, and chip enable signal.

FIG. 8 shows the address assignment of the control interface CI. The bit allocation is shown in FIG.

A byte control function is configured around each channel processing area to allocate two consecutive control bytes in the address mechanism, as shown as the first byte and second byte in FIG. 8, respectively. The control functions of these bytes will be described later.

Group Output Selection A 4-bit field enables channel data for all combinations of output groups.
When no group is selected, the group output is turned off. (1 is selection) [Group input selection] A 2-bit field is used to select which of the plurality of group inputs will be used to derive the output channel data. (Group 0 for 00 code, channel 1 for 01 code, etc.) [Channel Enable] Enables channel speed output. This channel velocity output is open drain, so
When it is not selected, it is in the off state. ) [Time Slot Selection] Use a 5-bit field to select the time slot used for group input and group output. When the operating mode is 64K bits/second, only the lower 4 bits are used. This field is not selected when 1Mbit/sec is selected.

[32/64K bits/second mode] This control sets 32 bits/second mode when low and 64K bits/second mode when high.
Seconds mode is set.

[1Mbit/sec mode] With this control, when high, 1Mbit/sec mode
Seconds mode is set; when low, 32 bits/second mode is set.

Addresses 12 and 13 are set with diagnostic and initial setting functions as described below. FIG. 10 shows various loop-round connections as well as normal connection modes.

[Channel and Group Loop Round] Byte 12 sets the "channel and group loop round" control for each channel. When set, loops channel inputs back to channel outputs and loops group inputs back to group outputs. These map round modes can be used for diagnostic purposes. The number of group information loop rounds and time slots follow the set mode.

[Loop Round for Channel Diagnostics] This instruction loops back all group inputs to the group inputs in the programmable general-purpose bus selector PUBS.
It becomes possible to diagnose PUBS from channel connection. (1 is loop round).

[Offset] The offset function can be selected for each channel. This feature supports the device group interface.
This compensates for the one time slot delay introduced by the line card. When the offset is set, data is sampled one time slot later and inserted into the time slot one time slot before the time slot specified in the time slot selection field.

[Reset] The reset instruction resets all registers, except for their own.
Clear all registers. This function facilitates initialization of the programmable general-purpose bus selector PUBS after power-on or system failure, and prevents group time slot congestion due to random time slot selection. Once this command is set, before normal operation is enabled,
This command must be cleared. (1 is
RESET).

Channel Monitoring Channel Input Monitoring This is a read-only address that allows the control processor to monitor the presence of data on each of the six channel input lines. When the control processor clock signal is asynchronous to the traffic clock signal, it cannot monitor each bit of data. Therefore, the pattern of data must be determined by sampling and decoding methods within the firmware of the controlling processor. Bit 6 of this field
is always 0.

[Monitoring Channel Output] This is a read address, and is used to monitor whether the control processor is outputting data to each of the six channel output lines. When the channel output enable bit is not set, data can be read, but
This provides diagnostic capabilities for complex traffic signal lines when using external traffic sources. Bit 6 of this field is always 0.

[Hardware Control Functions] Two hardware control functions are provided as described below.

[RESET] When this reset signal RESET is low, all programmable general purpose bus selectors PUBS are reset. This reset signal RESET
is typically supplied to a power-on reset or manual reset circuit.

[LOCK] This signal LOOK sets the group loop round on all channels to form a device control ring system.

[Programming Control] This control line is used for programming or monitoring the programmable general-purpose bus selector PUBS, and will be described later.

[Chip Enable Signal] This chip enable signal CE must be held low when performing a read or write operation. When this chip enable signal CE is not set, all address and data lines are disabled, which minimizes the power consumption of the chip even if other device elements are connected to the control bus. do.

[Read enable signal] This read enable signal and chip
When the enable signal is low, data held in the addressed register is enabled to enter the tristate data interface.

[Write signal] When the logical sum of the write enable signal and the chip enable signal changes from a high state to a low state, the data on the tristate data bus is input to the addressed register by clock drive. let

[Mode Description] [Overview] The device is associated with the following modes of operation.
This will be explained below.

a 32K bits/second channel versus 1M bits/second group mode, b 64K bits/second channel versus 1M bits/second group mode, c 1M bit/second channel versus 1M bits/second group mode, d channel and group loop round mode, e Channel diagnostic loop round mode, f LOCK loop round mode.

[Transmission direction from 32K bit/sec channel to 1M bit/sec mode] In this direction, as shown in Figure 11,
One of the 32 channels at 1 Mbit/sec is selected and output as a 32 Kbit/sec data stream on one channel output.

If “Offset” is not set,
Sample data on the trailing edge of the 1M bit clock signal at the center of the selected channel.
When ``Offset'' is set, data is sampled after one period of the 1MHz clock signal.

Channel interface data is sent out at the beginning of a group frame period.

Data sampled from one frame always appears at the channel output of the next frame, except for channel 31, which appears one frame later in offset mode.

[Incoming direction] In this direction, as shown in Fig. 11,
1M data for one channel interface
Bits per second are multiplexed into one channel.
Data is sampled 1 MHz half period before the center of the frame.

If ``Offset'' mode is not set, it will be inserted into the selected time slot and
Sent on the leading edge of the 1MHz clock signal. Data required for channels 16 to 31 is not delayed, but data for channels 0 to 15 is delayed by a maximum of 1/2 frame.

When “Offset” mode is set,
It will be inserted into the time slot immediately before the selected time slot. Data required by channels 17-31 will not be delayed, but data for channels 0-16 will be delayed by a maximum of 1/2 frame.

[Output direction of 64K bits/second channel to 1M bits/second group mode] In this direction, as shown in Fig. 12,
Two channels are selected from a group of 32 channels 1 Mbit/sec and output as a 64 Kbit/sec data stream to one channel output. The two 1 Mbit/s channels used need to be separated by 16 periods of 1 MHz.

If ``Offset'' mode is not set, insert data into the selected time slot. Data is sampled on the trailing edge of the 1MHz clock signal.

When “Offset” mode is set,
Select data after one cycle of 1MHz.

Channel interface data is sent at the beginning and midpoint of a frame period. In offset mode, data sampled in 1/2 frame always appears at the channel outputs in the next 1/2 frame period, except for channel 16, which appears one frame later.

[Incoming direction] In this direction, as shown in Fig. 12,
Channel interface data is multiplexed into two channels at 1 Mbit/s. Data is sampled in 1/2 of a 1 MHz period before 1/4 and 3/4 of the frame.

When “Offset” mode is not set, the data is offset to the selected time slot at 1MHz.
Insert with an offset of 16 cycles. Data is sent out from the 1MHz leading edge. Channel 8-1
Data on channel 1 is not delayed, but on channel 0
The data in ~7 is delayed by 1/4 frame.

When “Offset” mode is set,
It will be inserted into the time slot immediately before the selected time slot. Data for channels 9-15 is not delayed, but data for channels 0-8 is delayed by 1/4 frame.

[Output direction of 1M bit/sec channel to 1M bit/sec group mode] In this direction, as shown in Fig. 13,
1M bits/second of the group interface
Connect to bit/second channel output.

Data is sampled on the 1MHz trailing edge and sent out on the trailing edge of the clock signal. 1MHz data
It is delayed by one period of the clock signal.

Offset mode does not operate in this mode.

[Channel and Group Loop Round Mode] When operated, this mode loops the channel input to the channel output and loops the group input to the group output.

[Channel Loop Round] Data is sampled at:

a Time slot 15 in 32K bit/second mode
trailing edge of the 1MHz clock signal at

b Trailing edge of the 1MHz clock signal in time slots 7 and 23 in 64K bit/s mode.

c Trailing edge of the 1MHz clock signal in 1Mbit/s mode.

Data is sent out at the following times:

a Start of frame in 32K bit/s mode.

b Beginning of time slots 0 and 16 in 64K bit/s mode.

c Leading edge of each 1MHz clock signal in 1Mbit/s mode.

Offset/mode is not affected by channel loop rounds.

Data is delayed by one period no matter what clock signal is selected.

[Group loop round] Data is sampled at:

a For 32K bit/s mode, the trailing edge of the 1MHz clock signal in the selected timeslot in non-offset mode, or 1M after one timeslot in offset mode.
Trailing edge of the Hz clock signal.

b For 64K bits/second mode, 16 timeslots from the selected timeslot in non-offset mode and the trailing edge of the 1MHz clock signal of the selected timeslot;
When offset mode is set, data is sampled one time slot later.

c Trailing edge of each 1MHz clock signal in 1MHz/s mode.

Send data at:

a For 32K bit/s mode, the beginning of the selected time slot in non-offset mode and one time slot before in offset mode.

b For 64K bits/second mode, 16 timeslots away from the selected timeslot in non-offset mode and at the beginning of the selected timeslot. In offset mode, data is sent out one time slot earlier.

c Leading edge of each 1MHz clock signal in 1Mbit/s mode.

[Overview] This mode allows complete diagnosis of the programmable general purpose bus selector PUBS from the group and channel interfaces, except for two gates.

[Loop-round mode for channel diagnosis] In this mode, the group output of the comprehensive programmable general-purpose bus selector PUBS is loop-rounded to the group input, so selective loop-rounding as in other modes is not possible.

This mode allows diagnosis of the traffic signal line of the programmable general purpose bus selector PUBS from the channel connection.

When running this mode, only offset mode testing can be performed using two channels.

The data delay is as follows.

a 32K bit/second mode When time slots 16-31 are selected, data is delayed by one period of 32MHz.
When time slots 0-15 are selected, the data is delayed by two periods of 32KHz.

b 64K bits/second mode When time slots 8-15 or 24-31 are selected, data is delayed by one period of 64KHz. Time slot 0-7 or 16-2
When selecting 3, the data is delayed by two cycles of 64KHz.

c 1Mbit/s mode Data is always delayed by two periods of 1MHz.

LOCK Loop Round Mode This mode is activated by pulling down the programmable general purpose bus selector PUBS pin. This mode loops the incoming group and allows normal operation from the group-to-channel. Channel input is not used. Software selectable group and channel loop-round modes override the LOCK function.

[Interface Description (Timing)] The timings shown in this chapter represent the worst case within the allowable operating range and operating temperature range of -55°C to +125°.

[Control Timing] [Summary] The following timing numbers apply to the programmable general purpose bus selector PUBS and assume a 50 pf load on the data bus. See Figure 14.

[Read cycle] [Read enable to data bus control (
Low to data bus enable (data = 0) (REDE) = max. 60ms Low to data bus enable (data = 1) (REDE) = max. 90ms high to data bus enable (REDE) = max. 90ms Chip Enable to Data Bus Control
= 0)] Low to Data Bus Enable (Data = 0) (CEDE) = 70 ms max Low to Data Bus Enable (Data = 1) (CEDE) = 92 ms max High to Data Bus De Sable (data = 0) (CEDD) = High for maximum 40ms ~ Data bus disabled (Data = 1) (CEDD) = Maximum 48ms [Address change ~ Data valid (and both low) (ADV)] Address Stable ~ Data valid (data = 0) = max. 125 ns Address stable ~ Data valid (data = 1) = max. 200 ns [Chip enable ~ data valid (low) (CEDV)] Chip enable low ~ data Chip enable CE low to data valid (data = 1) = 200 ns max [Write cycle] [Data setting DWES before rising edge of ()]
(Data = 0) = min. 50ns (data = 1) = min. 71ns [Data retention DWEH after rising edge of ()]
(Data = 0) = Minimum 30ns (Data = 1) = Minimum 32ns [Address setting before the falling edge of () AWES] Setting = Minimum 21ns [Address retention after the falling edge of ()
AWEH] Setting = min. 13 ns (data = 1) = min. 71 ns [Setting before rising edge of () CEWES] Setting = min. 80 ns [Setting before rising edge of (WE) (CEWES) Setting = min. 80 ns rising edge of () Hold CEWES after end] Setting = minimum 33ns [Pulse width (WEP)] WE pulse width = 64ns [RESET pulse width] RESET pulse width = minimum 60ns [Traffic area timing] [Summary] Next timing The values apply to the programmable general purpose bus selector PUBS, see Figure 15.

[Group Interface Timing] 400pf on group output on high to low transition
We assumed a load of The rise time on the group bus is determined by the value of the pull-up resistor used and must be added to the given number.

[Group output] 1MHz clock signal high to group output (data =
0) = maximum 100ns 1MHz clock signal high to group output (data =
1) = Maximum 58ns [Group input] Group input setting before 1MHz falling edge 32 or 64K bit/s mode (data = 0) =
Minimum 32ns 32 or 64K bit/s mode (data = 1) =
28ns min 1MHz/sec mode (data = 0) = 39ns min 1MHz/sec mode (data = 1) = 35ns min Group input hold time after 1MHz rising edge 32 or
64Kbit/s mode (data = 0) = 70ns minimum 32 or 64Kbits/s mode (data = 1) = 70ns minimum 1MHz/s mode (data = 0) = 40ns minimum 1MHz/s mode (data = 1) = Minimum 40ns [Channel interface timing] Assuming a 50pf load on the group output during high-to-low transition. It is necessary to determine the value of the pull-up resistor using the rise time in the group bus and add this to the given value.

[Group output] Valid point of channel output from rising edge of 1MHz clock signal A32K bit/s mode (data = 0) = maximum
94ns A32K bit/s mode (data = 1) = maximum
80ns B64K bits/second mode (data = 0) = maximum
94ns B64K bits/second mode (data = 1) = maximum
80ns 1MHz/sec mode (data = 0) = 72ns max 1MHz/sec mode (data = 1) = 58ns max [Channel Input] Channel input set point from before falling edge of 1MHz clock signal C32K bits/sec mode (data = 0) = minimum
0ns C32K bits/second mode (data = 1) = minimum -
8ns D64K bits/second mode (data = 0) = minimum
0ns D64K bit/s mode (data = 1) = min. -8ns 1MHz/s mode (data = 0) = min. 14ns 1MHz/s mode (data = 1) = min. 6ns Channel input retention after falling edge of 1MHz clock signal Point C32K bits/second mode (data = 0) = minimum
142ns C32K bits/second mode (data = 0) = minimum
142ns D64K bits/second mode (data = 0) = minimum
142ns D64K bits/second mode (data = 0) = minimum
140ns 1MHz/second mode (data = 0) = minimum 48ns 1MHz/second mode (data = 0) = minimum 45s [Frame formation] Falling edge of 1MHz clock signal to falling edge of frame pulse = minimum 72ns frame
Rising edge of pulse to falling edge of 1MHz clock signal = minimum 21ns Minimum frame pulse width = 45ns

[Brief explanation of drawings]

Figure 1 shows a programmable general-purpose bus selector.
Figure 2 is a block diagram of a multiplexer applied to the programmable general-purpose bus selector PUBS, Figure 3 is a block diagram of the programmable general-purpose bus selector PUBS, and Figure 4 is a block diagram of the programmable general-purpose bus selector including the PUBS interface. The figure shows a programmable general-purpose bus selector.
Figure 5 is a block diagram of the control area of the programmable general-purpose bus selector PUBS. Figure 6 is a block diagram of the group interface area of the programmable general-purpose bus selector PUBS. Figure 7 is the block diagram of the group interface area of the programmable general-purpose bus selector PUBS. bus·
Block diagram of the timing area of selector PUBS,
FIG. 8 is a diagram showing the address allocation for the control interface, FIG. 9 is a diagram showing the bit allocation for the control interface, FIG. 10 is a block diagram of the loop-round mode of the programmable general-purpose bus selector PUBS, and FIG. 11 is 32KHz
Timing diagram of the data stream associated with a no-offset mode connection, Figure 12 is 64K
Timing diagram of data stream associated with connection in Hz no-offset mode, Figure 13 shows 1M
14 is a timing diagram of data streams associated with a Hz no-offset mode connection; FIG. 14 is a timing diagram of waveforms associated with control timing;
FIG. 5 is a waveform diagram related to the time reference. CA...Control area, CI...Control interface, CIN...Incoming channel, CTR...Control and status register, GIN...Highway input, GLS...Group loop round selector means, GOT...Highway group Output, GOSR
...Group output selector means and remaining retiming means, LM1 and LM2...Loop round multiplexing means, PUBS...Programmable general purpose bus selector, TG...Timing generator, TOB
...output buffer, TR...traffic retiming means, TIS...unit.

Claims (1)

[Scope of Claims] 1. A switching device in a digital communication switching system, comprising selection means configured to interface between a plurality of time division multiplexed highway groups and a plurality of channel digital traffic communication paths. the selection means is configured to implement a plurality of different switching connection modes enabling bi-directional communication between the channel digital traffic communication path and the time division multiplexed highway group; a control microprocessor controlled to effectuate said bi-directional communication within a group and within said channel digital traffic communication path, regardless of whether operating input/output data rates of a particular switching connection mode are compatible or not; The exchange device characterized in that: 2. A switching device in a digital communication switching system according to claim 1, wherein the selection means is driven by a master clock signal,
comprising clock timing means for providing internal timing signals for said selection means, and first and second register means configured to be program controlled from said control microprocessor;
The exchange device characterized by: 3. A switching device in a digital communication switching system according to claim 2, wherein the first register means is provided for each of a plurality of channel digital traffic communication paths, and the second register means is provided for each of a plurality of channel digital traffic communication paths. Loop-round control register means for controlling the connection of the channel digital traffic communication path and highway group; offset control register means for controlling time slots read from and written to the highway group; incoming and outputting; channel・
The switching device characterized in that the channel digital traffic communication path includes channel monitoring control register means for monitoring the traffic communication path. 4. A switching device in a digital communications switching system as claimed in claim 3, wherein said first register means is constructed from two independent bytes, the first said byte storing channel data into a highway group. a 4-bit field for any combination of outputs, a 2-bit field for selecting which input of the highway group is used in deriving the output channel data, and a 1-bit field for energizing the channel speed output. The second byte consists of a 5-bit field that selects the time slot to be used for the highway I/O group, a 1-bit field that controls two independent data rate processing modes, and further different data. and a 4-bit field for controlling a speed processing mode. 5. A switching device in a digital communication switching system according to claim 4, wherein the loop round control register means has a 1-bit field for each of a plurality of channel digital traffic communication paths, and a diagnostic connection. a 1-bit field of
The offset control means controls the plurality of channels.
The channel supervisory control register means is formed to include a one bit field for each of the digital traffic channels and a one bit field for register reset means, the channel supervisory control register means being configured to include a one bit field for each of the channel digital traffic channels. The switching device is characterized in that it is configured to include one bit fields for each. 6. A switching device in a digital communication switching system as set forth in claim 5, wherein the selection means selects a channel from which the associated channel input corresponds when a bit of a channel digital traffic communication path is set. Loop to output
3. A switching device characterized in that said switching device includes multiplexing means configured to loop back said incoming highway group to a corresponding highway group. 7. The switching device in the digital communication switching system according to claim 5, wherein the selection means, when the diagnostic connection bit is set,
It is characterized by comprising a loop-round selector configured to loop back all the outgoing highway groups to corresponding incoming highways in the selecting means so that the selecting means can be diagnosed from a channel digital traffic communication path. The exchange device. 8. A switching device in a digital communication switching system according to claim 5, which includes the highway group interface device, and when an offset bit is set, 1
Compensation for time slot delays is indicated by the interface device such that data is sampled one time slot later than the time slot specified in the time slot selection field of the second byte. The switching device is characterized in that data is transmitted one time slot in advance. 9. A switching device in a digital communication switching system as claimed in claim 5, wherein the channel monitoring register means is a read-only memory, and the control microprocessor is configured to store data when the channel monitoring bit is set. are respectively input to the channel traffic input path,
Alternatively, the switching device monitors the state output from the channel traffic output path. 10. A switching device in a digital communication switching system according to claim 5, wherein the selection means, when set, sets the loop-round connection of the highway group to all channels digital traffic communication paths. The exchange device characterized in that it is provided with a lock control.