JPH02302172A - Picture processing system - Google Patents

Abstract

PURPOSE:To obtain a reduced picture with high accuracy corresponding to a magnified size by using a readout clock with a higher frequency than that at a clock at write so as to read a data at the readout from a storage means so as to apply 2nd picture reduction. CONSTITUTION:A write control circuit 3 consists of an N-bit register 31, a thinning designation circuit 30 sending an interleave designation signal corresponding to a desired picture reduction rate, and a thinning control circuit 32 stopping the write of a corresponding picture element data outputted from the N-bit register 31 to a tentative storage means 4 based on the interleave designation signal sent from the designation circuit 30. A picture data inputted to the N-bit shift register 31 from a gate array is sent to the tentative storage means 4 while being shifted sequentially based on the write clock and subjected to thinning processing corresponding to a prescribed reduction rate.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to an image processing device that has an image reduction function and is used in facsimiles, printers, image scanners, etc. The present invention relates to an image processing method for reducing an image while reading out tod-shaped image data at a predetermined clock.

"Prior Art" Conventionally, facsimile machines and image scanners sometimes reduce image information read by an image sensor to a predetermined size and transmit it to the other receiver, and also in laser printers and other page printers. There are cases where the image information developed in the video memory is reduced to a predetermined size and output to the print engine.
As a method of reducing such image information to a predetermined size, for example, a method of reducing the image information by performing pixel data thinning processing on the image information in the scanning line direction at intervals corresponding to a predetermined reduction rate. exists. (Japanese Patent Publication No. 62-43589, etc.) Furthermore, in a device that performs image processing while alternately writing and reading image information in a predetermined scanning line direction into a plurality of line buffers based on a predetermined pixel clock frequency, There is also a method of reducing the image information by differentiating the clock frequency between the time (n) and the time of reading (m), and setting the frequency ratio (m/n) in correspondence with the image reduction rate.

(Unexamined Japanese Patent Publication No. 52-50581, etc.) ``Problems to be Solved by the Invention'' However, in the former method of thinning out pixel data, even if the thinning position of corresponding pixels is devised, the number of pixels differs from the original image. Image information is formed, so it is inevitable that image distortion will occur, and the image distortion is
4mB5 (?OX) A3mB5 (81%) A3 Shun A
5 (50%), which becomes more noticeable as the reduction rate increases,
In particular, when the reduction ratio is less than about 50 to Boz, problems occur in image reproducibility and legibility, and these reductions are virtually impossible.

In addition, in the latter technology, a configuration is adopted in which write and read clocks are generated using multiple clock generators with different frequency division ratios for the original oscillation clock, so in order to obtain a finer scaling ratio, the above-described The original oscillation clock for generating the write and read clocks must be made faster, which increases the cost of the device.

In view of the drawbacks of the prior art, the present invention provides 1! ii) The purpose of the present invention is to provide an image processing method that can obtain a reduced image that is preferable in terms of image reproducibility and legibility without noticeable image distortion even when the reduction ratio is set to 50 to 60 or less. do.

Another object of the present invention is to provide an image processing method that can accurately obtain a reduced image in response to variable sizes without increasing the speed of the original oscillation clock that generates the pixel clock.

"Means for solving the problem" The present invention is only for thinning processing! Instead of performing image reduction without performing image reduction, and instead of performing image reduction only by differentiating the blackout frequency during writing (n) and reading (m), the two are combined and thinning processing is performed when writing to the storage means. A first image reduction is performed in the memory means, and a second image is reduced by using a read clock having a higher frequency than the clock at the time of writing when reading from the storage means.
The present invention is characterized in that it performs image reduction and, as a result, obtains a reduced image of a desired magnification through two-stage reduction processing.

"Operation" According to this technical means, since the desired image reduction ratio is obtained by the multiplier (tlXt2) of the reduction ratio tl on the first stage side and the reduction ratio t2 on the second stage side, each stage In particular, even when the image reduction ratio T is set to a large value of 50-EIO% or less, the apparent reduction ratio in the first stage is reduced, and image reproducibility is improved accordingly.

On the other hand, since the number of thinnings and the thinning interval on the first stage side can be set arbitrarily using a counting means or a shift register, in other words, the reduction rate tl on the first stage side can be set arbitrarily. Therefore, even if the read clock cycle on the second stage side is fixed without being varied, it is possible to easily obtain the image reduction ratio T of the desired magnification, and as a result, the write and read clocks can be generated. There is no need to increase the speed of the original oscillation clock, and only two frequency dividing circuits are required to generate each of the clocks, thus making it possible to avoid complication of the device configuration.

Note that the image reduction rate T is greater than the reduction rate t2 on the second stage side.
If you want to obtain, more specifically, the reduction rate of 75% on the second stage side
86% (A4m B5) or 81%
If you want to obtain a reduction ratio of (B4-eA4), conversely, write the original image data as it is into the storage means using a write clock synchronized with the input clock cycle of the original image data, and when reading from the storage means, In this case, the same pixel may be repeatedly processed while reading using a read clock having a higher frequency than the write clock, and the apparent enlargement process (t3) may be performed, so that t2Xt3 becomes 8.
By setting the repetition rate to 8% or 81%, it is possible to freely obtain reduced images with high reproducibility without being affected by the size of the reduction ratio.

"Embodiments" Hereinafter, preferred embodiments of the present invention will be described in detail by way of example with reference to the drawings. However, unless otherwise specified, the dimensions, materials, shapes, and relative arrangements of the components described in this example are not intended to limit the scope of this invention, but are merely illustrative examples. It's nothing more than that.

FIG. 1 is an overall block diagram showing an image processing apparatus having a reduction function according to an embodiment of the present invention.

For example, I is a video memory that expands and stores the true equivalent image data in a dot shape, and when storing the image data, it is thinned out or repeatedly controlled in the sub-scanning direction in correspondence with a predetermined variable size. It is stored in this condition. (Since the magnification processing in the sub-scanning direction is not an important part of the present invention, its explanation will be omitted.) 2 is a control unit that scans the image data stored in the video memo January every time it scans or every n bits. After being read out in parallel to the shift register 21, the pixel takes in the shift register 21 are sequentially shifted based on an image input clock synchronized with the write clock described later, and are serially output to the write control circuit 3 side. .

The write control circuit 3, as shown in FIG. It consists of a thinning control circuit 32 that stops writing the corresponding pixel data output from the N-bit register 31 to the temporary storage means 4 side based on the signal, and controls the image data input from the gate array to the N-bit register 31. The data is sequentially shifted based on the write clock and thinned out in accordance with a predetermined reduction rate ti, and can be sent to the temporary storage means 4 side.

The temporary storage means 4 consists of two sets of line buffers 41 and 42 that perform toggle operations and a selector 43.
3 to perform writing and reading to and from the line buffers 41 and 42 in parallel based on a predetermined write clock and read clock.

Reference numeral 6 denotes a readout control circuit which reads out the thinned-out image data from the line buffers 41 and 42 via the selector 43 based on a predetermined readout clock, either as is or while repeating processing as necessary. It has almost the same circuit configuration as the write control circuit 3, except for the repetition designation part.

7i A clock generation circuit consisting of a pair of frequency dividers 71 and 72 that generate write and read clocks.The write clock is generated by dividing the original oscillation clock by four using the respective frequency dividers 72, while the original oscillation clock is By dividing the frequency by 3 using the frequency divider 71, the write clock becomes 75%.
A read clock having a clock period of 100 seconds is generated.

According to such embodiments, the effects of the present invention described above can be smoothly achieved.

That is, in this embodiment, the image data once thinned out by the thinning control circuit 3 is stored in the temporary storage means 4, and then read out based on the read clock set to 75 of the write clock cycle. The thinning rate performed by the thinning control circuit 3 can be set lower than the actual reduction rate by the clock period ratio.

For example, if the reduction rate is 70% (B4-eB5), set the thinning rate to 83z, if the reduction rate is 81% (A3-B5), set the thinning rate to 81z, and if the reduction rate is 50% (A3 instant A5), set the thinning rate to 83z. The thinning rate can be reduced to 87%.

In addition, 86% (A4mB5) and 81% (B4-*A4)
If you want to obtain a reduction rate of The matter is as described above.

"Effects of the Invention" As described above, according to the present invention, the reduction rate is 50 to 6o.
Even when the setting is below z, it is possible to obtain a reduced image that is preferable in terms of image reproducibility and legibility without noticeable image distortion. There is no need to speed up the original oscillation clock that generates the pixel clock, and as a result, the device configuration is simplified.

It has various effects such as

[Brief explanation of drawings]

FIG. 1 is a schematic block diagram showing an image processing apparatus for image reduction according to an embodiment of the present invention. FIG. 2 is a block diagram showing a thinning control circuit used in the processing device.

Claims (1)

[Claims] 1) In an image processing method in which image data is reduced in a predetermined scanning line direction while writing to and reading from a storage means at a predetermined clock, a first thinning process is performed when writing to the storage means. A second image reduction is performed by performing image reduction using a read clock having a higher frequency than the clock at the time of writing when reading from the storage means, and as a result, a desired image is obtained by two-stage reduction processing. 2) An image processing method characterized by obtaining a reduced image with a magnification ratio 2) In an image processing method in which image data is reduced in a predetermined scanning line direction while writing to and reading from a storage means at a predetermined clock, original image data is input. By using a write clock synchronized with the clock cycle to write into the storage means while thinning the original image data, and when reading from the storage means, by using a read clock having a higher frequency than the write clock. Image processing method characterized by obtaining reduced images of a desired magnification 3) By fixing the read clock and changing only the number of pixels to be thinned out at the time of writing to the storage means, reduced images of different magnifications are obtained. The image processing method according to claim 1) or 2), characterized in that: