JPH02301336A - Base band delay lock loop device - Google Patents

Abstract

PURPOSE:To generate an error signal having an excellent time discrimination characteristic by applying A/D conversion to an input PN signal subjected to cosine roll-off waveform shaping in advance and inputting a resulting digital numeral data to an error signal generating circuit to obtain an error signal in response to a time difference between the input PN signal and a copied PN signal. CONSTITUTION:A pseudo noise(PN) signal 1a subjected to the cosine roll-off waveform shaping is inputted to an equipment outputting the copied pseudo noise signal synchronously timewise with an input pseudo noise signal and the input PN signal is converted into a digital numerical data with an A/D converter 22. Then the digital numerical data is used to generate an error signal in response to the time difference between the input PN signal and the copied PN signal 18 with an error signal generating circuit 21a composed of digital circuits. Thus, the error signal generating circuit 21a composed of the digital circuits is used to generate the error signal having an excellent time discrimination characteristic.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a baseband delay lock loop device, which is one of the elemental technologies in the field of spread spectrum communication systems.

[Conventional technology]

A conventional baseband delay lock loop device is described, for example, in the document "Spread Spectrum Communication System" (by Yokoyama, Science and Technology Publishing, 198B). The prior art will be explained below based on this document.

FIG. 5 is a block diagram showing the configuration of a conventional baseband delay lock loop device. In the figure, 1 is a human-powered PN signal which is a baseband signal, 2 is a multiplier, and 3 is an integral time of the input PN signal l. an integrator equal to the repetition period, 4
is a correlator composed of a multiplier 2 and an integrator 3; 5 is a multiplier; 6 is an integrator whose integration time is equal to the repetition period of the input PN signal 1; 7 is composed of a multiplier 5 and an integrator 6 Correlator, 8 is leading correlation output, 9 is lagging correlation output, 10
is a subtracter, 11 is an error signal, lla is an error signal smoothed by a filter described later, 12 is a loop filter, 1
3 is a voltage controlled oscillator (Voltage Control
led 0scillator (hereinafter abbreviated as VCO), 14 is a clock signal output from VCO 13, 15 is a PN that generates the same PN signal as the input PN signal l
signal generator, 16 is the lead P which is the output of the PN signal generator;
N signal, 17 is a delay element whose delay time is equal to 1/2 of the chip period of input PN signal 1, 18 is a duplicate PN signal, 19
2 is a delay element whose delay time is equal to 1/2 of the chip period of input PN signal 1, 20 is a delayed PN signal, and 21 is a correlator 4.
7 and a subtracter 10.

Next, the operation will be explained.

The input PN signal l is an m-sequence code with a rectangular waveform taking a value of 1 or -1, the sequence length is 2'''-1 (m is an integer of 2 or more), and the chip period is Tc. That is, the input The repetition frequency MT of the PN signal 1 is T-(2''-1)Tc.

Further, the PN signal generator 15 is driven by a clock signal 14 output from the VCO 13, and outputs an advanced PN signal 16 which is a PN signal having the same waveform as the input PN signal. The advanced PN signal 16 is input to a delay element 17 whose delay time is Tc/2, and a duplicate PN signal 1B is output.

Further, the duplicate PN signal 18 is input to a delay element 19 whose delay time is T c /2, and the delayed PN signal 2
0 is output.

Here, the duplicate PN signal 18 is generated at a time Δ
The time waveform of input PN signal 1 is delayed by 5p.
N(t), and the time waveform of the duplicate PN signal 18 is 5FXI.
I (t), the time waveform of the advanced PN signal 16 is 82□(
t), the time waveform of the delayed PN signal 20 is 5PNL (t)
Then, Spptm (t) = 5pN(t+Δt)Sput
(t) = SPNl (t Tc/2) −3rn
(t+Δt-Tc/2)SPNL (t) =
SPNl (t+Tc/2n = Spw(t +
Δt+Tc/2), and let the autocorrelation function of the input PN signal 1 be R(τ), i.e., the correlation formed by the multiplier 2 and the integrator 3 whose integration time is T. In the device 4, the input PN signal 1
A correlation calculation is performed between the leading PN signal 16 and the leading PN signal 16, and a leading correlation output 8 is output. Advance phase "5"5PN (1) Sp,
4(t+Δt-Tc/2)dt-R(Δt-Tc/2
).

Similarly, a correlator 7 composed of a multiplier 5 and an integrator 6 whose integration time is T performs a correlation operation between the human-powered PN signal l and the delayed PN signal 20, and outputs a delayed correlation output 9. Ru. The value of the delayed correlation output 9 is expressed as a function Rt of Δt
(Δt), then.

Then, the lagging correlation output 9 is subtracted from the leading correlation output 8 in the subtracter 10, and an error signal 11 is output. If the value of the error signal 11 is a function E(Δt) of Δt, E(Δt)−Rt(Δt)−RL(Δt)−R(Δt
−Tc/2) −R(Δt +Tc/2).

At this time, since the input signal l is an m-sequence code with a sequence length of 2'''-1 (m is an integer of 2 or more), its autocorrelation function R (
τ) has the following value in the range of 1τl<(2′″−2)Tc.

From this, the value E(Δt) of the error signal 11 in the range of 1Δtl<3/2Tc takes the following value.

FIG. 6 shows the value E(Δt) (1
3 is a graph showing the characteristics of Δtl<3/2Tc). 6th
As shown in the figure, the value E(Δt) of the error signal 11
has the following property ■ in the range 1Δtl<3/2Tc
~■ has.

■ The graph of E(Δt) passes through the coordinate origin and is S-shaped.

■ E(Δt) is an odd function of Δt, and when Δt<Q, E(
When Δt)<Q and Δ1>0, E(Δt)>0.

Hereinafter, the above properties (1) to (2) will be collectively referred to as time discrimination characteristics.

As described above, since the error signal 11 has time discrimination characteristics, the error signal 11 is input to the loop filter 12 to remove the influence of noise, and the smoothed error signal 11a output from the loop filter 12 is sent to the VCO 13. By setting the control voltage to , the frequency of the clock signal 14 changes according to the value of Δt. Due to this change in the frequency of the clock signal 14, the PN signal generator 15 operates so that the time difference Δt between the input PN signal 1 and the duplicate PN signal 18 is always Δt−0.
The phase of the leading PN signal 16 outputted from the above also changes. That is, as long as 1Δt l<3/2Tc, the duplicate PN signal 1
8 always follows the input PN signal l in synchronization.

[Problem to be solved by the invention]

Since the conventional baseband delay lock loop device is configured as described above, the error signal generation circuit must be configured using a correlator, and since the correlation calculation is an analog calculation, the correlator is an analog circuit. Therefore, it is difficult to make the gains of the two correlators exactly the same, and this may cause a certain offset voltage to be superimposed on the error signal, degrading the tracking performance. In addition, in order to maintain the best tracking performance, it is necessary to match the gains of the two correlators as much as possible, which requires a lot of time to adjust the error signal generation circuit, etc.
There were problems associated with the use of an error signal generation circuit using a correlator, which is an analog circuit.

The present invention has been made to solve the above-mentioned problems, and it is possible to generate an error signal having good time discrimination characteristics by using an error signal generation circuit configured with a digital circuit. It is an object of the present invention to provide a baseband delay lock loop device that does not require circuit adjustment and does not cause deterioration in tracking performance originating from an error signal generation circuit.

[Means to solve the problem]

The baseband delay lock loop device according to the present invention inputs an input PN signal whose waveform has been shaped into a cosine roll-off in advance to an AD converter, and converts the output digital numerical data of the AD converter into an error signal constructed by a digital circuit. By using this as an input signal to the generation circuit, an error signal corresponding to the time difference between the input PN signal and the duplicate PN signal is obtained.

[Effect]

In this invention, the input PN signal has been subjected to cosine roll-off waveform shaping in advance, and therefore, when sampling is performed at a point other than the Nyquist point of the input PN signal in the AD converter, the input PN signal is output from the AD converter. Digital numerical data is affected by inter-chip interference. Due to the characteristics of the inter-chip interference and the correlation characteristics of the PN signal, an error signal having good time discrimination characteristics is output from the error signal generation circuit constituted by a digital circuit.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing the configuration of a baseband delay lock loop device according to a first embodiment of the present invention. In the figure, 1a is an input PN signal whose waveform has been shaped in advance by cosine roll-off, and 21a is a digital circuit. 22 is an AD converter that samples and quantizes the input PN signal 1a, and 23 is an AD converter 2.
The digital input PN signal, which is the output of 2, is the output of 2.
4 is a digital delay element whose delay time is equal to the chip period of the input PN signal 1a; 25 is delayed digitized input data obtained by delaying the digitized manual PN signal 23 by the digital delay element 24; 26 is a digital multiplier; 27 is a digital integrator whose cumulative time is equal to the repetition period of the input PN signal 1a, 28 is a leading error signal, 29 is a digital multiplier, and 30 is a digital multiplier whose cumulative time is equal to the repetition period of the input PN signal 1a.
N signal ・Digital integrator equal to the repetition period of 1a, 31 is a delayed error signal, 32 is a digital subtracter, 33 is a digital error signal, 33a is a digital error signal smoothed by a filter described later, 34 is a digital・Analog (Digital-t.

-Analog; hereinafter abbreviated as DA) converter;
35 is a delay time of 17 of the chip period of the human-powered PN signal 1a.
2, the delay element 36 is the PN signal generator 1
A delayed duplicate PN signal is obtained by delaying the rectangular waveform duplicate PN signal 18 outputted from 5 by a delay element 35, and 37 is a digital loop filter.

Next, the operation will be explained.

The input PN signal 1a has a sequence length N (N is an integer of 2 or more),
The chip period is Tc, and time t=iTc(i=1.2
．．・Assume that the rectangular waveform PN signal whose directivity is (ate(1°1)) at ``, N) is subjected to cosine roll-off waveform shaping. Therefore, if the repetition period of the input PN signal is T, then T = NTc. , and the human PN signal 1a
If the value at time t is f (t), then r (t) = Σai g (t Tc)人21. However, when g (t) is a single pulse waveform that has been subjected to cosine roll-off waveform shaping, and k is the roll-off rate, the following equation is obtained. g (0)-1, g (jTc)=0 (j=
±1. ±2. −), so f (iTc)=a
(iml, 2..., N), and the input PN signal la
The Nyquist point of is t=iTc (iml, 2°...,
N).

At this time, the clock signal 14 with a period Tc output from the VCO 13 is at time t, =kTc+Tc/2+Δt (
k is an integer) and rises at time 1. =kTc+Δt (
k is an integer). At the rise time of this clock signal 14, the AD converter 22 samples and quantizes the value of the input PN signal 1a, and outputs a digitized human-powered PN signal 23. Therefore, when the analog input signal value at the time of sampling is S, the AD converter 22 quantizes it and outputs a digital signal D (S) (hereinafter, this analog input signal value S and digital output D (
S) is called a quantization rule), then time t=iTc+Tc/2+Δt (iml, 2.
. . , N), the value of the digitized human-powered PN signal 23 is bdirect-D Cf (t)). By inputting this digitized human-powered PN signal 23 to the digital delay element 24 whose delay time is Tc, the delayed digitized human-powered PN signal 25 is outputted at time t=iTc+Tc/2+Δt.
The value C4 of the delayed digitized human-powered PN signal 26 at (iml, 2..., N) is as follows.

Also, in synchronization with the falling time of the black signal 14, P
The N signal generator 15 outputs a duplicate PN signal 18 with a rectangular waveform. Time t=iTc+Δt(iml, 2..., N
) of the replicated PN signal 18 at X! By inputting this replicated PN signal 18, where Xi = a , to a delay element 35 whose delay time is Tc/2, a delayed replicated PN signal 36 is output. Therefore, time t = i
T c + T c / 2 + Δt (i-1,2°・
..., N), the value yi of the delayed duplicate PN signal 36 becomes yl"a!".

This delayed duplicate PN signal 36 and delayed digimole human power PN
A sum-of-products operation with the signal 25 is performed by a digital multiplier 26 and a digital integrator 27 whose integration time is T=NTc, and a leading error signal 28 is output. At this time, the value of the leading error signal 28 is set to the function Et (Δ[) of at
Then, EtcΔt)−1ΣC,·ymA″ is also obtained.

Similarly, the digital multiplier 29 and the integrated time T-NTc
The digital integrator 30 causes delayed replication P
A product-sum calculation is performed on the N signal 36 and the digital input PN signal 23, and a delay error signal 31 is output. At this time, if the value of the delay error signal 3 is a function EL (at) of at, then EL (at) - Σb4 ·yi i .

Then, in the digital subtracter 32, the leading error signal 2
A delay error signal 31 is subtracted from 8 and a digital error signal 33 is output. The value of the digital error signal 33 is a
Let Ea (at) be the number of intervals in t, then E, (at) = Eg (at) - EL (at).

Input PN signal 1a whose cosine roll-off waveform has been shaped in advance
When sampled and quantized by the AD converter 22, the sampling time t-lTc+Tc/2+Δt(i-1, 2,..., N
) does not match the Nyquist point of the input PN signal, the value of the digital input PN signal 23, which is the output of the AD converter 22, is ``hDCf (iTc-Tc/2+Δt
)3 (i-1, 2°..., N) are affected by inter-chip interference. The inter-chip interference characteristics of this cosine roll-off shaped signal waveform and the rectangular waveform PN signal (a
l) (i=1.2...,N), the value Eo (at) of the digital error signal 33 is IΔ
It has good time discrimination characteristics in the range t1<3/2 Tc.

This is shown more specifically in FIG. 2. However, in FIG. 2, the rectangular waveform PN signal (aL) is made into an m-sequence code with a sequence length of 1023, and the input PN signal 1a that has been subjected to cosine roll-off waveform shaping is It is a graph showing the characteristics of the value E, (at) (1Δtl<3/2Tc) of the digital error signal 33 when the off rate k is 10.4 and the quantization rule of the AD converter 22 is. . Note that the rectangular waveform PN signal (al
) have different sequence lengths N (for example, N=2047) or (
at) as a PN signal other than the m sequence (e.g. gold code)
(ar
) have good correlation characteristics, a graph showing almost similar characteristics will be obtained.

As described above, since the digital error signal 33 has good time discrimination characteristics, the digital error signal 33 is inputted to the digital loop filter 37 to remove the influence of noise.
The smoothed digital error signal 33a, which is the output of the digital loop filter 37, is converted by the DA converter 34 into a smoothed error signal 11a, which is an analog voltage signal.
By setting Δt as the control voltage of the VCO 13, the frequency of the clock signal 14 changes according to the time difference Δt between the input PN signal 1a and the duplicate PN signal 18. This clock signal 14
Due to the change in frequency, the phase of the duplicate PN signal 18 output from the PN signal generator 15 always changes to Δt-Q as long as 1Δtl<3/2Tc. That is,
The duplicate PN signal 18 follows the input PN signal 1a in synchronization.

In the above embodiment, the digital delay element 24 has a delay time equal to the chip period Tc of the input PN signal 1a, but the digital delay element 24 has a delay time of 2
It suffices if it is below Tc.

Further, in the above embodiment, the case where the period of the clock signal 14 which is the output of the VCO 13 is equal to Tc is shown,
The period of the clock signal 14 may be Tc/j (j is a positive integer). In this case, by extracting every j outputs of the AD converter 22, data with a sampling time interval of Tc is created, This may be used as the digitized input PN signal 23, and the clock signal input to the PN signal generator 15 may be the clock signal 14 divided by j.

Next, a second embodiment of the present invention will be described when used in a receiving section of a direct sequence spread spectrum communication device.

The device according to the first embodiment described above is an error signal generating circuit 21a.
has the above-mentioned configuration, so when a PN signal with the polarity inverted is input, that is, the value f (t) of the input PN signal 1a at time t becomes f (t)−−Σatg(t 1Tc) 1Tc), the polarity of the digitized input PN signal 23 is also inverted, thereby inverting the polarity of the digital error signal 33. Therefore, when the polarity of the input PN signal 1a may change, the input Even if the value of the time difference Δt between the PN signal 1a and the duplicate PN signal 18 is the same, the polarity of the digital error signal 33 changes as the polarity of the input PN signal 1a changes, so the digital error signal 33 has a time discrimination characteristic. Not satisfied.

However, in the transmitting section of a direct sequence spread spectrum communication device, the information data to be transmitted, which takes a value of 1 or -1, is multiplied by a PN signal with a repetition period equal to the bit period of this information data, and the result is transmitted. Signal. Therefore, in the receiving section of the direct-sequence spectrum communication device, the polarity of the input PN signal 1a changes with the change in the polarity of the information data, so the necessary condition for the digital error signal 33 to have time discrimination characteristics is the digital error. The polarity of the signal 33 is determined only by the value of the time difference Δt between the input PN signal 1a and the duplicate PN signal 18, and is not dependent on the polarity of the input PN signal 1a.

In the device of the second embodiment, the error signal generating circuit 21a is
With the configuration shown in the figure, it is possible to obtain a digital error signal 33 that satisfies the above-mentioned requirements and has good time discrimination characteristics even when the polarity of the input PN signal 1a changes.

In FIG. 3, digital multipliers 38 and 39 square the leading error signal 28 and the lagging error signal 3, respectively. Next, in the digital subtracter 32, the square lead error signal 28a, which is the output of the digital multiplier 38, is converted into the square lead error signal 31, which is the output of the digital multiplier 39.
The signal from which a is subtracted is output as the digital error signal 33. At this time, the square leading error signal 28a and the square lagging error signal 31a have only 0 or positive values, regardless of the polarity of the digitized input PN signal 23.

Therefore, the polarity of the digital error signal 33 does not depend on the polarity of the input PN signal 1a, and the polarity of the input PN signal 1a and the duplicate PN
It is determined only by the value of the time difference Δt of the signal 18. Fourth
The figure shows the parameters of the input PN signal 1a and the AD converter 22.
The value Eゎ (Δ
t) (1Δtl<3/2Tc), and the value Ell (Δt) of the digital error signal 33 by the second embodiment device has good time discrimination characteristics in the range of 1ΔtI<3/2Tc. It shows.

〔Effect of the invention〕

As described above, according to the present invention, a PN signal that has been subjected to cosine roll-off waveform shaping in advance is used as an input signal, and the human-powered PN signal is
Converts the signal into digital numerical data using an AD converter,
However, this digital numerical data is used to generate an error signal corresponding to the time difference between the input PN signal and the duplicate PN signal using an error signal generation circuit made up of a digital circuit. A base that can generate an error signal with good time discrimination characteristics using an error signal generation circuit, does not require adjustment of the error signal generation circuit, and does not cause deterioration in tracking performance originating from the error signal generation circuit. This has the effect of providing a band delay lock loop device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a baseband delay lock loop device according to a first embodiment of the present invention, FIG. 2 is a diagram showing characteristics of a digital error signal in the first embodiment device,
FIG. 3 is a block diagram showing an error signal generation circuit composed of a digital circuit of a baseband delay lock loop device according to a second embodiment of the present invention, and FIG. FIG. 5 is a block diagram showing the conventional baseband delay lock loop device 2, and FIG. 6 is a diagram showing the characteristics of the error signal in the conventional device. In the figure, 1a is an input PN signal that has been previously subjected to cosine roll-off waveform shaping, 13 is a voltage controlled oscillator, 14 is a clock signal, 15 is a PN signal generator, 18 is a duplicate PN signal, and 21a is a digital circuit. Error signal generation circuit, 22 is an AD converter, 23 is a digitized input PN signal, 24 is a digital delay element, 25 is delayed digitized input data, 26.29 is a digital multiplier, 27.
30 is a digital integrator, 28 is a leading error signal, 31 is a delayed error signal, 32 is a digital subtracter, 33° 33a
is a digital error signal, 34 is a DA converter, 35 is a delay element, 36 is a delayed duplicate PN signal, 37 is a digital loop filter, 38, 39 is a digital multiplier, 28a is a square lead error signal, 31a is a square delay error It's a signal. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

[Claims] (1) In a baseband delay lock loop device that outputs a replicated pseudo-noise signal temporally synchronized with an input pseudo-noise signal, pseudo-noise (Pseu
doNoise (hereinafter abbreviated as PN) signal as an input signal, samples and quantizes the input PN signal, and outputs the result as a digital numerical signal.
; hereinafter abbreviated as AD) converter, and an error signal corresponding to the time difference between the input PN signal and the duplicate PN signal is calculated from the digital numerical signal output from the AD converter and output as a digital numerical signal. 1. A baseband delay lock loop device comprising: an error signal generation circuit configured with a digital circuit;