JPH02300981A - Filtering processing device - Google Patents

Abstract

PURPOSE:To execute MTF (modulation transfer function) correction without providing any additional circuit by setting weight information for every group of picture elements symmetrical in both a vertical direction and a horizontal direction centering around a remarked picture element. CONSTITUTION:Two pieces of the weight information J, I about two groups of the picture elements C1, C2 and B1, B2 symmetrical in both the vertical direction and the horizontal direction among the picture elements B1, B2, C1, C2, D1 to D4 centering around the remarked picture element A are set separately in a weight information storage part 2. On the other hand, an arithmetic circuit 3 is constituted so that the sum (C1+C2) of the picture information of the picture elements C1, C2 is obtained by an adder 34, and the value of the sum is multiplied by the weight information J by a multiplier 36, and further, the sum of the product of the picture information of the remarked picture element A and the weight information H obtained by the multiplier 30 is obtained by the adder 40, and the sum (B1+B2) of the picture information of the picture elements B1, B2 is obtained by the adder 31, and the value of the sum is multiplied by the weight information I by the multiplier 38. Thus, the MTF correction can be executed without providing newly any special circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a filtering processing device that performs two-dimensional filter processing on image information read by an image reading device or the like.

[Conventional technology]

A conventional filtering processing device of this type is disclosed in Japanese Patent Laid-Open No. 61-62187.

FIG. 4 shows the circuit shown in FIG. 6 of this document, which consists of a line memory 10° 11 and latches 12 to 17, and is configured to detect the pixel of interest A as the center of the two-dimensional image information read from the original image. The surrounding pixels Bl, B2 . C.I., C.
2, an image information storage unit 1 that stores image information for a total of 9 pixels, D1 to D4, is provided, and the image information of each pixel is manually input to an arithmetic circuit 6, and each pixel is outputted from a weight information storage unit 8. Side weight information H, It, 12°Jl, J
2, Kl- is multiplied by 4, HA, IIBI.

12 B2. J2 C2, JI C1, ni3 D3. K
IDI, to 4 D4. 2D2 is obtained by multipliers 61-69. Then, the product is calculated by adders 70 to 77
The total sum is determined by the adder 77 and sent as filtering output information.

Here, nine pieces of weight information H, II, 12. ...K4 is generally selected so that its sum becomes zero.

In the configuration shown in FIG. 4, the image information and weight information of each pixel are multiplied by independent multipliers 61 to 69, so the number of multipliers and adders increases, and the arithmetic circuit 6 becomes large-scale. There is a problem.

Therefore, as shown in FIG. 5, common weight information is applied to pixels CI, C2, Bl, and B2 above, below, right, and left of the pixel of interest A, and common weight information is also applied to pixels Dl-D4 diagonally above and below. The weight information K is set in the weight information storage section 7, and the CL
, C2, Bl, B2 pixels, (C1+C2)
Addition of + (Bl +82) is performed by adder 91.92.9
5, the multiplier 97 multiplies the common weight information, and for pixels D1 to D4, (Di +D3) +
(B2 + D 4) is added to adder 9B, 64.96
After that, the common weight information K is multiplied by the multiplier 98,
Further, an adder 99 calculates the sum of the products of these multipliers 97 and 98, and an adder 100 calculates the sum of the product HA of the image information and weight information of the pixel of interest A calculated by the multiplier 90 and the sum of the adder 99.
A circuit has been devised in which the following equation is obtained.

[Problem to be solved by the invention]

However, in the circuit of Fig. 5, Bl, B2°CI,
Although the weight information of pixels in each group of C2 and D1 to D4 is common, the modulation transfer function MTF (=contrast of output image/contrast of input image) in the horizontal direction and vertical direction of the read image is actually different. , it must be corrected.

However, Bl, B2. Since it is set in common for each group of CI, C2, and Di-B4, the weight information cannot be changed between B1, B2 and CI, C2, and MTF cannot be corrected without adding a new circuit. There is a problem.

An object of the present invention is to provide a filtering processing device that can correct MTF without providing a separate circuit.

[Means to solve the problem]

The filtering processing device according to the present invention sets weight information for each group of pixels symmetrical to both the vertical axis and the horizontal axis of the filtering operation window.

[Effect]

In the present invention, since weight information is set for each group of pixels that are symmetrical in both the vertical and horizontal directions with the pixel of interest as the center, MTF correction can be performed without providing a separate circuit.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and the same parts as those in FIG. 5 are represented by the same symbols, and the explanation thereof will be omitted.

In FIG. 1, the weight information storage unit 2 stores B1, B2, . Among pixels CI, C2, and DI-B4, pixel C is symmetrical in both the vertical and horizontal directions.
Weight information J for groups I and C2, Bl and B2
, I are set separately. However, the pixel of interest A and DI
As for the -B4 pixel, weight information of H and is set as in the conventional case.

On the other hand, in the arithmetic circuit 3, an adder 34 calculates the sum of image information of pixels C1 and C2 (CI + C2), a multiplier 36 multiplies the sum by weight information J, and a multiplier 30 The adder 40 calculates the sum of the products of the image information of the pixel of interest A and the weight information H, and the adder 31 calculates the sum (Bl +82) of the image information of the pixels B1 and B2.
The multiplier 38 is configured to multiply the sum value by weight information (■). Furthermore, regarding the pixels of Di-B4, the sum of the image information of these pixels is calculated as (DI
+D2 +D3 +D4) into adders 32, 33゜35
After that, the sum value is multiplied by the weight information K in a multiplier 37, the product is added in an adder 39, and the sum of this adder 39 and the sum of the adder 40 are found in an adder 41. , adder 4
1 is configured to send out the output as filtering output information.

Therefore, according to this configuration, arbitrary weight information 1. Since J can be set, MTF correction can be performed without the need to newly provide a special circuit.

FIG. 2 is a circuit diagram showing another embodiment of the present invention. This embodiment uses pixels in the same column that are continuous in the direction orthogonal to the main scanning direction (B2.B2.B
4) are simultaneously read out, the sum of partial products of pixels in the same column is determined, the sum of partial products is delayed by one pixel period, and the sum of the sums of partial products with other columns is determined.

That is, the adder 5 adds the sum of the image information of pixels B2 and B4.
0, the sum (Di +D2) is multiplied by the weight information K in the multiplier 53, and the image information and weight information l of the pixel B2 calculated in the multiplier 54 for the some product K・(D2+D4).
The adder 55 adds the product IB2 of B2. B2. B4
The sum of partial products of pixels in the same column I B2 +K (B2 +
D4) is calculated. This partial product sum is then latched 56
, it is delayed by one pixel period. Then, the output of latch 56 becomes IA+K (CI +C2'). Next, the image information of the next column is simultaneously read out, and the sum (
DZ+D4) is input to the multiplier 52, the product with the weight information J is calculated, and the product is input to the adder 58.

Further, the product of the image information of the pixel B2 and the weight information H is obtained by a multiplier, and the product HB2 is input to the adder 57 manually. Then, the output of the adder 57 is HB2 + IA+J (D2+D4)+K(CI+C
2).

After this, when the output of the adder 58 is delayed by one pixel period by the latch 59, the output of the latch 59 becomes HA+J Bl
+J (CI+C2)+K(D1+D3).

Next, the image information of the last column is simultaneously read out, and the sum value IB2 +K (D2+D4) obtained from the output of the adder 55 is obtained.
is input to the adder 60 and added to the outputs of the five latches.

Then, from the adder 60, HA+I (Bl +
82) +J (CI +C2) +K (old +D2 +
D3 + D4) is obtained.

With this configuration, the configuration of the arithmetic circuit 5 can be further simplified, and the configuration of the image information storage section 1 can also be simplified.

Note that weight information I, J for surrounding pixels to the pixel of interest
, 17 such as 1.1/2.1/4.178 as the value of
When setting 2° (n-integer), the multiplier in which these weight information is manually input can be configured by a shift circuit.

On the other hand, although FIGS. 1 and 2 show the case of 3×3 pixels as the filtering operation window, this is not limited to this, and the same applies to the case of 5×5 pixels as shown in FIG. 3(b). be able to.

In this case, the groups of the filtering operation window Fl in the 3×3 pixel configuration are the groups indicated by C and B, as shown in FIG. As shown in Figure (b), there are groups indicated by C and F and groups indicated by B and E.

〔Effect of the invention〕

As explained above, in the present invention, weight information is set for each group of pixels symmetrical to both the horizontal and vertical axes of the filtering operation window, so MTF correction can be performed without newly providing a special circuit. It can be carried out.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing one embodiment of the present invention, Fig. 2 is a block diagram showing another embodiment of the invention, and Fig. 3 shows weight information when the filtering operation window is set to 3 x 3 and 5 x 5 pixels. FIG. 4 is a block diagram showing an example of a conventional filtering processing device, and FIG. 5 is a block diagram showing another example of the conventional filtering processing device. 1... Image information storage section, 2... Weight information storage section, 3
゜5...Arithmetic circuit, Fl, F2...Filtering operation window, 10.11...Line memory, 12-17,
56.59...Latch.

Claims (2)

[Claims] (1) In a filtering processing device that multiplies two-dimensional input image information consisting of a plurality of pixels by weight information set in a filtering operation window for each pixel and outputs the sum as filtering output image information, the weight information A filtering processing device characterized in that the filtering processing device is configured to set each group of pixels symmetrical to both the vertical axis and the horizontal axis of a filtering operation window. (2) After calculating the sum of partial products of weight information and image information for pixels in the same column that are continuous in the direction perpendicular to the main scanning direction when performing filtering operations, by delaying the sum of partial products, other 2. The filtering processing device according to claim 1, wherein the filtering processing device calculates the sum of partial product sums of columns.