JPH02300680A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02300680A JPH02300680A JP1122527A JP12252789A JPH02300680A JP H02300680 A JPH02300680 A JP H02300680A JP 1122527 A JP1122527 A JP 1122527A JP 12252789 A JP12252789 A JP 12252789A JP H02300680 A JPH02300680 A JP H02300680A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- terminal
- test
- circuit
- display data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000012360 testing method Methods 0.000 claims abstract description 37
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 14
- 238000010586 diagram Methods 0.000 description 10
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 5
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229920000742 Cotton Polymers 0.000 description 1
- 235000002597 Solanum melongena Nutrition 0.000 description 1
- 244000061458 Solanum melongena Species 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野］
本発明は、通電試験を前提とし、フィルムキャリア方式
により実装された半導体装置の回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a circuit of a semiconductor device mounted by a film carrier method on the premise of a conduction test.
［従来の技術］
従来のフィルムに実装された半導体装置の通電試験は、
第３図に示す様に、長尺状のフィルムに連続的に実装さ
れた半導体装置１を個々の半導体装置に切り離した後、
送り穴２２を利用してソケットに固定してソケットから
何本もの制御信号を半導体装置に印加し行なっていた。[Conventional technology] In the conventional conduction test of semiconductor devices mounted on a film,
As shown in FIG. 3, after cutting the semiconductor devices 1 continuously mounted on a long film into individual semiconductor devices,
The semiconductor device is fixed to a socket using the feed hole 22, and a number of control signals are applied from the socket to the semiconductor device.
また個々に切り離さなくとも、数十ｃｍの短尺状に切断
した形態てあればソケッ１へを並べて設置する事により
、数個程度の通電試験が行なえた。In addition, even if the pieces were cut into short pieces of several tens of centimeters in length, they could be placed side by side in the socket 1 to conduct an energization test without cutting them individually.
［発明が解決しようとする課題］
しかし従来技術では、フィルムキャリアを個々の半導体
装置ごとに、あるいは短尺状に切り離さなければ通電試
験は不可能であった。このため通電試験を行なう際に、
ソケットに半導体装置の実装されたフィルムを個々に挿
入するしかならず、膨大な工数を必要とした。[Problems to be Solved by the Invention] However, in the prior art, it was impossible to carry out a current test unless the film carrier was cut into individual semiconductor devices or into short pieces. For this reason, when conducting a current test,
The film with the semiconductor device mounted thereon had to be individually inserted into the socket, which required a huge amount of man-hours.
また半導体装置を実装した長尺状のフィルムを切り離す
ことにより、フィルムキャリアにおける搬送性、加工性
等の大きな利点を損なう事になった。Moreover, by cutting the long film on which the semiconductor device is mounted, the great advantages of the film carrier, such as transportability and processability, are lost.
そこで本発明はこの様な問題点を解決するもので、その
目的とするところは、複数の半導体装置の実装された長
尺状のフィルムを個々もしくは短尺状に切断せずに通電
試験が容易となる半導体装置の回路を提供するところに
ある。The present invention is intended to solve these problems, and its purpose is to easily conduct a current conduction test on a long film on which a plurality of semiconductor devices are mounted without cutting it individually or into short pieces. The purpose of this invention is to provide a circuit for a semiconductor device.
［課題を解決するだめの手段］
” Ｈ”もしくは°Ｌ゛のいずれかの状態をとる事によ
りテストモードとなり、前記テストモードと反対の状態
をとる事により通常モードとなるテスト端子を設け、テ
ストモード時において、少なくとも一つの基本信号から
、動作に必要な別の信号をつくり出す回路を具備するこ
とを特徴とする。[Means to solve the problem] A test terminal is provided, which becomes the test mode by taking either the "H" or °L state, and which becomes the normal mode by taking the opposite state to the test mode. The present invention is characterized in that it includes a circuit that generates another signal necessary for operation from at least one basic signal in the mode.
［作 用］
複数の半導体装置が実装された長尺状のフィルムのまま
、通電試験をするためには、第４図に示す様に長尺状の
フィルム２３の送り穴２２に沿ってフィルム上に電源ラ
イン２５．２６．２７、もしくは信号ライン２８を配置
する。各半導体装置には前記電源もしくは信号ラインに
ジャンパー線２９を用いて半導体装置から延在するり−
１〜に電気的に接続される。フィルム端に出ている電源
もしくは信号ラインに適当な電圧及び信号を与える事に
より、それに接続された半導体装置の通電試験を一度に
行なう事ができる。このときフィルム幅は制約されてお
り、電源、信号ラインの数はおのずと制約される。通電
試験に必要な信号を発生ずる回路を半導体装置内に具備
する事により、電源、信号ライン数を減し、通電試験を
可能とする。[Function] In order to conduct a current conduction test with a long film on which a plurality of semiconductor devices are mounted, as shown in FIG. Power supply lines 25, 26, 27 or signal lines 28 are arranged. Each semiconductor device has a jumper line 29 extending from the semiconductor device to the power supply or signal line.
1 to electrically connected to. By applying an appropriate voltage and signal to the power supply or signal line extending from the edge of the film, it is possible to conduct a current conduction test on the semiconductor devices connected thereto at once. At this time, the film width is restricted, and the number of power supply and signal lines is naturally restricted. By equipping the semiconductor device with a circuit that generates the signals necessary for the energization test, the number of power supply and signal lines can be reduced and the energization test can be performed.
〔実 施 例］
第１図は本発明の一実施例であって、液晶駆動用半導体
装置の回路図を示す。第２図は第１図回路図の動作を説
明するためのタイミング図である。第４図は長尺状のフ
ィルムに実装された半導体装置を通電試験する時の配線
パターン図を示す。[Embodiment] FIG. 1 is an embodiment of the present invention, and shows a circuit diagram of a semiconductor device for driving a liquid crystal. FIG. 2 is a timing diagram for explaining the operation of the circuit diagram of FIG. 1. FIG. 4 shows a wiring pattern diagram when carrying out a current test on a semiconductor device mounted on a long film.
第１図において一点鎮綿で囲まれた部分１が半導体装置
全体を表わし、点線で囲まれた部分２が通電試験用信号
発生回路を示す。In FIG. 1, a portion 1 surrounded by cotton padding represents the entire semiconductor device, and a portion 2 surrounded by dotted lines represents a signal generation circuit for energization testing.
液晶駆動用半導体装置（以降ドライバＩ’Ｃと称す）は
、シフトレジスタ］５を転送りロックで動作させる事に
より、表示データ入力端子３の信号を順次ラッチＡに保
持し、さらにラッチＢにラインラッチされる。ラッチ内
容と、交流化信号入力端子６の状態により、液晶駆動出
力端子１０の電位が決定する。The liquid crystal driving semiconductor device (hereinafter referred to as driver I'C) operates the shift register 5 in a transfer lock mode to sequentially hold the signals of the display data input terminal 3 in latch A, and then transfer the line to latch B. Latched. The potential of the liquid crystal drive output terminal 10 is determined by the contents of the latch and the state of the AC signal input terminal 6.
転送りロック端子４に入力された基本信号は、分周回路
２１により分周信号■及び分周信号■を作成する。分周
信号■及び■とテスト端子５に巧えられる信号はＮＡＮ
Ｄゲート２０に人力され、さらにＮＡＮＤゲ、−ト２０
の出力と、交流化信号入力端子６及び表示データ入力端
子３に与えられた信号がそれぞれ対応するＮＡＮＤゲー
ト１９に入力される。The basic signal input to the transfer lock terminal 4 is used to create a frequency division signal (2) and a frequency division signal (2) by the frequency division circuit 21. The divided signals ■ and ■ and the signal applied to the test terminal 5 are NAN
Human power is applied to D gate 20, and further NAND gate 20
, and the signals applied to the AC signal input terminal 6 and the display data input terminal 3 are input to the corresponding NAND gates 19, respectively.
第４図に示す様に、イネーブル端子］７、ラッチ制御端
子１８、表示データ入力端子３、ナス１一端子５、及び
交流化信号入力端子６を正極電源Ｖｃｃに接続し、転送
りロック端子４に基本信号を人力した場合、テスト端子
の状態が’ Ｈ”のためテストモードとなり分周信号■
はＮＡＮＤゲー１−１９．２０を介して表示データ人力
信号としてラッチ△１４に入力され、ラッチＢ １．３
及びレベルシフタ１２を介して液晶駆動回路１１に達す
る。また分周信号■は液晶交流化入力信号として液晶駆
動回路１１に達する。As shown in FIG. 4, the enable terminal 7, latch control terminal 18, display data input terminal 3, eggplant 1 terminal 5, and alternating current signal input terminal 6 are connected to the positive power supply Vcc, and the transfer lock terminal 4 is connected to the positive power supply Vcc. When the basic signal is input manually, the state of the test terminal is 'H', so it becomes test mode and the frequency divided signal ■
is input to latch △14 as a display data human input signal via NAND game 1-19.20, and latch B1.3
and reaches the liquid crystal drive circuit 11 via the level shifter 12. Further, the frequency-divided signal ■ reaches the liquid crystal drive circuit 11 as a liquid crystal AC input signal.
液晶駆動回路では表示データ及び交流化信号の状態の絹
合せによってスイッチングする駆動１ヘランジスタが決
まるため、分周信号■を表示データ、分周信号■を交流
化信号とする事により、駆動トランジスタを全て時分割
的に動作させる事ができる。In the liquid crystal drive circuit, the drive 1 transistor to be switched is determined by the combination of the display data and AC conversion signal states, so by using the frequency division signal ■ as the display data and the frequency division signal ■ as the AC conversion signal, all drive transistors can be switched. It can be operated in a time-division manner.
第１図においてテス］・端子５を゛Ｌ°°レベルにした
場合は通常モードとなり各ＮＡＮＤゲート２０の出力は
常に゛Ｈ゛レベルとなり、表示データ入力端子３、及び
交流化信号入力端子６に入力された信号が、それぞれ表
示データ及び交流化信号としてドライバーＩＣを制御す
る事になる。In FIG. 1, when terminal 5 is set to 'L°° level, the normal mode is set and the output of each NAND gate 20 is always at 'H' level, and the output from display data input terminal 3 and alternating current signal input terminal 6 is set to normal mode. The input signals control the driver IC as display data and alternating current signals, respectively.
本発明による半導体装置を実装したフィルムのパターン
図は第４図の様になる。長尺状の長尺方向に平行して走
る導電ラインは、電源ライン２５．２６．２７、及び基
本信号ライン２８の合計４本のみである。またドライバ
ーＩＣＩケ当り必要なジャンパー線は２ケのみとなる。A pattern diagram of a film on which a semiconductor device according to the present invention is mounted is shown in FIG. There are only four conductive lines in total that run in parallel in the longitudinal direction of the elongated shape: the power supply lines 25, 26, and 27, and the basic signal line 28. Also, only two jumper wires are required per driver ICI.
信号ラインの数が増加しない事により、フィルムの幅に
よる制約はうけなくなり、またこれによりジャンパー線
の数も減少するため、通電試験時の信頼性も向上する。Since the number of signal lines does not increase, there is no restriction due to the width of the film, and since the number of jumper wires is also reduced, reliability during conduction tests is improved.
以上の様にフィルムに実装された半導体装置の通電試験
を、長尺状のまま容易にしかも安定して行なう事ができ
る。As described above, the conduction test of a semiconductor device mounted on a film can be easily and stably carried out while the device is in a long shape.
〔発明の効果１
以上述べたように本発明によれば、通電試験用信号発生
回路を半導体装置内に具備する事により、通電試験時の
制御信号数が減り、複数の半導体装置が実装された長尺
状のフィルムのまま通電試験をする場合、フィルムの幅
の制約はなくなり、またジャンパー線の数も減じるので
、より安定した信頼度の高い通電試験が容易になるとい
う効果を有する。[Effects of the Invention 1] As described above, according to the present invention, by providing a signal generation circuit for a conduction test in a semiconductor device, the number of control signals during a conduction test is reduced, and a plurality of semiconductor devices can be mounted. When carrying out a current test with a long film, there is no restriction on the width of the film, and the number of jumper wires is also reduced, which has the effect of facilitating a more stable and reliable current test.
第１図は本発明の半導体装置の一例を示す回路図。
第２図は第１図回路図の動作を説明するだめのタイミン
グ図。
第３図は従来の通電試験用信号発生回路を具備しない半
導体装置のフィルムの配線パターン図。
第４図は、通電試験用信号発生回路を具備した本発明の
半導体装置のフィルムの配線パターン図。
１・・・半導体装置部
２・・ 通電試験用信号発生回路
３・・・表示データ入力端子
４・・・転送りロック入力端子
５・・・テスト端子
６ ・・交流化信号入力端子
７・・・液晶駆動用電源端子
８・・・ＧＮＤ端子
９・ ・Ｖｃｃ端子
１０・・・液晶駆動用出力端子
１１・・・液晶駆動回路
１２・・・レベルシフタ
１３・・・ラッチＢ
１４・・・ラッチＡ
１５・・・シフトレジスタ
１６・ ・イネーブルコントロール
１７・・・イネーブル端子
１８・・・ラッチ制御端子
１９ ・ ＮＡＮＤゲート
２０・ ＮＡＮＤゲート
２１・・・分周回路
２２・・・送り穴
２３・・・フィルム
２４・・・液晶駆動用出力配線
２５・・・液晶駆動用電源ライン
２６・・・ＧＮＤ電源ライン
２７・・・Ｖｃｃ電源ライン
２８ ・・基本信号ライン
２９ ・ジャンパー線
以上FIG. 1 is a circuit diagram showing an example of a semiconductor device of the present invention. FIG. 2 is a timing diagram for explaining the operation of the circuit diagram of FIG. 1. FIG. 3 is a wiring pattern diagram of a film of a semiconductor device that does not include a conventional current test signal generation circuit. FIG. 4 is a wiring pattern diagram of a film of a semiconductor device of the present invention, which is equipped with a signal generation circuit for a current conduction test. 1...Semiconductor device section 2...Signal generation circuit for energization test 3...Display data input terminal 4...Transfer lock input terminal 5...Test terminal 6...AC signal input terminal 7... -Power supply terminal for liquid crystal drive 8...GND terminal 9 -Vcc terminal 10...Output terminal for liquid crystal drive 11...Liquid crystal drive circuit 12...Level shifter 13...Latch B 14...Latch A 15... Shift register 16... Enable control 17... Enable terminal 18... Latch control terminal 19 NAND gate 20 NAND gate 21... Frequency divider circuit 22... Sprocket hole 23... Film 24... Output wiring for liquid crystal drive 25... Power supply line for liquid crystal drive 26... GND power line 27... Vcc power line 28... Basic signal line 29 - Jumper line or higher
Claims (1)
テストモードとなり、前記テストモードと反対の状態を
とる事により通常モードとなるテスト端子を設け、テス
トモード時において、少なくとも一つの基本信号から、
動作に必要な別の信号をつくり出す回路を具備すること
を特徴とする半導体装置。A test terminal is provided that enters a test mode by taking a state of either "H" or "L" and enters a normal mode by taking a state opposite to the test mode, and in the test mode, at least one basic signal from,
A semiconductor device characterized by comprising a circuit that generates another signal necessary for operation.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1122527A JPH02300680A (en) | 1989-05-16 | 1989-05-16 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1122527A JPH02300680A (en) | 1989-05-16 | 1989-05-16 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02300680A true JPH02300680A (en) | 1990-12-12 |
Family
ID=14838058
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1122527A Pending JPH02300680A (en) | 1989-05-16 | 1989-05-16 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02300680A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864685A (en) * | 1995-09-19 | 1996-03-08 | Seiko Epson Corp | Semiconductor element |
| US6397342B1 (en) | 1998-02-17 | 2002-05-28 | Nec Corporation | Device with a clock output circuit |
-
1989
- 1989-05-16 JP JP1122527A patent/JPH02300680A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0864685A (en) * | 1995-09-19 | 1996-03-08 | Seiko Epson Corp | Semiconductor element |
| US6397342B1 (en) | 1998-02-17 | 2002-05-28 | Nec Corporation | Device with a clock output circuit |
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