CN109584772B - Display panel, device and driving method - Google Patents
Display panel, device and driving method Download PDFInfo
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- CN109584772B CN109584772B CN201811572471.4A CN201811572471A CN109584772B CN 109584772 B CN109584772 B CN 109584772B CN 201811572471 A CN201811572471 A CN 201811572471A CN 109584772 B CN109584772 B CN 109584772B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
Abstract
The invention provides a display panel, a device and a driving method, which are used for solving the technical problem of poor display effect of the display panel caused by unequal public voltage signals input to all public electrode blocks in the prior art. The display area of the display panel comprises a plurality of public electrode blocks arranged in an array, and the public electrode blocks are reused as touch electrodes; the non-display area of the display panel comprises a signal control line, at least one grid driving circuit, a control circuit and at least one pair of clock signal lines; the input end of the control circuit is electrically connected with the at least one pair of clock signal lines and the signal control line, and the output end of the control circuit is electrically connected with each common electrode block; the control circuit is configured to: and controlling the common electrode blocks to be mutually and electrically connected in a display stage and mutually disconnected in a touch control stage according to the control signal provided by the signal control line and the clock signal provided by the at least one pair of clock signal lines.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a display panel, a display device, and a driving method.
Background
With the development of the self-contained touch display technology, the common electrode of the array substrate of the display panel can be used as the touch sensing electrode for self-contained touch detection, and touch control and display control are performed in a time-sharing manner through time-sharing driving, so that the touch and display functions can be realized simultaneously. Therefore, the touch sensing electrode is directly integrated in the display panel, so that the manufacturing cost is greatly reduced, the production efficiency is improved, and the thickness of the panel is reduced.
Referring to fig. 1, fig. 1 is a schematic structural diagram of a display panel in the prior art, including: a common electrode layer and a routing layer oppositely arranged on the substrate. The common electrode layer is divided into a plurality of common electrode blocks 11 which are arranged in an array, the routing layer comprises a plurality of routing lines 12, and the routing lines 12 are connected with the common electrode blocks 11 in a one-to-one correspondence manner; the integrated circuit 13 of the display panel is disposed at the lower end of the array, and a common voltage signal is supplied to each common electrode block 11 through a plurality of wires 12 of a wire layer.
As can be seen from fig. 1, the length of the trace 12 of the common electrode block 11 connected to the far end of the integrated circuit 13 is far greater than the length of the trace 12 of the common electrode block 11 connected to the near end of the integrated circuit 13, however, the common voltage signal is affected by the resistance and capacitance of the trace itself during the transmission process, the different lengths of the trace 12 will cause different delays of the common voltage signal at the near end and the far end of the integrated circuit 13, and finally cause unequal common voltage signals input to the common electrode blocks 11, which affects the uniformity of in-plane display, and the larger the size of the display panel, the more obvious the effect is.
Disclosure of Invention
The embodiment of the invention provides a display panel, a device and a driving method, which are used for solving the technical problem of poor display effect of the display panel caused by unequal common voltage signals input to all common electrode blocks in the prior art.
In a first aspect, an embodiment of the present invention provides a display panel, which is divided into a display area and a non-display area; the display area comprises a plurality of public electrode blocks arranged in an array, and the public electrode blocks are reused as touch electrodes; the non-display area comprises a signal control line, at least one grid driving circuit, a control circuit and at least one pair of clock signal lines;
each pair of clock signal lines in the at least one pair of clock signal lines is electrically connected with each gate driving circuit in the at least one gate driving circuit in a one-to-one correspondence manner, and the at least one pair of clock signal lines is used for outputting clock signals to control the at least one gate driving circuit to work in a display stage;
the input end of the control circuit is electrically connected with the at least one pair of clock signal lines and the signal control line, and the output end of the control circuit is electrically connected with each common electrode block; the control circuit is configured to: controlling the common electrode blocks to be mutually and electrically connected in a display stage and mutually disconnected in a touch control stage according to a control signal provided by the signal control line and a clock signal provided by the at least one pair of clock signal lines;
the control signal provided by the signal control line is at a low level in the touch control stage if the control signal is at a high level in the display stage, and is at a high level in the touch control stage if the control signal is at a low level in the display stage.
In the embodiment, the control circuit is arranged in the non-display area of the display panel, so that the control circuit controls the common electrode blocks to be electrically connected with each other in the display stage according to the control signal provided by the signal control line and the clock signal of the gate drive circuit, and the common electrode blocks are disconnected with each other in the touch stage. Meanwhile, the clock signal used by the control circuit is the clock signal of the shared grid driving circuit, so that the circuit wiring is very simple, the thinning of the display panel is facilitated, and the process cost is low.
In a second aspect, an embodiment of the present invention provides a display device, including the display panel according to the first aspect of the embodiment or any optional implementation manner of the first aspect of the embodiment.
In a third aspect, an embodiment of the present invention provides a driving method applied to the display panel according to the first aspect of the embodiment or any optional implementation manner of the first aspect, where the method includes:
and loading a clock signal to each pair of clock signal lines in the at least one pair of clock signal lines, and loading a control signal to the signal control line, so that the control circuit controls the common electrode blocks to be electrically connected with each other in a display stage and to be disconnected with each other in a touch stage according to the control signal provided by the signal control line and the clock signal provided by the at least one pair of clock signal lines.
One or more technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:
according to the technical scheme of the embodiment of the invention, the control circuit is arranged in the non-display area of the display panel, so that the control circuit controls the common electrode blocks to be electrically connected with each other in the display stage according to the control signal provided by the signal control line and the clock signal of the gate drive circuit, and the common electrode blocks are disconnected with each other in the touch control stage. Meanwhile, the clock signal used by the control circuit is the clock signal of the shared grid driving circuit, so that the circuit wiring is very simple, the thinning of the display panel is facilitated, and the process cost is low.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of a display panel in the prior art;
FIG. 2 is a schematic diagram of a possible display panel according to an embodiment of the invention;
FIG. 3a is a schematic diagram illustrating a possible routing manner of signal control lines according to an embodiment of the present invention;
FIG. 3b is a schematic diagram illustrating another possible routing manner of signal control lines according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a possible control circuit according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a possible conversion circuit according to an embodiment of the present invention;
FIG. 6a is a schematic diagram of a possible switch circuit according to an embodiment of the present invention;
FIG. 6b is a schematic diagram of another possible switch circuit according to an embodiment of the present invention;
FIG. 6c is a schematic diagram of another possible switch circuit according to an embodiment of the present invention;
FIG. 6d is a schematic diagram of another possible switch circuit according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of another possible display panel according to an embodiment of the invention;
FIG. 8 is a diagram of the CK1, CKB1, CK2, CKB2 and Goff signals in an embodiment of the invention;
FIG. 9 is a diagram of the CK1, CKB1, CK2, CKB2, Goff, and SW signals in an embodiment of the present invention;
FIG. 10 is a schematic diagram of another possible display panel according to an embodiment of the invention;
FIG. 11 is a diagram of the CK1, CKB1, CK2, CKB2, and Goff signals in accordance with the present invention;
FIG. 12 is a diagram of the CK1, CKB1, CK2, CKB2, Goff, and SW signals in accordance with the present invention.
Detailed Description
The technical solutions of the present invention are described in detail below with reference to the drawings and the specific embodiments, and it should be understood that the specific features in the embodiments and the embodiments of the present invention are not intended to limit the technical solutions of the present invention, but may be combined with each other without conflict. Wherein the shapes and sizes of the various elements in the drawings are not to scale and are merely illustrative of embodiments of the invention.
It is to be understood that the terms first, second, and the like in the description of the embodiments of the invention are used for distinguishing between the descriptions and not necessarily for describing a sequential or chronological order. "plurality" in the description of the embodiments of the present invention means two or more.
The term "and/or" in the embodiment of the present invention is only one kind of association relationship describing an associated object, and indicates that three relationships may exist, for example, a and/or B may indicate: a exists alone, A and B exist simultaneously, and B exists alone. In addition, the character "/" herein generally indicates that the former and latter related objects are in an "or" relationship.
The embodiment of the invention provides a display panel, a device and a driving method, which are used for solving the technical problem of poor display effect of the display panel caused by unequal common voltage signals input to all common electrode blocks in the prior art.
Referring to fig. 2, the display panel is divided into a display area 21 and a non-display area 22; the display area 21 comprises a plurality of common electrode blocks 211 arranged in an array, and the common electrode blocks 211 are reused as touch electrodes; the non-display region 22 includes a signal control line 221, at least one gate driver circuit 222, a control circuit 223, at least one pair of clock signal lines 224, and an integrated circuit 225;
each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is electrically connected to each gate driving circuit 222 in the at least one gate driving circuit 222 in a one-to-one correspondence manner, and the at least one pair of clock signal lines 224 is used for outputting a clock signal to control the at least one gate driving circuit 222 to work in a display stage; it should be noted that each pair of clock signal lines 224 actually includes two clock signal lines, and for convenience of illustration in fig. 2, each pair of clock signal lines 224 is represented by only one solid line;
the input end of the control circuit 223 is electrically connected with at least one pair of clock signal lines 224 and signal control lines 221, and the output end of the control circuit 223 is electrically connected with each common electrode block 211; the control circuit 223 is configured to: according to the control signal provided by the signal control line 221 and the clock signal provided by at least one pair of clock signal lines 224, the common electrode blocks 211 are controlled to be electrically connected with each other in the display stage and to be disconnected with each other in the touch stage;
the control signal provided by the signal control line 221 is at a low level in the touch control stage if it is at a high level in the display stage, and at a high level in the touch control stage if it is at a low level in the display stage.
It should be noted that, in the specific implementation, there are many numbers of the gate driving circuits 222, the clock signal lines 224 and the common electrode blocks 211, for convenience of illustration, only a small number of the gate driving circuits 222, the clock signal lines 224 and the common electrode blocks 211 are drawn in the embodiment of the present invention, and a person skilled in the art may set the specific numbers of the gate driving circuits 222, the clock signal lines 224 and the common electrode blocks 211 according to actual requirements, and the embodiment of the present invention is not limited specifically.
In the above scheme, the control circuit is arranged in the non-display area of the display panel, so that the control circuit controls the common electrode blocks to be electrically connected with each other in the display stage according to the control signal provided by the signal control line and the clock signal of the gate drive circuit, and the common electrode blocks are disconnected with each other in the touch stage. Meanwhile, the clock signal used by the control circuit is the clock signal of the shared grid driving circuit, so that the circuit wiring is very simple, the thinning of the display panel is facilitated, and the process cost is low.
Optionally, in a specific implementation process, the control signal provided by the signal control line 221 may be a control signal directly provided by the integrated circuit 225 to the signal control line 221, or may be a control signal provided by the integrated circuit 225 to other circuit modules, and the signal control line 221 shares a control signal of the other circuit modules (such as the gate driving circuit 222), which is not limited in the embodiment of the present invention.
Referring to fig. 3a, when the signal control lines 221 share the control signal of the gate driving circuit 222, the signal control lines are further electrically connected to at least one gate driving circuit 222, and specifically, may be electrically connected to each gate driving circuit of the at least one gate driving circuit 222; the control signal output by the signal control line 221 is also used to control each gate driving circuit 222 to stop working in the touch phase. For example, the control signal of the gate driver circuit 222 common to the signal control lines 221 may be a Goff signal.
Referring to fig. 3b, when the control signal is directly supplied to the signal control line 221 by the integrated circuit 225, the signal control line 221 is also connected to the integrated circuit 225 of the display panel; the control signal provided by the signal control line 221 is specifically a signal generated by the integrated circuit 225 and sent to the signal control line 221.
It should also be noted that each pair of clock signal lines 224 actually includes two clock signal lines, and each pair of clock signal lines 224 is represented by only one solid line for ease of illustration in fig. 3a and 3 b.
This embodiment to the control signal's of signal control line source, provides two kinds of implementation, when solving because the length of walking the line differs will lead to the different technical problem of delay of the public voltage signal of integrated circuit near-end and distal end, can also simplify circuit structure, improves the precision of circuit control, saves technology cost, improves the flexibility and the suitability of scheme.
Optionally, referring to fig. 4, the control circuit 223 specifically includes: a switching circuit 223a and a switching circuit 223 b.
Wherein the switch circuit 223b is disposed at one end of the non-display region 22 away from the integrated circuit 225 of the display panel; for example, when the integrated circuit 225 is disposed below the common electrode block array, the switching circuit 223b is disposed above the common electrode block array.
Wherein, the first kind input end of the conversion circuit 223a is electrically connected with at least one pair of clock signal lines 224, the second kind input end of the conversion circuit 223a is electrically connected with the signal control line 221, the output end of the conversion circuit 223a is electrically connected with the input end of the switch circuit 223b, and the output end of the switch circuit 223b is electrically connected with each common electrode block 211;
wherein the conversion circuit 223a is configured to: in the display period, a first control signal is generated according to the clock signal output from the at least one pair of clock signal lines 224 and the control signal output from the signal control line 221 and is transmitted to the switch circuit 223 b; in the touch time period, a second control signal is generated according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221 and is sent to the switch circuit 223 b;
the switch circuit 223b is configured to: the common electrode blocks 211 are turned on when the first control signal is received, and the common electrode blocks 211 are turned off when the second control signal is received.
It should also be noted that each pair of clock signal lines 224 actually includes two clock signal lines, and each pair of clock signal lines 224 is represented by only one solid line in fig. 4 for convenience of illustration.
Through the embodiment, the conversion circuit generates a first control signal and sends the first control signal to the switch circuit 223b in the display stage based on the clock signals of at least one pair of clock signal lines and the control signals of the signal control lines, controls the switch circuit 223b to conduct each common electrode block 211, generates a second control signal and sends the second control signal to the switch circuit 223b in the touch control stage, and controls the switch circuit 223b to disconnect each common electrode block 211, so that the technical problem that the delays of common voltage signals at the near end and the far end of the integrated circuit are different due to different lengths of wiring can be solved on the premise that the normal time-sharing driving work of the display panel is guaranteed, and the common voltage signals input to each common electrode block are equal finally.
Optionally, the conversion circuit 223a specifically includes a first type of thin film transistor corresponding to each clock signal line 224 in at least one pair of clock signal lines 224, and a second type of thin film transistor corresponding to the signal control line 221; the first input end is specifically a grid electrode and a first electrode of the first thin film transistor; the second pole of the first type thin film transistor is connected with the output end of the conversion circuit 223 a; the second input end is specifically a grid electrode of the second thin film transistor; a first electrode of the second type thin film transistor is connected to a low potential signal line for supplying a low level signal to the gate driver circuit 222, or connected to a high potential signal line for supplying a high level signal to the gate driver circuit 222; the second pole of the second type thin film transistor is connected to the output terminal of the switching circuit 223 a.
For example: referring to fig. 5, the conversion circuit 223a specifically includes transistors T1, T2, T3, T4, and T5. The input terminals of the transistors T1 and T2 are respectively connected to a first pair of clock signals CK1 and CKB1, wherein CK1 and CKB1 correspond to the clock signal of the first driving circuit 222a in the at least one gate driving circuit 222; the input ends of the transistors T3 and T4 are respectively connected to the second pair of clock signals CK2 and CKB2, wherein CK2 and CKB2 correspond to the clock signal of the second driving circuit 222b in the at least one gate driving circuit 222; the gate of the transistor T5 is connected to the Goff signal corresponding to the gate driving circuit 222, and the first electrode is connected to the low-potential signal line for providing the low-level signal VGL to the gate driving circuit 222.
In a specific implementation process, the first pair of clock signals CK1 and CKB1 and the second pair of clock signals CK2 and CKB2 may be the same or different, and the embodiment of the invention is not limited in particular. When any pair of clock signals (e.g., CK1, CKB1) exists in the plurality of gate driving circuits, the transistors (e.g., T1, T2) corresponding to the pair of clock signals may be electrically connected to the pair of clock signals in all gate driving circuits, or may be electrically connected to only the pair of clock signals in some gate driving circuits, and the embodiment of the present invention is not particularly limited.
In a specific implementation process, since the Goff signal and the VGL signal of each gate driving circuit are the same, T5 may be connected to the Goff signal of any one gate driving circuit, or may be connected to the Goff signals of multiple gate driving circuits at the same time, which is not limited herein.
It should be noted that, in the embodiment of the present invention, a first pole of the transistor may be used as its source and a second pole may be used as its drain according to the type of the transistor and the signal of its gate; or, conversely, the first pole of the transistor is used as the drain thereof, and the second pole is used as the source thereof, which is not specifically distinguished herein.
In the embodiment, the transistor design conversion circuit 223a can simplify the circuit structure, improve the accuracy of circuit control, and save the process cost.
Alternatively, the switching circuit 223b includes switching transistors corresponding to the respective common electrode blocks 211 one to one; the gate of each switching transistor is electrically connected to the output terminal of the conversion circuit 223 a.
Wherein the first poles of the switching transistors are electrically connected to each other and/or the first poles of the switching transistors are electrically connected to the common electrode line 226. The common electrode line 226 is located at one end of the non-display area 22 away from the integrated circuit 225 of the display panel, and the signal transmitted in the common electrode line 226 is a common voltage signal. For example, referring to fig. 6a, the first poles of the switching transistors are electrically connected to each other; for another example, referring to fig. 6b, the first electrode of each switching transistor is electrically connected to the common electrode line 226; for another example, referring to fig. 6c, the first poles of the switching transistors are electrically connected to each other and are electrically connected to the common electrode line 226.
Wherein, the second poles of the switch transistors are electrically connected with the common electrode blocks 211 in a one-to-one correspondence.
In the embodiment, the switch circuit 223b is designed by the switch transistor, so that the circuit structure can be simplified, the circuit control accuracy is improved, and the process cost is saved.
Alternatively, in order to reduce the number of wirings in the display panel, the touch signal lines connected to the common electrode blocks 211 in one-to-one correspondence may be extended to one end of the non-display region 22, which is away from the integrated circuit 225 of the display panel, and electrically connected to the second electrode of the switching transistor. For example, referring to fig. 6d, when the integrated circuit 225 is disposed below the common electrode block array, and the switch circuit 223b is disposed above the common electrode block array, the touch signal line 227 (i.e. the trace 12 in fig. 1) connecting the integrated circuit 225 to each common motor block 221 can be extended above the common electrode block array to be electrically connected to the second electrode of each switch transistor in the switch circuit 223 b.
In specific implementation, the gate driving circuit 222 is disposed on the M1 layer of the display panel, each common electrode block 211 is disposed on the M2 layer of the display panel, and the touch signal line 227 can be switched to the M2 layer at a position overlapped with the gate driving circuit 222, preferably at the lower left corner or the lower right corner of the common electrode block array.
The embodiment reduces the wiring in the display panel, further simplifies the circuit structure and saves the process cost.
Alternatively, the transistors in the switch circuit 223b and the conversion circuit 223a are transistors with the same doping characteristics. The circuit structure can be simplified, the circuit control accuracy is improved, and the process cost is saved.
Optionally, the transistor in the embodiment of the present invention may be an N-type thin film transistor or a P-type thin film transistor, and the embodiment of the present invention is not limited in particular.
Next, the details of the case where the transistors are an N-type thin film transistor and a P-type thin film transistor, respectively, will be described:
the 1 st: in the embodiment of the present invention, the transistors are all N-type thin film transistors, and the first electrode of the second type thin film transistor is connected to a low potential signal line for providing a low level signal VGL to the gate driving circuit 222.
In the display phase, each pair of clock signals output by at least one pair of clock signal lines 224 are two square wave signals with a phase difference of 180 degrees, and the control signal output by the signal control line 221 is a low level signal; a first part of the first type thin film transistors and a second part of the first type thin film transistors connected with the at least one pair of clock signal lines 224 are alternately turned on or off along with the high-low level conversion of the received square wave signal, the second type thin film transistors are turned off, and a second pole of the first type thin film transistors in the on state outputs a high level signal to the output end of the conversion circuit 223 a; after the switch circuit 223b receives the high level signal output by the conversion circuit 223a, all the switch transistors in the switch circuit 223b are turned on, so that the common electrode blocks 211 are electrically connected to each other;
in the touch stage, each pair of clock signals output by at least one pair of clock signal lines 224 is a low level signal, and the control signal output by the signal control line 221 is a high level signal; the first type thin film transistors connected to the at least one pair of clock signal lines 224 are all turned off, the second type thin film transistors are turned on, and the second poles of the second type thin film transistors output low level signals to the output terminals of the switching circuits 223 a; upon receiving the low level signal output from the switching circuit 223a, the switching circuit 223b turns off all the switching transistors in the switching circuit 223b, so that the common electrode blocks 211 are disconnected from each other.
The 2 nd: in the embodiment of the present invention, the transistors are all P-type thin film transistors, and the first electrode of the second type thin film transistor is connected to a high potential signal line for providing a high level signal VGH to the gate driving circuit 222.
In the display phase, each pair of clock signals output by at least one pair of clock signal lines 224 are two square wave signals with a phase difference of 180 degrees, and the control signal output by the signal control line 221 is a high level signal; a first part of first-type thin film transistors and a second part of first-type thin film transistors in the first-type thin film transistors connected with the at least one pair of clock signal lines 224 are alternately turned on or off along with the high-low level conversion of the received square wave signal, the second-type thin film transistors are turned off, and the second poles of the first-type thin film transistors in the on state output low-level signals to the output end of the conversion circuit 223 a; after the switch circuit 223b receives the low level signal output by the conversion circuit 223a, all the switch transistors in the switch circuit 223b are turned on, so that the common electrode blocks 211 are electrically connected to each other;
in the touch stage, each pair of clock signals output by at least one pair of clock signal lines 224 is a high level signal, and the control signal output by the signal control line 221 is a low level signal; the first type thin film transistors connected to the at least one pair of clock signal lines 224 are all turned off, and the second type thin film transistors are turned on; the second pole of the second type thin film transistor outputs a high level signal to the output terminal of the switching circuit 223 a; upon receiving the high level signal output from the switching circuit 223a, the switching circuit 223b turns off all the switching transistors in the switching circuit 223b, so that the common electrode blocks 211 are disconnected from each other.
In the embodiment, the control circuit 223 is designed by the N-type thin film transistor or the P-type thin film transistor, so that the circuit structure can be simplified, the accuracy of circuit control can be improved, and the process cost can be saved.
In order to more clearly understand the technical solutions of the embodiments of the present invention, the following detailed description is given with reference to a possible complete embodiment:
referring to fig. 7, the transistors in the display panel shown in fig. 7 are all N-type thin film transistors, the converting circuit 223a includes transistors T1, T2, T3, T4 and T5, and the first poles of the switching transistors in the switching circuit 223b are electrically connected to each other and are electrically connected to the common electrode line 226. The transistors T1 and T2 receive CK1 and CKB1 of the first pair of clock signals, the transistors T3 and T4 receive CK2 and CKB2 of the second pair of clock signals, the gate of the transistor T3 receives Goff signal, and the first pole receives VGL signal.
Referring to fig. 8, fig. 8 is a level diagram of CK1, CKB1, CK2, CKB2, Goff in the display panel shown in fig. 7. In the display period, T1 and T2 in the conversion circuit 223a are alternately turned on or off (specifically, turned on at a high level and turned off at a low level) along with the transition of the high and low levels of the received square wave signal, T3 and T4 are alternately turned on or turned off (specifically, turned on at a high level and turned off at a low level) along with the transition of the high and low levels of the received square wave signal, T5 is turned off, and the output terminal of the conversion circuit 223a outputs the SW signal at a high level, as shown in fig. 9; after the switch circuit 223b receives the high-level SW signal output by the conversion circuit 223a, all the switch transistors in the switch circuit 223b are turned on, so that the common electrode blocks 211 are electrically connected to each other;
in the touch time period, T1, T2, T3 and T4 in the conversion circuit 223a are all turned off, T5 is turned on, T5 outputs a low level (i.e., VGL), and the output terminal of the conversion circuit 223a outputs a SW signal of a low level, as shown in fig. 9; upon receiving the SW signal of low level output from the switching circuit 223a, the switching circuit 223b turns off all the switching transistors in the switching circuit 223b, so that the common electrode blocks 211 are disconnected from each other.
Referring to fig. 10, the transistors in the display panel shown in fig. 10 are all P-type thin film transistors, the converting circuit 223a includes transistors T1, T2, T3, T4 and T5, and the first electrodes of the switching transistors in the switching circuit 223b are electrically connected to each other and are electrically connected to the common electrode line 226. The transistors T1 and T2 receive CK1 and CKB1 of the first pair of clock signals, the transistors T3 and T4 receive CK2 and CKB2 of the second pair of clock signals, the gate of the transistor T3 receives Goff signal, and the first pole receives VGH signal.
Referring to fig. 11, fig. 11 is a level diagram of CK1, CKB1, CK2, CKB2, Goff in the display panel shown in fig. 10. In the display period, T1 and T2 in the conversion circuit 223a are alternately turned on or off (specifically, turned on at a low level and turned off at a high level) with the transition of the high and low levels of the received square wave signal, T3 and T4 are alternately turned on or off (specifically, turned on at a low level and turned off at a high level) with the transition of the high and low levels of the received square wave signal, T5 is turned off, and the output terminal of the conversion circuit 223a outputs the SW signal at a low level, as shown in fig. 12; after the switch circuit 223b receives the SW signal of low level output by the conversion circuit 223a, all the switch transistors in the switch circuit 223b are turned on, so that the common electrode blocks 211 are electrically connected to each other;
in the touch time period, T1, T2, T3 and T4 in the conversion circuit 223a are all turned off, T5 is turned on, T5 outputs high level (i.e., VGH), and the output terminal of the conversion circuit 223a outputs SW signal of high level, as shown in fig. 12; upon receiving the SW signal of high level output from the switching circuit 223a, the switching circuit 223b turns off all the switching transistors in the switching circuit 223b, so that the common electrode blocks 211 are disconnected from each other.
Based on the same inventive concept, embodiments of the present invention further provide a display device, including the display panel in any one of the above-mentioned optional embodiments of the present invention.
Based on the same inventive concept, an embodiment of the present invention further provides a driving method, which is applied to the display panel in any of the above optional embodiments of the embodiment of the present invention, where the method includes:
each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is applied with a clock signal, and the signal control line 221 is applied with a control signal, so that the control circuit 223 controls the common electrode blocks 211 to be electrically connected to each other in the display stage and to be disconnected from each other in the touch stage according to the control signal provided by the signal control line 221 and the clock signal provided by the at least one pair of clock signal lines 224.
Optionally, the controlling of the common electrode blocks 211 to be electrically connected to each other in the display stage and to be disconnected from each other in the touch stage specifically includes:
in the display time period, the switching circuit 223a in the control circuit 223 generates a first control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and transmits the first control signal to the switching circuit 223b in the control circuit 223, so that the switching circuit 223b turns on each common electrode block 211 when receiving the first control signal;
in the touch time period, the switching circuit 223a of the control circuit 223 generates a second control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and sends the second control signal to the switching circuit 223b of the control circuit 223, so that the switching circuit 223b turns off each common electrode block 211 when receiving the second control signal.
Optionally, loading a clock signal to each pair of clock signal lines 224 in the at least one pair of clock signal lines 224, and loading a control signal to the signal control line 221 specifically includes:
in the display phase, each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is loaded with two square wave signals with a phase difference of 180 degrees, and the signal control line 221 is loaded with a low level signal; in a touch phase, each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is loaded with a low-level signal, and the signal control line 221 is loaded with a high-level signal;
in the display time period, the converting circuit 223a in the control circuit 223 generates a first control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and sends the first control signal to the switching circuit 223b in the control circuit 223, so that the switching circuit 223b turns on each common electrode block 211 when receiving the first control signal, specifically including:
the first and second part of the first type of thin film transistors in the switching circuit 223a are alternately turned on or off along with the high-low level conversion of the received square wave signal, the second type of thin film transistors in the switching circuit 223a are turned off, and the second pole of the first type of thin film transistors in the on state outputs a high level signal to the output end of the switching circuit 223a, so that the switching circuit 223b turns on all the switching transistors in the switching circuit 223b after receiving the high level signal output by the switching circuit 223a, and further, the common electrode blocks 211 are electrically connected with each other;
in the touch time period, the converting circuit 223a in the control circuit 223 generates a second control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and sends the second control signal to the switching circuit 223b in the control circuit 223, so that the switching circuit 223b turns off each common electrode block 211 when receiving the second control signal, specifically including:
the first type thin film transistors in the switching circuit 223a are all turned off, the second type thin film transistors in the switching circuit 223a are turned on, and the second poles of the second type thin film transistors output low level signals to the output end of the switching circuit 223a, so that the switching circuit 223b turns off all the switching transistors in the switching circuit 223b after receiving the low level signals output by the switching circuit 223a, and further, the common electrode blocks 211 are mutually disconnected.
Optionally, loading a clock signal to each pair of clock signal lines 224 in the at least one pair of clock signal lines 224, and loading a control signal to the signal control line 221 specifically includes:
in the display phase, each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is loaded with two square wave signals with a phase difference of 180 degrees, and the signal control line 221 is loaded with a high level signal; in a touch phase, each pair of clock signal lines 224 in the at least one pair of clock signal lines 224 is loaded with a high-level signal, and the signal control line 221 is loaded with a low-level signal;
in the display time period, the converting circuit 223a in the control circuit 223 generates a first control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and sends the first control signal to the switching circuit 223b in the control circuit 223, so that the switching circuit 223b turns on each common electrode block 211 when receiving the first control signal, specifically including:
the first and second part of the first type of thin film transistors in the switching circuit 223a are alternately turned on or off along with the high-low level conversion of the received square wave signal, the second type of thin film transistors in the switching circuit 223a are turned off, and the second pole of the first type of thin film transistors in the on state outputs a low level signal to the output end of the switching circuit 223a, so that the switching circuit 223b turns on all the switching transistors in the switching circuit 223b after receiving the low level signal output by the switching circuit 223a, and further, the common electrode blocks 211 are electrically connected with each other;
in the touch time period, the converting circuit 223a in the control circuit 223 generates a second control signal according to the clock signal output by the at least one pair of clock signal lines 224 and the control signal output by the signal control line 221, and sends the second control signal to the switching circuit 223b in the control circuit 223, so that the switching circuit 223b turns off each common electrode block 211 when receiving the second control signal, specifically including:
the first type thin film transistors in the switching circuit 223a are all turned off, the second type thin film transistors in the switching circuit 223a are turned on, and the second poles of the second type thin film transistors output high level signals to the output end of the switching circuit 223a, so that the switching circuit 223b turns off all the switching transistors in the switching circuit 223b after receiving the high level signals output by the switching circuit 223a, and further, the common electrode blocks 211 are mutually disconnected.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (14)
1. A display panel is characterized by being divided into a display area and a non-display area; the display area comprises a plurality of public electrode blocks arranged in an array, and the public electrode blocks are reused as touch electrodes; the non-display area comprises a signal control line, at least one grid driving circuit, a control circuit and at least one pair of clock signal lines;
each pair of clock signal lines in the at least one pair of clock signal lines is electrically connected with each gate driving circuit in the at least one gate driving circuit in a one-to-one correspondence manner, and the at least one pair of clock signal lines is used for outputting clock signals to control the at least one gate driving circuit to work in a display stage;
the input end of the control circuit is electrically connected with the at least one pair of clock signal lines and the signal control line, and the output end of the control circuit is electrically connected with each common electrode block; the control circuit is configured to: controlling the common electrode blocks to be mutually and electrically connected in a display stage and mutually disconnected in a touch control stage according to a control signal provided by the signal control line and a clock signal provided by the at least one pair of clock signal lines;
the control signal provided by the signal control line is at a low level in the touch control stage if the control signal is at a high level in the display stage, and is at a high level in the touch control stage if the control signal is at a low level in the display stage;
the control circuit comprises a switch circuit, and the output end of the switch circuit is electrically connected with each common electrode block; the switching circuit is configured to: switching on each common electrode block in a display stage, and switching off each common electrode block in a touch stage; the switch circuit is arranged at one end of the non-display area, which is far away from the integrated circuit of the display panel;
wherein the control circuit further comprises a conversion circuit; the first input end of the conversion circuit is electrically connected with the at least one pair of clock signal wires, the second input end of the conversion circuit is electrically connected with the signal control wire, and the output end of the conversion circuit is electrically connected with the input end of the switch circuit;
the conversion circuit is configured to: in a display time period, generating a first control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sending the first control signal to the switch circuit; and in a touch control time period, generating a second control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sending the second control signal to the switch circuit.
2. The display panel of claim 1, wherein the signal control line is further electrically connected to the at least one gate driving circuit;
and the control signal output by the signal control line is also used for controlling each grid driving circuit to stop working in a touch control stage.
3. The display panel of claim 1, wherein the signal control lines are further connected to an integrated circuit of the display panel;
the control signal provided by the signal control line is specifically a signal generated by the integrated circuit and sent to the signal control line.
4. The display panel according to claim 1, wherein the conversion circuit includes a first type of thin film transistor corresponding to each of the at least one pair of clock signal lines one to one, and a second type of thin film transistor corresponding to the signal control line;
the first input end is specifically a grid electrode and a first electrode of the first thin film transistor; the second pole of the first-class thin film transistor is connected with the output end of the conversion circuit;
the second type input end is specifically a grid electrode of the second type thin film transistor; a first pole of the second type thin film transistor is connected with a low-potential signal line for providing a low-level signal for the grid driving circuit, or is connected with a high-potential signal line for providing a high-level signal for the grid driving circuit; and the second pole of the second type thin film transistor is connected with the output end of the conversion circuit.
5. The display panel according to claim 4, wherein the switching circuit includes switching transistors in one-to-one correspondence with the common electrode blocks;
the grid electrode of each switching transistor is electrically connected with the output end of the conversion circuit; the first poles of the switching transistors are electrically connected with each other, and/or the first poles of the switching transistors are electrically connected with a common electrode wire; the second pole of each of the switching transistors is electrically connected to the corresponding common electrode block.
6. The display panel according to claim 5, wherein the transistors in the switch circuit and the conversion circuit are both N-type thin film transistors; the first pole of the second type thin film transistor is connected with a low-potential signal wire used for providing a low-level signal for the grid drive circuit;
in a display stage, each pair of clock signals output by the at least one pair of clock signal lines are two square wave signals with the phase difference of 180 degrees, and a control signal output by the signal control line is a low-level signal; a first part of transistors and a second part of transistors in the first type of thin film transistors connected with the at least one pair of clock signal lines are alternately turned on or off along with the high-low level conversion of the received square wave signals, the second type of thin film transistors are turned off, and a second pole of the first type of thin film transistors in the on state outputs high-level signals to the output end of the conversion circuit; after the switching circuit receives the high-level signal output by the conversion circuit, all switching transistors in the switching circuit are switched on, so that the common electrode blocks are electrically connected with each other;
in a touch control stage, each pair of clock signals output by the at least one pair of clock signal lines are low-level signals, and control signals output by the signal control lines are high-level signals; all the first thin film transistors connected with the at least one pair of clock signal lines are closed, the second thin film transistors are opened, and the second poles of the second thin film transistors output low-level signals to the output end of the conversion circuit; after the switching circuit receives the low level signal output by the conversion circuit, all the switching transistors in the switching circuit are closed, so that the common electrode blocks are mutually disconnected.
7. The display panel according to claim 5, wherein the transistors in the switch circuit and the conversion circuit are both P-type thin film transistors; the first pole of the second type thin film transistor is connected with a high-potential signal line for providing a high-level signal for the grid drive circuit;
in a display stage, each pair of clock signals output by the at least one pair of clock signal lines are two square wave signals with the phase difference of 180 degrees, and a control signal output by the signal control line is a high-level signal; a first part of first-class thin film transistors and a second part of first-class thin film transistors in the first-class thin film transistors connected with the at least one pair of clock signal lines are alternately turned on or off along with the high-low level conversion of the received square wave signals, the second-class thin film transistors are turned off, and the second poles of the first-class thin film transistors in the on state output low-level signals to the output end of the conversion circuit; after the switching circuit receives the low-level signal output by the conversion circuit, all switching transistors in the switching circuit are switched on, so that the common electrode blocks are electrically connected with each other;
in a touch control stage, each pair of clock signals output by the at least one pair of clock signal lines are high-level signals, and control signals output by the signal control lines are low-level signals; all the first thin film transistors connected with the at least one pair of clock signal lines are closed, and the second thin film transistors are opened; a second pole of the second type thin film transistor outputs a high level signal to an output end of the conversion circuit; after the switching circuit receives the high-level signal output by the conversion circuit, all the switching transistors in the switching circuit are turned off, so that the common electrode blocks are mutually disconnected.
8. The display panel according to claim 5, wherein the display region includes touch signal lines connected in one-to-one correspondence with the common electrode blocks, and one end of the touch signal lines extending to the non-display region away from the integrated circuit of the display panel is electrically connected to the second electrode of the switching transistor.
9. The display panel according to claim 5, wherein the common electrode line is located at an end of the non-display area away from an integrated circuit of the display panel.
10. The display panel according to any one of claims 4 to 9, wherein the transistors in the switch circuit and the conversion circuit are transistors of the same doping characteristic.
11. A display device characterized by comprising the display panel according to any one of claims 1 to 10.
12. A method of driving a display panel according to any one of claims 1 to 10, the method comprising:
loading a clock signal to each pair of clock signal lines in at least one pair of clock signal lines, and loading a control signal to a signal control line, so that the control circuit controls the common electrode blocks to be electrically connected with each other in a display stage and to be disconnected with each other in a touch control stage according to the control signal provided by the signal control line and the clock signal provided by the at least one pair of clock signal lines;
wherein, control each public electrode piece and connect each other the electricity in the demonstration stage, break off each other in the touch-control stage, include:
in a display time period, enabling a switch circuit in the control circuit to conduct each common electrode block;
in a touch time period, enabling the switch circuit to disconnect each common electrode block;
the making of the switch circuit in the control circuit to conduct each common electrode block specifically includes: a conversion circuit in the control circuit generates a first control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sends the first control signal to a switch circuit in the control circuit, so that the switch circuit conducts each common electrode block when receiving the first control signal;
the making the switch circuit to switch off each common electrode block specifically includes: and a conversion circuit in the control circuit generates a second control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sends the second control signal to a switch circuit in the control circuit, so that the switch circuit disconnects each common electrode block when receiving the second control signal.
13. The method of claim 12, wherein loading a clock signal to each of at least one pair of clock signal lines and loading a control signal to a signal control line comprises:
in a display stage, two square wave signals with the phase difference of 180 degrees are loaded on each pair of clock signal lines in the at least one pair of clock signal lines respectively, and low-level signals are loaded on the signal control lines; in a touch control stage, loading a low-level signal to each pair of clock signal lines in the at least one pair of clock signal lines, and loading a high-level signal to the signal control line;
in a display time period, a conversion circuit in the control circuit generates a first control signal according to a clock signal output by the at least one pair of clock signal lines and a control signal output by the signal control line, and sends the first control signal to a switch circuit in the control circuit, so that the switch circuit turns on each common electrode block when receiving the first control signal, specifically including:
a first part of transistors and a second part of transistors in a first type of thin film transistors in the conversion circuit are alternately turned on or off along with the high-low level conversion of a received square wave signal, a second type of thin film transistors in the conversion circuit are turned off, and a second pole of the first type of thin film transistors in the on state outputs a high level signal to the output end of the conversion circuit, so that the switch circuit turns on all switch transistors in the switch circuit after receiving the high level signal output by the conversion circuit, and further all the common electrode blocks are electrically connected with each other;
in a touch time period, a conversion circuit in the control circuit generates a second control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sends the second control signal to a switch circuit in the control circuit, so that the switch circuit disconnects each common electrode block when receiving the second control signal, specifically comprising:
and the first type of thin film transistors in the conversion circuit are all closed, the second type of thin film transistors in the conversion circuit are opened, and the second poles of the second type of thin film transistors output low level signals to the output end of the conversion circuit, so that the switch circuit closes all the switch transistors in the switch circuit after receiving the low level signals output by the conversion circuit, and further, all the common electrode blocks are mutually disconnected.
14. The method of claim 12, wherein loading a clock signal to each of at least one pair of clock signal lines and loading a control signal to a signal control line comprises:
in a display stage, two square wave signals with the phase difference of 180 degrees are loaded on each pair of clock signal lines in the at least one pair of clock signal lines respectively, and a high-level signal is loaded on the signal control line; in a touch control stage, loading a high-level signal to each pair of clock signal lines in the at least one pair of clock signal lines, and loading a low-level signal to the signal control line;
in a display time period, a conversion circuit in the control circuit generates a first control signal according to a clock signal output by the at least one pair of clock signal lines and a control signal output by the signal control line, and sends the first control signal to a switch circuit in the control circuit, so that the switch circuit turns on each common electrode block when receiving the first control signal, specifically including:
a first part of transistors and a second part of transistors in a first type of thin film transistors in the conversion circuit are alternately turned on or off along with the high-low level conversion of a received square wave signal, a second type of thin film transistors in the conversion circuit are turned off, and a second pole of the first type of thin film transistors in the on state outputs a low level signal to the output end of the conversion circuit, so that the switch circuit turns on all switch transistors in the switch circuit after receiving the low level signal output by the conversion circuit, and further all the common electrode blocks are electrically connected with each other;
in a touch time period, a conversion circuit in the control circuit generates a second control signal according to the clock signal output by the at least one pair of clock signal lines and the control signal output by the signal control line and sends the second control signal to a switch circuit in the control circuit, so that the switch circuit disconnects each common electrode block when receiving the second control signal, specifically comprising:
and the first type of thin film transistors in the conversion circuit are all closed, the second type of thin film transistors in the conversion circuit are opened, and the second poles of the second type of thin film transistors output high level signals to the output end of the conversion circuit, so that the switch circuit closes all the switch transistors in the switch circuit after receiving the high level signals output by the conversion circuit, and further, all the common electrode blocks are mutually disconnected.
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