JPH02299021A - Digital comparator - Google Patents

Abstract

PURPOSE:To monitor the degree of the correlation of a comparison result by constituting the digital comparator with a several-bit exclusive OR gate group which inputs respective bits of digital data A and B and a counting adder for respective gate outputs. CONSTITUTION:The digital data to be compared are inputted from input terminals 102 and 103 and eight combinations of them are arranged corresponding to the respective bits to form parallel input terminals 101. The respective bits are inputted to exclusive OR gates 104, which output '0' at the time of the coincidence and '1' at the time of the discordance. Then the counting adder 105 counts '1's in the outputs of the respective exclusive OR gates 104. A 40-bit binary adder 109 calculates the sum of the output of the counting adder 105 and a decision value input 110 and the result is outputted from an output terminal 111 and a carry 112.

Description

[Detailed description of the invention] [Industrial application field] Regarding digital comparators.

[Prior Art] A conventional digital comparator determines whether two pieces of data match or not, or treats the data as a binary number and compares the magnitude thereof. This digital comparator is essential to digital equipment such as computers, and has been widely used.

Conventional digital comparators were necessary and sufficient for digital equipment, which is characterized by precision.

[Problem to be solved by the invention] However, in recent years, as digital technology has been applied to fields that require ambiguity, conventional digital comparators are unable to deal with ambiguity due to their strictness. It can be difficult. FIG. 3 shows a conventional digital comparator. In a conventional digital comparator, two pieces of data to be compared are input to a negative logic output exclusive OR gate 301 for each bit, and the output thereof is input to a multi-input AND gate 301. Only when the two digital data completely match, the output terminal 303
The conventional digital comparator outputs a judgment of non-coincidence if there is even one mismatched bit, so it is not suitable for making flexible and ambiguous judgments.

For example, when comparing two pieces of digital data to see if they match, even if they match except for one bit,
In other words, a conventional digital comparator outputs a "mismatch" result even when only one bit does not match.

When it is okay to ignore differences of about 1 bit in the data and determine that two pieces of digital data match, if you try to achieve this with a conventional digital comparator, the number of bits of data to be compared will increase. The more difficult it becomes.

Therefore, the digital comparator of the present invention has digital data A,
In the digital comparator that compares digital data B,
A group of exclusive OR gates of several bits each with each bit of digital data A as one input and each bit of digital data B as the other input, and one of the outputs of each gate of the exclusive OR gate group. and a count adder for counting the number of ``1n''.Alternatively, in addition to the exclusive OR gate and the count adder for counting the number of ``1n'', the output of the count adder and the input It is characterized by comprising an adder that performs addition with a judgment value. Alternatively, in addition to the exclusive OR gate and a counting adder that counts the number of "1"s, the feature includes a numerical comparator that compares the output of the counting adder with an input judgment value. do.

[Example code] The digital comparator of the present invention will be explained using figures.

FIG. 1 shows one embodiment of the digital comparator of the present invention.

The digital comparator shown in FIG. 1 compares two pieces of 8-bit data. Two digital data to be compared are inputted from input terminals indicated by 102 and 103, respectively, and the combinations are arranged corresponding to the 8 set bits to form a parallel input terminal 101. Each bit is input to an exclusive OR '7'-t 104, which outputs 0'' if they match, and 1'' if they do not match. And count adder 105
1 at the output of each exclusive OR gate 104 by
You can count how many `` are there.

The counting adder 105 is a 1-bit binary adder 106 .
This is realized by a combination of a 2-bit binary adder 107 and a 3-bit binary adder 108. A 4-bit binary adder 109 calculates the addition of the output of the count adder 105 and the judgment value 110, and the result is sent to the output terminal 11.
1, output from carry 112. Judgment value: human power 110
If all the input data are "θ", each bit of the two data is compared and the number of bits that do not match is outputted from the output terminal 111 as a binary number.

For example, if this output is O, it means that the two data completely match, and if it is 2, it means that the two data have two
It can be seen that there are some mismatched bits, and that they almost match. As described above, by using the digital comparator of the present invention, it is possible to know the degree of coincidence of data (hereinafter referred to as correlation degree; the larger the correlation degree means the greater the degree of coincidence). Depending on the data input from the judgment value manual 110, the 4-pit binary adder 109
In some cases, the output of is a value of 16 or more, in which case "1" is output to the carry output 112. Utilizing this fact, it is possible to determine whether or not two pieces of data have a correlation greater than or equal to the set correlation degree. For example, when attempting to determine that data match when the number of mismatched bits is two or less, the determination value input 110 is set to '13'' (2
Enter "11 (Ll") in hexadecimal notation. Then,
Carry 112 is 0 if there are two or less mismatched bits.
” is three or more, 1' will be output.

Further, FIG. 2 shows a configuration example in which the binary value comparator 204 is replaced with the adder 109 in FIG. 1. The output of the count adder 105 and the value of the judgment value 202 are compared by a binary value comparator 204. In this example, the output of the binary value comparator and the enable input are configured with negative logic. Count adder 10
If the output of 5 is smaller than the judgment value, 0'' is output to the output terminal 206.In other words, as a result of comparing the two digital data, the number of mismatched bits is smaller than the judgment value, and the two data meet the criteria given by the judgment value. This shows that they matched to the above degree.However, if the enable input 203 is disabled, 0'' will not be output to the output terminal 206.

FIG. 4 shows an example in which the digital comparator 401 of FIG. 1 is combined to form a 24-bit digital comparator. The input terminal A402 and the input terminal B4O3 have two 24
Bit data is input to the input terminal C404, and a binary number representing a determination value is input.

Output terminal 111 of digital comparator 401 and judgment value input 1
10 are connected by 405 lines. The carry output 112 of each digital comparator 401 is a large chaor gate 406
are input and the logical sum is taken.

Its output is connected to output terminal 407. 2 when inputting “12” (1100” in binary notation) to the input terminal 404
When there are 3 or less mismatched bits out of 4 bits, the output terminal 407
is filled with nO'', and when there are four or more, it is filled with ``1''.In this way, the digital comparators in Figure 1 can easily be connected in series to form a digital comparator of 8 bits or more. .

An example in which the digital comparator of the present invention is used in an optical disc reproducing device will be described with reference to FIG.

The optical disc 501 has a high recording density and is used as a large capacity recording medium. Although optical discs have a high recording density, errors are likely to occur in data due to minute defects on the recording surface. The bit error rate for magnetic disks is 10-
” bits/bit or less, whereas for optical discs it is around 10-5 bits/bit. Therefore, an error correction code is used for recording on optical discs, and the error correction code installed in the playback device is After the error in the reproduced data is corrected by the correction device 508, the external 513
Data is sent to. However, the stage before that, that is,
Errors in data also cause problems in the process of reproducing data from optical discs. The data is read from the optical disc as an analog signal and then reproduced as serial data 510 by the conversion circuit 502. A specific pattern is embedded in the serial data to indicate the beginning of the data and to achieve byte synchronization. By detecting this specific pattern from the serial data using the pattern detector 507, the playback device can recognize the beginning of the data and achieve byte synchronization of the data. Detection No. 1 512 is the decoder circuit 5
08 and the decoding circuit operates at an appropriate timing, so that the serial data can be correctly decoded. However, since optical discs have a high error rate, this particular pattern may contain erroneous bits, and pattern detectors using conventional digital comparators may fail to discover the particular pattern. .

This is because a conventional digital comparator for determining whether a match or mismatch is used is used to detect a specific pattern, so even if one bit in the specific pattern is incorrect, it will be determined as a mismatch and detection will not be possible. The pattern detector 507 using the digital comparator 504 of the present invention can detect even if an error bit is included in a specific pattern. Serial data 510 is input to shift register 503, and its parallel output is input to the parallel input terminal of digital comparator 504. A specific pattern 505 to be detected is input as data to be compared with this. Then, a determination level 506 corresponding to the allowable number of error bits is input as a determination value input. With this configuration, 9. Even if an error bit exists in a specific pattern in the serial data, if it is within an allowable range, the specific pattern can be detected and a detection signal 512 can be sent to the decoder. Attempting to implement such a function using a conventional digital comparator would increase the circuit scale, making it impractical.

Furthermore, the digital comparator of the present invention can also be applied to pattern recognition. By comparing the input cover pattern with various basic patterns using the digital comparator of the present invention and monitoring the degree of correlation, it is possible to quickly determine which basic pattern the input cover pattern is closest to.

[Effect of the invention] The digital comparator of the present invention is a digital comparator that compares digital data A and digital data B, and inputs each bit of digital data A to one input and each bit of digital data B to the other input. It consists of a group of exclusive OR gates each having a number of bits, and a counting adder that counts the number of "1"s output from each gate of the exclusive OR gate group. Alternatively, the exclusive OR gate and the count adder that counts the number of n1'' are configured with an adder that adds the output of the additive count adder and the input judgment value. In addition to a digital OR gate and a counting adder for counting the number of "1"s, the apparatus is composed of a numerical comparator for comparing the output of the counting adder and the input judgment value.

As a result, when comparing two digital data, it is possible to not only detect a complete match, but also output the number of mismatched bits when there are mismatched bits in the two digital data, or output the number of mismatched bits if the number of mismatched bits is within the judgment value. This makes it possible to make judgments where it is assumed that there is a match. Furthermore, when the digital comparator of the present invention is integrated into an IC, it can be used to compare digital data of arbitrary length by connecting the comparators tC in series.

Furthermore, as explained in the examples of optical discs and pattern recognition, it can be used particularly effectively in fields where flexible, ambiguous data comparison is required. In recent years, flexibility has been required for digital devices. The digital comparator of the present invention facilitates the implementation of flexible digital equipment.

[Brief explanation of drawings]

FIG. 1 is a logic circuit diagram showing an embodiment of the digital comparator of the present invention. 101 Parallel input terminal 104 Exclusive OR gate 105 Count adder 1094-bit binary adder 111 Output terminal 112 Carry output FIG. 2 is a logic circuit diagram showing an embodiment of the digital comparator of the present invention. 202 Judgment value input 204 Binary value comparison FIG. 3 is a logic circuit diagram of a conventional digital comparator. 302 Multi-input AND gate FIG. 4 uses the digital comparator shown in FIG.
A logic circuit diagram that realizes a 4-bit digital comparator. 401 Digital comparator 406 shown in FIG. 1 Multi-input OR gate FIG. 5 is a block diagram in which the digital comparator of the present invention is applied to an optical disc playback device. 501 Optical disk 504 Digital comparator of the present invention 507 Pattern detector or higher

Claims (3)

[Claims] (1) In a digital comparator that compares digital data A and digital data B, each bit of the digital data A is input to one input, and each bit of the digital data B is input to the other input. A digital comparator comprising: a group of exclusive OR gates; and a counting adder that counts the number of "1"s in the output of each gate of the exclusive OR gate group. 2. The digital comparator according to claim 1, further comprising an adder that adds the output of the counting adder and the input judgment value. (3) The digital comparator according to claim 1, further comprising a numerical comparator that compares the output of the adder with an input judgment value.