JPH02206227A - Deciding circuit for binary data - Google Patents

Abstract

PURPOSE:To make a correct bit significant by using a decision circuit to make the digit of a high-order k-set samples significant, deciding an n-bit code, comparing the code with a predetermined erasure code and deciding the digit of a sample value. CONSTITUTION:A cascade connection circuit composed of decision circuits 5, 6-9 stores a digit corresponding to a maximum value in an inputted signal. The result is decoded into a 11-bit binary code and the output of the decision circuits 5-7 is given to an OR circuit 11 and the output of the decision circuits 8, 9 is fed to a selector 10. The selector 10 selects an output from the decision circuit 8 when the content of decision by an erasure code decision circuit 12 is normal and selects an output from the decision circuit 9 when the content is not normal and the output is given to the OR circuit 11. Since the output of the OR circuit 11 is not an erasure code, the output of the erasure code decision circuit 12 is normal. Thus, when the output of the OR circuit 11 is fetched in a proper timing, a correct 4/11 code is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a binary data determination circuit used for processing reproduction signals of magneto-optical disks.

[Conventional technology]

Binary data is recorded on a magneto-optical data recording medium, and it is desired that the encoding method has a high recording density and a high error correction ability. 11 codes are known. This means that 4 bits out of 11 bits are 1°.

(Significant) The other bits are "'O" (insignificance). A binary data string is separated every 8 bits, and a code that uniquely corresponds to this 8-bit bit string is determined. Figure 7(a)
~(b) shows an example of this code.

The 4/11 code data recorded on the magneto-optical disk is reproduced, but the reproduced data needs to be decoded.

That is, a binary data string is obtained from the analog signal obtained by converting the signal optically obtained from the magneto-optical disk into an electrical signal, the 4/11 code is determined from this, and the data is further converted to 8-bit data. .

[Problem to be solved by the invention]

However, the level of the reproduced signal may fluctuate due to dirt on the disk surface or the operation of the optical and electrical parts of the reproduction system.

In addition, as shown in Fig. 2(a), "1" Daijin,
This is less of a problem if the numbers are discrete, but (b) (
As shown in C), the "0'° digit between the 1" digits tends to have a high level due to the influence of the adjacent digits, and the low level "'" digits appear in other "1°" digits.
If there is 1'°, in this case, 10100001010 may be erroneously determined as 11100001000.

The object of the present invention is to establish a circuit for determining the 4/11 code or the /n code in such a decoding process.

[Means to solve the problem]

The determination circuit of the present invention samples an analog signal at a predetermined period, converts it from analog to digital, and first determines an n-bit code by considering the upper digits of the sample value as significant, and then converts this into a predetermined erasure code. Compare, and if this does not apply, establish an n-bit code, and if so, make the digit of the sample value of the 1st place insignificant, and instead, make the digit of the sample value of the (k+1) place significant. It is something.

If the n-bit code obtained in this way is an erasure code, the digits of the 11th-value sample value are made insignificant, and the 1st, 2nd, and so on are the -2, k, k+1 sample values. digits are considered significant.

[Effect]

If a high level analog signal is not a significant bit, this is detected and the correct bit can be made significant.

〔Example〕

The present invention will be explained below based on drawings showing embodiments thereof.

First, I will explain the code system.

The original binary data is 011000111001101011
10-(7), but in 8-bit units 01100011/10011010/1110...
Each 8-bit data is converted into a 4/11 code according to the code table shown in FIG. 7, and this is recorded on a magneto-optical disk.

Theoretically, there can be 4/11 codes, but 256 codes are sufficient for encoding 8-bit data. Therefore, in this embodiment, erasure codes are defined according to the following rules.

(1) A pattern in which “1°’ is 4 consecutive digits (
2) Pattern (3) where the first 3 digits are l°
A pattern in which the last two digits are "1" Figure 1 is a block diagram of the circuit of the present invention, in which an analog signal AS reproduced from a magneto-optical disk (not shown) is converted into an analog/digital (A/D). The generated clock signal CLK is synchronized with the analog signal by the clock pit recorded in the servo byte area of the magneto-optical disk, and is sent to the A/D converter 4. Here, sampling and conversion are performed at the digit cycle of the 4711 code.The clock signal CLK is also supplied to the digit determination circuits 5, 6, 7, 8, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 10, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12 must be selected.
9 clock terminal. The magneto-optical disk has a sub synchronization signal SS in 4/11 code units (subcode).
S is recorded, and this is the "1" digit determination circuit 5, 6, 7, 8.9 and erasure sign determination circuit 12.
It is given as a heliset signal.

“1” digit judgment circuit 5.6... compares the input digital signal with the previously input and latched value, and if the value of the newly input signal is larger, it It latches and outputs the previous latch signal, and if it is small, it outputs that input signal without latching it, and the A/D converter 4 output is "1"" digit judgment circuit 5.
■ Digit judgment circuit 5 (or 6, 7.8
) output is 1 digit judgment circuit 6 (or 7, 8.9)
It is used as input. In other words, the determination circuits 5, 6, . . . 9 are connected in cascade. The cascade circuit of judgment circuits 5, 6, . . . 9 stores the digit corresponding to the signal latched in this way, which is the maximum value of the input signal, as will be explained later, and stores only the corresponding digit. Let ``l'' be 1
It is decoded into a 1-bit binary code and sent to judgment circuits 5, 6 .
7 is input to the OR circuit 11, and determination circuits 8 and 9 are input to the selector IO. The selector 10 outputs the output from the determination circuit 8 when the erasure sign determination circuit 12 outputs an output indicating that the determination content is normal, and outputs the output from the determination circuit 9 when the output indicates that the determination is abnormal. Select and output to the OR circuit 11. The output of the OR circuit is a 4/11 code, which is input to the erasure code determination circuit 12, where it is compared with an erasure code stored in advance, or it is determined whether or not it is an erasure code by a predetermined logical operation. If the input code is an erasure code, the selector 10 is switched to the determination circuit 9 side as described above.

The operation of the above circuit will be explained.

When an analog signal AS as shown in FIG. 2(a) is input, the analog signal AS is converted into an analog/digital (A/D) signal by an A/D converter 4 according to a clock signal CLK having a period indicated by the scale on the horizontal axis. The changed and converted digital signal is input to the determination circuit 5.

In the example of FIG. 2(a), since the second digit is large, the 1st and 3.4th digits are small, and the 5th digit is the largest, the determination circuit 5 latches the clock signal CL at each cycle. or the values of the digits cascaded through the latch are M 1, 2, 3, 4 . s, 6, 7. a, 9, 1
0.11 digits ■ ■ ■ ■ ■ ■ ■ ■
■ ■ ■. In other words, since the 0th stage determination circuit 6, which stores the maximum value digit, does not receive the fifth digit signal, it stores the second digit, which is the second highest value. Therefore, the period is 1, 2, 3, 4, 5, 6, 7, 8, 9, 1
0.11 digits ■ ■ ... Old...
...Old, old, old, old...Old, song... ■Similarly, the 3rd degree 4.5th digit [phase] ■■ is stored in the judgment circuits 7, 8 and 9, respectively. be done. Accordingly, the judgment circuit 5,
6, 7.8 output the following 11-bit codes to the OR circuit 11, respectively.

Judgment circuit 5 00001000000 Judgment circuit 6 01000000000 Judgment circuit 7 00000000010 Judgment circuit 8 00000001000 Therefore, the output of the OR circuit 11 becomes 01001001010. Since this is not an erasure code, the output of the erasure code determination circuit 12 indicates normal, and the selector 10 continues to select the determination circuit 8. Therefore, if the output of the OR circuit 11 is taken in at an appropriate timing, a correct 4/11 code can be obtained. When the sub-synchronization signal SSS is input, the determination circuits 5, 6, . . . 9, and 12 are reset, and become ready to input the analog signal corresponding to the next 11 digits.

FIG. 3 is a block diagram showing the configuration of the "l" digit determination circuits 6...9.

Input data IN is input to the selector 22 and comparator 23. In addition, the latched contents of the latch circuit 24 are also Q.
It is input to the selector 22 and comparator 23 from the terminal. The comparator 23 compares the two inputs, and if input data IN>Q, the input signal IN is transferred to the latch circuit 2.
4, the output Q of the latch circuit 24 is outputted as output data OUT, and conversely, when IN≦Q, the input signal IN is outputted as output data 0LIT,
Further, in order to switch the selector 22 so as to apply the output Q of the latch circuit 24 to the input terminal of the latch circuit 24, a high level signal is applied to the selector 22 in the former case, and a low level signal is applied to the latter case.

These high and low signals serve as one input of the AND circuit 251, and also serve as low active inputs of the AND circuit 252, and the extraction inputs of both the AND circuits 251 and 252 are the clock signal CLK. The output of the AND circuit 251 is given as a clock for the latch circuit 24,
It is also applied to the low active reset terminal R of the counter 26 via an inverter. − direction AND circuit 252
The output is given to the counter 26 as a counting target. The contents of the counter 26 are latched into the latch circuit 27 by the sub synchronization signal SSS. The contents of the latch circuit 27 are converted into an 11-bit signal as described above using data 28 and output to the OR circuit 11. The other sub-synchronization signal SSS is applied to the terminal R of the latch circuit 24 as a reset signal.

Next, the operation of this circuit will first be explained for the determination circuit 5 in Figure 2 (a).
) signal AS will be explained as an example.

When the first digit input signal is input, latch circuit 2
Since the content of 4 has been reset and is O, IN>Q in the comparator 23, the comparator 23 outputs a high level signal, and the signal is sent to the latch circuit 24 via the selector 22.
The signal of the first digit inputted to is latched. Further, the counter 26 is reset by the output of the AND game 1-251.

Next, when the second digit signal is input, since IN>Q, it is latched into the latch circuit 24 in the same manner as described above. Similarly, counter 26 is reset again. On the other hand, the signal of the first digit that was latched earlier is output as O.
It becomes UT.

Next, in the input signal of the third digit, since IN≦Q, the comparator output becomes low level, and the signal of the third digit becomes the output 011T as it is.

On the other hand, since the latch circuit 24 does not have the clock signal CLK output from the AND gate 251, the latch circuit 24 retains the contents of the second digit as is. - direction, NO
Since the gate 252 outputs the clock signal CLK, the counter 26 is incremented by +1.

Similarly, when the fourth digit is input, the counter 26 becomes 2.
becomes. When the 5th digit signal is input, IN>Q
(-second digit), this input signal is latched and the counter 26 is reset. Since the fifth digit is the maximum, the contents of the latch circuit 24 do not change thereafter, while the counter 26 counts up to 6 by inputting the sixth to eleventh digits.

If the content of the counter 26 is m, the decoder 28
1-m) Outputs an 11-bit code where each digit is 1, in this case 00001000000.

Next, since the fifth digit is not inputted to the judgment circuit 6, such as 0■■■■■■■..., the content of the latch circuit 24 becomes the second largest second digit signal, and the counter 26 is counted up to 9. Therefore, the decoder 28 outputs 01oooooooooo. In this way, the digits stored in the latch circuit 24 by the decoder 27 are 1. It is an 11-bit code with the others being 0. Judgment circuits 7, 8. and 9 latch circuits 24 store the signals of the 10.8th and 9th digits, and the contents 1 of the counter 26
0 is 1,3°2 respectively. Therefore, from the OR circuit 11, the output of the decoder 28 of the judgment circuit 5, 6° 7.8 is 0100.
1001010 is output.

FIG. 4 shows the configuration of the erasure code determination circuit.

In the figure, 30 is a program logic array (P
LA) and the OR circuit 11 output (Ml+ = (M(1, Ml, Mz+ M39M4.
Ms.

M, ・Mri・Ms・M9・MIo)5 are inputted, performs the following logical operation, and outputs a high level signal Y as a result.

Y=MG　xMI　xMz　XM3 +Mt XM, xMI XM4 +Mt xM, xM4XM% +Ma　XMA　XMS　XMI.

+Ma XMs XM6 XM? + Ms X Mh X Mt X Ma+Mi, XM
? XMI XM9 +M, xM, xM, xM,.

+M6 XMI XMz +M*　XM　I.

Items 1 to 8 on the right side are the 9th term in (1) of the erasure code regulations.
Paragraph 1 corresponds to (2) of the same, and Paragraph 10 corresponds to (3) of the same.

This signal Y and sub synchronization signal SSS are transmitted to the NAN port circuit 32.
is input. Therefore, when the output of the OR circuit 11 is an erasure code, the output of the NAND circuit 32 becomes a low level in synchronization with the sub-synchronization signal SSS.
1 is reset. The set output Q of the flip-flop 31 becomes low only during this reset, switching the selector 10 to the determination circuit 9 side.

According to the circuit of the present invention, as shown in FIG. 2, etc., even though the second digit is 0, it is moved to 1 among the first and third digits and becomes a high level, and is larger than the first O digit. OR circuit 11 output is 111000010
It becomes 00. However, since this 4/11 code is an erasure code, the selector IO is switched to the determination circuit 9 side, and the output becomes correct as 10100001010.

FIG. 5 is a block diagram of the second circuit of the present invention, which is similar to the first circuit in that even if the fourth and fifth digits are exchanged, if it is still an erasure code, the third digit The fifth place was exchanged with the fifth place. Therefore, in this example, the third
, 4° Judgment circuit 7° that latches the signal of the 5th digit 8.
The configuration is such that the output of the decoder 28 of 9 is applied to the OR circuit 11 via the selector 10. The erasure sign determination circuit 12 selects the outputs of the determination circuits 7 and 8 during normal operation.
When the erasure is determined once, the outputs of determination circuits 7 and 9 are selected, and when the erasure is determined for the second time, the outputs of determination circuits 8 and 9 are selected based on the output of the OR circuit 11.

The analog signal shown in FIG. 2(C) is an example in which the magnitudes of the second and eighth digits are reversed from those in FIG. 2(b), and the first, second, and third digits are ORed.
The signal is output from the circuit 11 and determined to be an erasure. Next, the 4th and 5th digits are exchanged and the 1st 2.3.10th digit is output, but this is also determined to be an eraser. Next, the 3rd and 5th digits are exchanged, and the 1.3rd, 8.10th digits, 10100001010, are output and determined correctly.

FIG. 6 shows an example of the erasure sign determination circuit 12 in this case, and shows the PLA 30 output Y and clock signal C similar to FIG.
A counter 33 is provided to count the output of an AND gate 34 having two inputs, LK and LK. This counter is reset by the sub-synchronization signal SSS, and when the output Q is O, the selector 10 controls the judgment circuits 7 and 8, when it is 1, the judgment circuits 7 and 9, and when it is 2, the selector 10 controls the judgment circuits 7 and 9. The selector 10 is configured to select.

It goes without saying that the present invention is applicable not only to the 4/11 code but also to the /n code in general.

〔Effect of the invention〕

In the case of the present invention as described above, it is possible to accurately judge binary data and even decode it without depending on level fluctuations of analog signals, and when using this for reproduction of magneto-optical disks, etc., a disk drive with high reliability is required. We are providing it.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of the first circuit of the present invention, Fig. 2 is a waveform diagram for explaining the operation, Fig. 3 is a block diagram of the digit judgment circuit, and Fig. 4 is a block diagram of the erasure sign judgment circuit. FIG. 5 is a block diagram of the second circuit of the present invention, and FIG.
The figure is a block diagram of the erasure code determination circuit, and FIG. 7 is a drawing showing the 4/11 code. 4...A/D converter 5,6...9..."I I
I digit determination circuit 1, 2...Erasure code determination circuit 10...Selector 11...OR circuit Note that in the drawings, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) A circuit for determining an original n-bit code from an analog signal having information on a string of n-bit codes in which k bits out of n bits are significant and (n-k) bits are insignificant, the circuit comprising: An analog/digital converter that samples and converts analog/digital values at a predetermined period, latches the maximum value among sequentially input values, outputs values other than the maximum value, and converts the input values into analog/digital values. (k+1) significant digit determination circuits for specifying the input order of the maximum value, the (k+1) significant digit determination circuits are cascade-connected, and the sample value output of the analog/digital converter is based on this continuation. means for generating an n-bit code in relation to the input order specified by the significant digit determination circuits in the first to k stages of the cascaded circuit for n consecutive sample values input to the first stage of the circuit; , means for determining whether or not the n-bit code is a predetermined erasure code, and means for determining whether or not the n-bit code is a predetermined erasure code;
1) A binary data determination circuit comprising: means for generating an n-bit code in relation to the input order specified by the significant digit determination circuit of the stage and (k+1)th stage. (2) A circuit for determining an original n-bit code from an analog signal having information on a string of n-bit codes in which k bits out of n bits are significant and (n-k) bits are insignificant, the analog signal comprising: An analog/digital converter that samples and converts analog/digital values at a predetermined period, latches the maximum value among sequentially input values, outputs values other than the maximum value, and converts the input values into analog/digital values. (k+1) significant digit determination circuits for specifying the input order of the maximum value, the (k+1) significant digit determination circuits are connected in cascade, and the sample value output of the analog/digital converter is based on this continuation. means for generating an n-bit code in relation to an input order that is input to the first stage of the circuit and that is specified by the significant digit determination circuits of the first to k stages of the continuation circuit for n consecutive sample values; , means for determining whether or not the n-bit code is a predetermined erasure code; and means for determining whether or not the n-bit code is a predetermined erasure code;
1) means for generating an n-bit code in relation to the input order specified by the significant digit determination circuit of the stage and (k+1)th stage; and whether or not the n-bit code is a predetermined erasure code. means for determining the first stage of the cascade circuit ~(k−
2) a means for generating an n-bit code in relation to the input order specified by the stage and the significant digit determination circuits of the kth stage and the (k+1)th stage; circuit.