JPH02298195A - Color component signal converter - Google Patents

Abstract

PURPOSE:To prevent generation of a time difference in an interchannel signal by providing a matrix circuit switching a coefficient in response to the kind of a component signal, 1st and 2nd thinning filters decreasing the data density of 2nd and 3rd matrix outputs, to an encoder side and arranging an inverse matrix circuit setting the coefficient in response to the kind of the component signal to be outputted to a decoder side. CONSTITUTION:In the case of an inputted 1st component signal, the signal is entirely clamped at a black level and in the case of a 2nd component signal, a luminance signal is clamped to a black level and a chroma signal is clamped at an achromatic level. Each clamp output is inputted to AD conversion circuit groups 8, 9, 10 applying AD conversion in 48.6MHz and digitized. Each AD conversion output is inputted to a matrix circuit 11. The chroma data of a reproducing signal is inputted respectively to 1st and 2nd interpolation filters 35, 36, where the data density is interpolated thrice. On the other hand, the luminance data is inputted to a 2nd video delay circuit 34 and the luminance data is retarded in matching with the processing time of the 1st and 2nd interpolation filters 35, 36.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Field of Industrial Application The present invention relates to a color component signal conversion device for changing the arrangement of component video signals and transmitting the same.

(b) Prior Art FIG. 3 shows a circuit block diagram of a conventional video tape recorder which inputs component signals of a high-definition signal and performs recording and reproduction. This video tape recorder uses two types of component signals as input signals, the first component signal is composed of three primary color signals of RGB, and the second
The component signals are a Y signal and two types of chroma signals (P
R) (P,) (see Figure 3). However, PR=
(RY)/1.576, PR(B-Y)/1.82
It is 6. The recorded video signal consists of two channels and is a signal obtained by time-division compression multiplexing a line-sequential chroma signal and a Y signal at a predetermined compression ratio. Therefore, during recording, the first component signal must be converted into a second component signal, and the second component signal must be digitally processed for time division multiplexing. Furthermore, during reproduction, the time division multiplexing must be removed by digital processing and the second component signal must be converted into the first component signal if necessary.

In FIG. 3, the first component signal and the second component signal are input to the same input terminal, but the first switch group (51), (52), and (53) that are switched by the input format switching signal are When a component signal is input, the signal is input to the matrix circuit (50). This matrix circuit (50) has 3 analog
Converting the primary color signal to a second component signal. The second switch group (54), (55), and (56) are selected by the formant switching signal to select the input low-pass filter group (1).
(2) Input to (3).

The 10th bus filter (1) of the first channel has its cutoff frequency set to 20 MHz in order to select the Y component, and the 2nd and 30th bus filters (2) ( In 3), the cutoff frequency is set to 7 MHz to select the chroma component. Each low-pass output is input to the next-stage clamp circuit group (4), (5), and (6). The first clamp circuit (4) of the first channel clamps the black level, and the second and third clamp circuits of the second and third channels clamp the black level.
Clamp circuits (5) and (6) clamp the achromatic portion to suppress fluctuations in the DC level. Each clamp output is
The first AD conversion circuit (8) has a frequency of 48.6 MHz, and the second and third AD conversion circuits (9) (10) have a frequency of 16.2 MHz.
``r-AD conversion is performed. The AD conversion data is converted in the recording system video signal processing circuit (16).

As a result of the conversion, the recorded video signal is converted into a two-channel signal. The signals of each channel are arranged by time-division multiplexing a horizontal synchronization signal, a burst signal, a chroma signal in line order, and a luminance signal at a predetermined ratio in units of two horizontal synchronization periods, as shown in FIG. The signals are converted into analog signals in the first and second DA conversion circuits (18) and (19), and then converted into FM signals in the subsequent FM modulation circuits (20) and (21).
Modulated. Each modulation output is connected to a rotating video head (22) (
23) and recorded on the magnetic tape (24). Note that the recording system video signal processing circuit (16
) is derived from the recording timing signal generation circuit (17) in synchronization with the synchronization signal inputted to the synchronization input terminal together with the component signal.

On the other hand, the reproducing circuit demodulates the outputs reproduced by the rotating video heads (22) and (23) in the first and second FM demodulation circuits (27) and (28), respectively, and outputs the outputs to the fourth and fifth A of the next stage.
The data is digitized in D conversion circuits (30) and (31). The AD conversion output is input to a reproduction video signal processing circuit (33), where it is synchronized and converted into luminance data and two-channel chroma data. Each conversion data is D
A conversion circuit group (40), (41), and (42) respectively input the luminance data, and the third DA conversion circuit (41) converts the luminance data into 4
At 8.6MHz, the fourth and fifth DA conversion circuits (42)
(43) converts the chroma data into analog data at 16.2 MHz. The analogized luminance signal and chroma signal are input to the blanking addition circuit group (43), (44), and (45), and the first blanking addition circuit (43) sets the blanking level to the black level, and the second, The third blanking addition circuits (44) and (45) each define the blanking level to be an achromatic color level and add a synchronization signal. Output each additional signal Low-pass filter group (47) (4
8) Enter (49) and enter No. 40 - Bath fill (47)
A luminance signal with a cutoff frequency of 20MHz,
Further, chroma signals of 7 MHz or less are derived from the fifth and 60th bus filters (48) and (49), respectively. These low-pass filter outputs are output to the third switch group (57) (58) (59) when selecting the second component signal.
However, when selecting the first component signal, it is input to the inverse matrix circuit (60), converted into R-G-B three primary color signals, and then sent to the third switch group (57). )(5B) (59).

In addition, this third switch group (57) (58) (59) is
Switching is controlled by an output format switching signal. Further, the playback circuit inputs the FM demodulation output to a sync separation circuit (29) to perform sync separation, and based on this sync separation output, the playback timing signal generation circuit (32) outputs the FM demodulation output to the playback video processing circuit (33). A timing signal for data writing is supplied to. In addition, the playback timing signal generation circuit (
32) supplies a readout timing signal to the playback video signal processing circuit (33) in synchronization with an external synchronization signal input to the synchronization input terminal, and the synchronization signal generation circuit (39) supplies the readout timing signal to the playback video signal processing circuit (33). A synchronization signal whose phase matches the input component signal is formed and derived.

(c) Problems to be Solved by the Invention In the prior art described above, in order to perform matrix processing or inverse matrix processing only on the first component signal, the second component signal is A delay of 10 ηsec occurred. Therefore,
In order to eliminate this time difference, it is necessary to delay the second component signal at the digital processing stage or analog processing stage, but the delay time in digital processing is gradual and it is difficult to completely compensate for the delay. . Therefore, conventionally, the first to third delay circuits (Dl) to (D3) and the fifth to seventh delay circuits (D5
) to (Dl) were provided.

Further, the 10th-pass filter and the second and 30th-pass filters not only have different bandpass characteristics but also different delay characteristics. Therefore, a delay time difference occurs between the chroma signal and the luminance signal, and in order to eliminate this time difference, the fourth delay circuit (D4) and the eighth delay circuit (D4) delay the luminance signal.
8) was established.

Therefore, it is necessary to configure the circuit so that the above-mentioned delay time difference does not occur.

(d) Means for Solving the Problems Therefore, the present invention provides a group of low-pass filters that input recording component signals with common bandpass characteristics, and a clamping potential of the low-pass filter output that changes depending on the type of component signal. A clamp circuit group, an AD conversion circuit group that samples each clamp output at the same frequency, a matrix circuit that inputs the AD conversion output and switches coefficients according to the type of component signal, and data of the second and third matrix outputs. The invention is characterized in that first and second thinning filters for reducing the density are disposed on the encoder side, and a thinning filter for multiplying the data density of the chroma data in the component data obtained by the reproduction processing to match the luminance data. 1. A second interpolation filter, a delay circuit for delaying the luminance detector in the component data equally to the first and second interpolation filters, and a type of component signal to be inputted with the interpolated data and the delayed data and outputted. The present invention is characterized in that an inverse matrix circuit that sets coefficients according to the decoder side is disposed on the decoder side.

(E) Function Therefore, according to the present invention, during recording, the low-pass filter group has a common characteristic, the matrix circuit and the inverse matrix circuit exhibit a constant amount of delay regardless of the type of component signal, and the chroma data is processed. Since the delay time of the decimation filter or interpolation filter and the delay time of the delay circuit that inputs the luminance data match, there is no time difference between signals between channels.

(F) Embodiment Hereinafter, an embodiment will be described in which the present invention is applied to a high-quality video tape recorder.

In this embodiment, the first component signal and the second component signal are selectively inputted and recorded in a high-quality video tape recorder of the type that records the second component signal in two channels. The component signal and the second component signal are selectively derived.

First, input component signals are passed through a group of low-pass filters (1) and (2) each having a passband of 20 MHz.
)(3). Therefore, although no delay time difference occurs between the signals of each channel, the chroma signal in the second component signal is derived while containing unnecessary high-frequency components. Each low-pass output is a group of clamp circuits (4) (5)
(6) is input. A clamp level setting circuit (7) that inputs an input format switching signal controls each clamp circuit (4), (5), and (6) to switch the clamp voltage according to the type of component signal. Therefore, the first
In the case of component signals, all are clamped at the black level, and in the case of the second component signal, the luminance signal is clamped at the black level and the chroma signal is clamped at the achromatic color level.

Each clamp output is AD at 48 and 6 MHz, respectively.
The signals are input to the AD conversion circuit group (8), (9), and (1,0) for conversion and are digitized.

Each AD conversion output is input to a matrix circuit (11). This matrix circuit (11) has a configuration as shown in Fig. 2, and in order to input (X 3. Coefficient setting circuits (cl) to (C9) are provided to form a filtering circuit, and the coefficients are set in a relationship that applies to the first component signal and a relationship that applies to the second component signal, respectively. is set. This setting switching is performed by issuing a coefficient setting signal from a matrix coefficient switching circuit (12) which inputs an input format switching signal.

Therefore, the matrix circuit requires the same processing time for any component signal, and there is no difference in delay time depending on the type of component signal. The derived matrix output corresponds to the second component signal, but the data density of the chroma data is tripled.

Therefore, the first and second thinning filters (14) and (15) to which the chroma output is input cut out the high-frequency components using built-in digital low-pass filters, and then thin out the data so that the data density becomes 173. On the other hand, the luminance data is
The data input to the video delay circuit (13) is delayed by a time equal to the processing time of the first and second thinning filters (14) and (15) described above. Note that the first video delay circuit (1
3) can be omitted by delaying the writing within the recording system video signal processing circuit (16).

The data thinned out and the data delayed by the above-described processing are input to a recording system video signal processing circuit, and two-channel recording is performed as in the prior art described above.

On the other hand, in the reproduction circuit of this embodiment, reproduction processing is performed in the same procedure as in the prior art up to the reproduction system video signal processing circuit (33). From this reproduction video signal processing circuit (33), 4
Luminance data at 8.6 MHz and chroma data at 16.2 MHz are derived. In order to digitally perform inverse matrix processing on this chroma data, the data density must be tripled to match the data density of each channel. Therefore, the chroma data is input to the first and second interpolation filters (35) and (36), respectively, and the data density is 3.
interpolated twice. On the other hand, the luminance data is transferred to the second video delay circuit (
34) and the first and second interpolation filters (35) (
The luminance data is delayed according to the processing time of step 36).

Note that the second video delay circuit (34) can also be omitted for the same reason as the first video delay circuit (13). The interpolated data and delayed data are input to an inverse matrix circuit (37).

This inverse matrix circuit (37) has the same circuit connections as the matrix circuit shown in FIG. 2, and only the set count values of the coefficient setting circuits (C1) to (C9) are different.
The coefficients are switched in accordance with the type of component signal to be output. This switching control is performed based on a coefficient setting signal issued from an inverse matrix coefficient determining circuit (38) which inputs an output format switching signal. The data derived from the inverse matrix circuit (37) is derived at a frequency of 48.6 MHz, and the data is
The signals are input to a group of conversion circuits (40), (41), and (42) and converted into analog signals. The analogized three-channel component signals are sent to the blanking addition circuit group (43) (4
4) Input in (45).

This blanking addition circuit group (43) (44) (45)
inputs a blanking signal from a blanking level setting circuit (46) which inputs an output format switching signal, and adds the blanking signal to the input component signal. The resulting additional output is led out to each output terminal via a group of low-pass filters (47) (4, 8) (49) with a cutoff frequency of 20 MHz.

Components in FIG. 1 that are the same as those in FIG. 3 are given the same reference numerals, and redundant explanation of circuit operations will be omitted.

Further, in this embodiment, the converted signal was magnetically recorded and reproduced, but the parts after the recording system video signal processing circuit (16) were replaced with optical modulation means, and the parts up to the reproduction system video signal processing circuit (33) were replaced with optical demodulation means. Therefore, it is also possible to apply the present invention to optical transmission means, and the present invention also includes such a configuration.

Furthermore, in this embodiment, three primary color signals, luminance, P, P,
Although the present invention is also applicable to component signals such as a combination of a Y signal and a color difference signal, the present invention also includes such a configuration.

Furthermore, the sampling frequency of this embodiment is 48°6MH.
z can also be changed as necessary, and if the sampling frequency is increased, the first video delay circuit (13) also needs to be replaced with a thinning filter. Furthermore, when increasing the sampling frequency, there is an advantage that inexpensive low-pass filters can be used as the preceding stage low-pass filter group.

(g) As a result of the effects of the invention, according to the present invention, delay compensation according to the type of component signal or delay compensation between channels is no longer necessary.
The effect is great.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram according to an embodiment of the present invention, and FIG.
The figure shows a block diagram of the main circuit, FIG. 3 shows a block diagram of the conventional circuit, and FIG. 4 shows signal waveforms of the main part. (1) (2) (3)...Low pass filter group, (8)
(9) (10)... AD conversion circuit group, (11)...
Matrix circuit, (13)...first video delay circuit, (
14) (15)...first and second thinning filters, (3
4)...Second video delay circuit, (37)...Inverse matrix circuit, (3s) (36)...First and second interpolation filters, (40) (41) (42)... DA conversion circuit group. Figure 2

Claims (2)

[Claims] (1) A group of low-pass filters (1) (2) (3) that input a first component signal consisting of three primary color signals or a second component signal consisting of a luminance signal and two types of color signals and share a common cutoff frequency. ), AD conversion circuit groups (8), (9), and (10) that digitize the outputs of the low-pass filter groups (1), (2), and (3) using the same clock to form and derive AD conversion data; a matrix circuit (11) that inputs the conversion output and switches matrix coefficients according to the type of component signal to form and derive luminance data and color difference data corresponding to the second component signal; and a matrix circuit (11) that limits high frequency components of the color difference data. A color component signal conversion device comprising at least first and second thinning filters (14) and (15) for sparsing data density. (2) First and second interpolation filters (35) and (36) that input reproduced color difference data and perform data interpolation so that the data density matches the reproduced luminance data; and input the reproduced luminance data and the amount of delay thereof. The first and second interpolation filters (35
) (36) video delay circuit (3)
4) inputting the outputs of the first and second interpolation filters (35) and (36) and the video delay circuit (34) and forming component data by switching matrix coefficients according to the type of component signal to be derived; Inverse matrix circuit (37)
and a DA conversion circuit group (40), (41), and (42) that convert the output of the inverse matrix circuit into analog at the same frequency.