JPH02298177A - Agc circuit - Google Patents

Abstract

PURPOSE:To keep a level of an output signal constant even when a composite video signal with different modulation is inputted by detecting a level of a positive component of a vertical synchronizing pulse and a level of a negative component and holding a result being the sum of the absolute value of the level of each component for a vertical sweep period. CONSTITUTION:A reference extraction pulse (3) and a delay extraction pulse (4)are applied to a vertical synchronizing extraction circuit 7 as gate signals to extract a signal for vertical synchronizing pulse period from a composite video signal outputted from a buffer amplifier 2. A positive level detection circuit 8 detects a level part VH for 0V or over in the inputted signal and transfers the result to a level hold amplifier 10 and a negative level detection circuit 9 detects a level VL of 0V or below of the inputted signal and transfers the result to a level hold amplifier 11. The value holding by the level hold amplifiers 10, 11 is subject to absolute value addition at an adder circuit 12 and held by a hold amplifier 13 for one vertical sweep period only and compared and adjusted with a reference value Vr at a comparator 14 to adjust the gain of the gain adjustment amplifier 15.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an AG that compensates a composite video signal obtained by video detection from level fluctuations due to differences in modulation degree.
Regarding C circuit.

[Conventional technology]

Television signals are transmitted to each television receiver via a transmitting satellite, terrestrial antenna, cable, or the like, and for the purpose of transmission, carrier waves are modulated according to various methods.

[Problem to be solved by the invention]

However, the degree of modulation at this time (for example, in AM modulation, the ratio of the amplitude of the modulated signal to the amplitude of the carrier wave) may differ depending on the channel or satellite, and in such cases, the composite video signal obtained by detection may be The different levels cause various problems in later processing.

SUMMARY OF THE INVENTION An object of the present invention is to provide an AGC circuit that can maintain the level of its output signal constant even when composite video signals having different degrees of modulation are input.

[Means for Solving the Problems] To this end, the present invention provides a first detection means for detecting the level of a positive polarity component of a vertical synchronization pulse in a composite video signal output from a video detection circuit; a second detection means for detecting the level of the negative polarity component; an addition means for adding the absolute values of the levels of each component detected by the first and second detection means; The present invention is configured to include a hold means for holding the sweep period, a comparison means for comparing the signal from the hold means with a reference value, and a level control means for controlling the level of the composite video signal based on the output of the comparison means. .

〔Example〕

Examples of the present invention will be described below. FIG. 1 is a diagram showing a circuit of one embodiment. Reference numeral 1 designates an input terminal for inputting a composite video signal (a signal including a video signal and a synchronization signal) output from the video detection circuit, and 2 designates a buffer amplifier with high input impedance and low output impedance.

3 is a synchronization separation circuit that separates and extracts the synchronization signal ■ from the composite video signal, and 4 is a vertical synchronization signal ■ from the synchronization separated signal ■.
5 is a reference sampling pulse generation circuit that generates a reference sampling pulse signal ■ for the vertical synchronization period; 6 is a reference sampling pulse generation circuit that generates a reference sampling pulse signal ■ output from the reference sampling pulse generation circuit 5 with a pulse width at least equal to or larger than the pulse width. (For example v!
A? This is a delayed sampling pulse generation circuit that generates a delayed sampling pulse (2) delayed by 1.5 to 2.0 μs from the falling edge of the signal.

7 is a vertical synchronization sampling diagram for extracting a vertical synchronization pulse signal from a composite video signal using the above-mentioned reference sampling pulse signal ■ and delayed sampling pulse signal ■ as gate signals, and 8 is a reference sampling diagram in the vertical synchronization sampling circuit 7. A positive polarity level detection circuit 9 detects the level of the positive polarity signal component V from the signal ■ extracted by the pulse signal ■. 9 is a negative polarity signal component ■ from the signal ■ extracted by the delayed sampling pulse signal ■ in the same circuit 7. This is a negative polarity level detection circuit that detects the level of .

Further, 10.11 is a level hold amplifier that holds the detection signal V from the positive polarity level detection circuit 8 and the negative polarity level detection circuit 9 and the level of vL for at least the vertical synchronization pulse period, and 12 is both level hold amplifier 10. 1
13 is a hold amplifier that holds the level of the signal output from adder circuit 12 for a 1V period (vertical sweep period); 14 is a reference voltage value Vr and the output from hold amplifier 13; a comparator for comparing signal levels, 15 a gain adjustment amplifier whose gain is adjusted according to the comparison result signal, 16 this gain adjustment amplifier 1;
This is an output terminal that sends the output signal from 5 to the video amplification circuit.

Now, from the synchronization separation circuit 3, the synchronization signal ■ shown in FIG.
is output, and the vertical synchronization signal generation circuit 4 outputs this synchronization signal ■
A vertical synchronization signal (2) is generated based on this. This vertical synchronizing signal (2) is then applied as a gate pulse to the reference sampling pulse generation circuit 5, where the reference sampling pulse (2) is obtained. Further, this reference sampling pulse (2) is delayed in the delayed sampling pulse generating circuit 6 to obtain a delayed sampling pulse (2).

The reference sampling pulse (2) and the delayed sampling pulse (2) are applied as gate signals to the vertical synchronization sampling circuit 7 to extract the signal during the vertical synchronization pulse period from the composite video signal output from the buffer amplifier 2. As a result, the reference sampling pulse ■ is obtained by extracting the vertical synchronizing pulse itself and outputting it to the positive polarity level detection circuit 8.
The delayed sampling pulse (3) extracts the level portion where no pulse exists and transfers it to the negative polarity level detection circuit 9.

Then, the positive polarity level detection circuit 8 detects the level portion V8 of the input signal that is higher than Ov and transfers it to the level hold amplifier 10, and the negative polarity level detection circuit 9 detects the level portion VL of the input signal that is lower than Ov. It is detected and transferred to the level hold amplifier 11.

As shown in FIG. 2, the reference sampling pulse ■ and the delayed sampling pulse ■ are generated in the same number in one vertical pulse period. The level detection at .9 is performed for multiple pulses during this period, and the level hold amplifier 10
．． 11, the total value (that is, the average value) is held at the level.

Then, the absolute values of the values held by the level hold amplifiers 10 and 11 are added by the adding circuit 12, and the level from the bottom to the peak of the vertical synchronizing pulse is obtained here. This level indicates the average value of the plurality of vertical synchronization pulses. This signal is held by the hold amplifier 13 for one vertical sweep period, compared with the reference value Vr by the comparator 14, and then adjusted by the gain adjustment amplifier 13.
The gain of 5 will be adjusted.

As a result of the above, when the level of the input composite video signal is larger than the reference (corresponding to the reference voltage value Vr of the comparator 14), the gain adjustment amplifier 15 is controlled to decrease the gain, and when the level is smaller than the reference Therefore, regardless of the level of the composite video signal input to the input terminal 1, a composite video signal of a constant level is always obtained at the output terminal 16.

〔Effect of the invention〕

As described above, according to the present invention, even if the level of the input composite video signal differs due to the difference in the degree of modulation, the level can be controlled to a constant value, and there is an advantage that subsequent processing becomes easier.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of an AGC circuit according to an embodiment of the present invention, and FIG.
The figure is a timing chart for explaining the operation of the circuit.

Claims (4)

[Claims] (1) a first detection means for detecting the level of the positive polarity component of the vertical synchronization pulse in the composite video signal output from the video detection circuit; and a second detection means for detecting the level of the negative polarity component of the vertical synchronization pulse. a detection means, an addition means for adding the absolute values of the levels of each component detected by the first and second detection means, a hold means for holding the result of addition by the addition means for a vertical sweep period, and from the hold means. An AGC circuit comprising: comparing means for comparing the signal of the composite video signal with a reference value; and level controlling means for controlling the level of the composite video signal based on the output of the comparing means. (2), a reference sampling pulse generating means in which the first detection means generates a reference sampling pulse synchronized with the vertical synchronization pulse; and a first extraction means for extracting the vertical synchronization pulse using the reference sampling pulse; 2. The AGC circuit according to claim 1, further comprising positive polarity level detection means for detecting the level of the positive polarity component of the extracted vertical synchronization pulse. (3), the second detection means includes delayed sampling pulse generation means for generating a delayed sampling pulse that is delayed from the vertical synchronizing pulse by a pulse width of the pulse; 2. The AGC circuit according to claim 1, comprising: second extraction means for extracting the signal; and negative polarity level detection means for detecting the level of the negative polarity component of the extracted signal. (4) Detection by the first detection means and the second detection means is performed multiple times during the existence period of the vertical synchronization pulse, and the average value of each detection result is added by the addition means. An AGC circuit according to claim 1.