JPH02298107A - Voltage controlled oscillator - Google Patents

Voltage controlled oscillator

Info

Publication number
JPH02298107A
JPH02298107A JP11739089A JP11739089A JPH02298107A JP H02298107 A JPH02298107 A JP H02298107A JP 11739089 A JP11739089 A JP 11739089A JP 11739089 A JP11739089 A JP 11739089A JP H02298107 A JPH02298107 A JP H02298107A
Authority
JP
Japan
Prior art keywords
modulation
circuit
gate
capacitance
controlled oscillator
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11739089A
Other languages
Japanese (ja)
Inventor
Katsuki Obayashi
勝喜 大林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Original Assignee
Hitachi Denshi KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK filed Critical Hitachi Denshi KK
Priority to JP11739089A priority Critical patent/JPH02298107A/en
Publication of JPH02298107A publication Critical patent/JPH02298107A/en
Pending legal-status Critical Current

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  • Inductance-Capacitance Distribution Constants And Capacitance-Resistance Oscillators (AREA)

Abstract

PURPOSE:To evade the change of the modulation degree even when the oscillation frequency is changed by connecting a modulation input to a bias voltage supply line of a gate of a dual gate FET forming a negative resistance generating circuit. CONSTITUTION:A modulation circuit 3 consists of a DC cut capacitance 36 connecting to a DC bias resistor 16 of a gate of a dual gate FET 4 and a modulation terminal 35. Thus, as a modulation circuit, without using a varactor diode, the modulation input is connected to the gate 2 of the dual gate FET to control the oscillation frequency. Thus, since the capacitance of the oscillation circuit is not dependend on the capacitance change of a varactor diode 32, for modulation, the voltage controlled oscillator whose modulation degree is unchanged even when the capacitance of the varactor diode 26 is changed to vary the oscillation frequency.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は周波数シンセサイザに使用する電圧制御発振器
に関し、特に電圧可変素子として可変容量ダイオードを
用いた電圧制御発振器に関するものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a voltage controlled oscillator used in a frequency synthesizer, and particularly to a voltage controlled oscillator using a variable capacitance diode as a voltage variable element.

〔従来の技術〕[Conventional technology]

第2図に従来の電圧制御発振器の回路図を示す。 FIG. 2 shows a circuit diagram of a conventional voltage controlled oscillator.

この電圧制御発振器は第2図に示すように、負性抵抗発
生回路1と共振回路2と変調回路3とから構成されてい
る。このとき負性抵抗発生回路lはデュアルゲート電界
効果トランジスタ(以下FETと略称)4とソースイン
ダクタ5.ソース抵抗6、ドレイン・ソース間容量7.
ソース容量8゜ゲート1容量9.ゲート2容量io、 
 ゲート1の直流バイアス抵抗11.12.13.  
ゲート2の直流バイアス抵抗14.15.16.¥lL
源用チョークコイル17.を源接地容量18.共振回路
2への結合容量19.を原端子20.出力結合容[21
,出力端子22からなる。そして共振回路2は共振用コ
イル23.共振用容量24と一端が接地された可変容量
ダイオード26との結合容量25.寄生発振防止用抵抗
27.高周波阻止用インタツタ28゜接地容量29.可
変容量ダイオード26の直流バイアス端子30からなる
。変調回路3は共振回路2との結合容量31.可変容量
ダイオード32.抵抗33.接地容量34.変調久方端
子35がらなっている。ここで直流バイアス端子30の
バイアス電圧を変化させることにより、可変容量ダイオ
ード26の容量を変化させて電圧制御発振器の発振周波
数を変化することができる。
As shown in FIG. 2, this voltage controlled oscillator is composed of a negative resistance generating circuit 1, a resonant circuit 2, and a modulation circuit 3. At this time, the negative resistance generating circuit 1 includes a dual gate field effect transistor (hereinafter abbreviated as FET) 4 and a source inductor 5. Source resistance 6, drain-source capacitance 7.
Source capacitance 8° Gate 1 capacitance 9. gate 2 capacity io,
Gate 1 DC bias resistance 11.12.13.
Gate 2 DC bias resistance 14.15.16. ¥lL
Source choke coil 17. The source grounding capacity 18. Coupling capacitance to resonance circuit 2 19. The original terminal 20. Output coupling capacity [21
, and an output terminal 22. The resonant circuit 2 includes a resonant coil 23. Coupling capacitance 25 between the resonance capacitor 24 and the variable capacitance diode 26 whose one end is grounded. Parasitic oscillation prevention resistor 27. Interconnector for high frequency blocking 28° Grounding capacity 29. It consists of a DC bias terminal 30 of a variable capacitance diode 26. The modulation circuit 3 has a coupling capacitance 31 with the resonance circuit 2. Variable capacitance diode 32. Resistance 33. Ground capacity 34. The modulation terminal 35 consists of a modulation terminal 35. By changing the bias voltage of the DC bias terminal 30, the capacitance of the variable capacitance diode 26 can be changed and the oscillation frequency of the voltage controlled oscillator can be changed.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかし、前記従来のものには、変調入力レベルを一定と
したとき1発振周波数を変化させると。
However, in the conventional method, when the modulation input level is kept constant, the oscillation frequency is changed.

可変容量ダイオード26の容量が変化するため。This is because the capacitance of the variable capacitance diode 26 changes.

変調度も変化するという欠点がある。The disadvantage is that the degree of modulation also changes.

本発明はこの欠点を解決すべくなされたもので。The present invention was made to solve this drawback.

その目的は発振周波数を変化させても、変調度の変化し
ない電圧制御発振器を提供することにある。
The purpose is to provide a voltage controlled oscillator in which the degree of modulation does not change even if the oscillation frequency is changed.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は上記の目的を達成するため、電圧制御発振器に
おいて、負性抵抗発生回路を構成するデュアルゲー) 
FETのゲート2のバイアス電圧供給ラインに変調入力
を接続したものである。
In order to achieve the above object, the present invention provides a voltage controlled oscillator (a dual gate) that constitutes a negative resistance generation circuit.
A modulation input is connected to the bias voltage supply line of gate 2 of the FET.

〔作用〕 したがって9本発明においては、可変容量ダイオードの
容量が変化しても負性抵抗発生回路のデュアルゲートF
ETのゲート2には影響をおよぼさないので変調度が変
化しない電圧制御発振回路が実現できる。
[Operation] Therefore, in the present invention, even if the capacitance of the variable capacitance diode changes, the dual gate F of the negative resistance generating circuit
Since the gate 2 of the ET is not affected, it is possible to realize a voltage controlled oscillation circuit in which the degree of modulation does not change.

〔実施例〕〔Example〕

以下9本発明を図面に示す実施例に基づいて詳細に説明
する。第1図は本発明による電圧制御発振器の一実施例
を示す回路図である。同図において、1は負性抵抗発生
回路であって、デュアルゲートFET4とノースインダ
クタ5.ソース抵抗6、ドレイン・ソース間容量7.ソ
ース容量8゜ゲート1容量9.ゲート2容量10.ゲー
ト1の直流バイアス抵抗11.12.13.ゲート2の
直流バイアス抵抗14.15.16.電源用チョークコ
イル17.電源接地容量18.共振回路2への結合容量
19.電源端子20.出力結合容量21.出力端子22
からなる。そして共振回路2は共振用コイル23.共振
用容量24と一端が接地された可変容量ダイオード26
との結合容量25.寄生発振防止用抵抗27.高周波阻
止用インダクタ28.接地容量29.可変容量ダイオー
ド26の直流バイアス端子30からなる。変調回路3は
デュアルゲー)FET4のゲート2の直流バイアス抵抗
16に接地した直流カット用容量36と変調端子35か
もなる。すなわち本実施例が第2図の従来例のものと異
なる点は、変調回路として、可変容量ダイオードを使用
することなく、変調入力をデュアルゲートF E Tの
ゲート2に接続したことにある。
Hereinafter, nine embodiments of the present invention will be described in detail based on embodiments shown in the drawings. FIG. 1 is a circuit diagram showing an embodiment of a voltage controlled oscillator according to the present invention. In the figure, 1 is a negative resistance generating circuit, which includes a dual gate FET 4 and a north inductor 5. Source resistance 6, drain-source capacitance 7. Source capacitance 8° Gate 1 capacitance 9. Gate 2 capacity 10. Gate 1 DC bias resistance 11.12.13. Gate 2 DC bias resistance 14.15.16. Power supply choke coil 17. Power supply grounding capacity 18. Coupling capacitance to resonance circuit 2 19. Power terminal 20. Output coupling capacitance 21. Output terminal 22
Consisting of The resonant circuit 2 includes a resonant coil 23. A resonance capacitor 24 and a variable capacitance diode 26 whose one end is grounded.
Coupling capacity with 25. Parasitic oscillation prevention resistor 27. High frequency blocking inductor 28. Ground capacity 29. It consists of a DC bias terminal 30 of a variable capacitance diode 26. The modulation circuit 3 also includes a DC cut capacitor 36 grounded to the DC bias resistor 16 of the gate 2 of the dual gate FET 4 and a modulation terminal 35. That is, this embodiment differs from the conventional example shown in FIG. 2 in that the modulation input is connected to the gate 2 of the dual gate FET without using a variable capacitance diode as the modulation circuit.

なお図中同一符号は同一または相当部分を示している。Note that the same reference numerals in the figures indicate the same or equivalent parts.

このように前記実施例のものによると発振回路の容量を
可変容量ダイオード32の容量変化によって変調をかけ
るのではないので発振周波数を変化させるため、可変容
量ダイオード26の容量を変化させても、変調度が変化
しない電圧制御発振器が得られる。また、この実施例で
はゲート2に変調入力を接続しているが、ゲー)1に接
続しても同様の効果が得られる。
In this way, according to the embodiment described above, the capacitance of the oscillation circuit is not modulated by changing the capacitance of the variable capacitance diode 32, so the oscillation frequency is changed, so even if the capacitance of the variable capacitance diode 26 is changed, the modulation is not performed. A voltage controlled oscillator whose frequency does not change is obtained. Further, in this embodiment, the modulation input is connected to gate 2, but the same effect can be obtained even if it is connected to gate 1.

〔発明の効果〕〔Effect of the invention〕

以上説明したように9本発明によれはデュアルゲートF
ETのゲートに変調をかけることにより。
As explained above, according to the present invention, the dual gate F
By modulating the gate of ET.

発振周波数を変化させても変調度がほとんど変化しない
電圧制御発振器が実現できる。
It is possible to realize a voltage controlled oscillator in which the degree of modulation hardly changes even if the oscillation frequency is changed.

また、変調用に可変容量ダイオードを使用しないので2
回路が簡単になり安価にもなる。
Also, since no variable capacitance diode is used for modulation, 2
The circuit becomes simpler and cheaper.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す回路図、第2図は従来
の電圧制御発振器の一例を示す回路図である。 1:負性抵抗発生回路、2:共振回路、3:変調回路、
4 :FET、5,17,28:インダクタ。 6、11.12.13.14.15.16.27.33
 :抵抗。 7、8.9. 10.1.8.19.21.24.25
.29. :3L。 34、36 :容量、23:共振用コイル、26.32
:可変容量ダイオード、20:電源端子、22:出力端
子、30:直流バイアス端子、35:変調端子。。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an example of a conventional voltage controlled oscillator. 1: Negative resistance generation circuit, 2: Resonance circuit, 3: Modulation circuit,
4: FET, 5, 17, 28: Inductor. 6, 11.12.13.14.15.16.27.33
:resistance. 7, 8.9. 10.1.8.19.21.24.25
.. 29. :3L. 34, 36: Capacity, 23: Resonance coil, 26.32
: Variable capacitance diode, 20: Power supply terminal, 22: Output terminal, 30: DC bias terminal, 35: Modulation terminal. .

Claims (1)

【特許請求の範囲】[Claims] 1、デュアルゲートFETを用いた負性抵抗発生回路と
このデュアルゲートFETのゲートに結合された変調回
路と前記負性抵抗発生回路に結合された、共振周波数を
可変すべく挿入された可変容量ダイオードを含む共振回
路を具備し、前記可変容量ダイオードに供給される直流
電圧によって発振周波数を制御するようにしたことを特
徴とする電圧制御発振器。
1. A negative resistance generation circuit using a dual gate FET, a modulation circuit coupled to the gate of this dual gate FET, and a variable capacitance diode inserted to vary the resonance frequency, coupled to the negative resistance generation circuit. 1. A voltage controlled oscillator comprising: a resonant circuit including a resonant circuit, the oscillation frequency of which is controlled by a DC voltage supplied to the variable capacitance diode.
JP11739089A 1989-05-12 1989-05-12 Voltage controlled oscillator Pending JPH02298107A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11739089A JPH02298107A (en) 1989-05-12 1989-05-12 Voltage controlled oscillator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11739089A JPH02298107A (en) 1989-05-12 1989-05-12 Voltage controlled oscillator

Publications (1)

Publication Number Publication Date
JPH02298107A true JPH02298107A (en) 1990-12-10

Family

ID=14710468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11739089A Pending JPH02298107A (en) 1989-05-12 1989-05-12 Voltage controlled oscillator

Country Status (1)

Country Link
JP (1) JPH02298107A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6760575B2 (en) 1998-05-29 2004-07-06 Silicon Laboratories, Inc. Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications
US6965761B2 (en) 1998-05-29 2005-11-15 Silicon Laboratories, Inc. Controlled oscillator circuitry for synthesizing high-frequency signals and associated method
US6993307B2 (en) 1998-05-29 2006-01-31 Silicon Laboratories, Inc. Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6760575B2 (en) 1998-05-29 2004-07-06 Silicon Laboratories, Inc. Method and apparatus for generating a variable capacitance for synthesizing high-frequency signals for wireless communications
US6965761B2 (en) 1998-05-29 2005-11-15 Silicon Laboratories, Inc. Controlled oscillator circuitry for synthesizing high-frequency signals and associated method
US6993307B2 (en) 1998-05-29 2006-01-31 Silicon Laboratories, Inc. Method and apparatus for operating a PLL with a phase detector/sample hold circuit for synthesizing high-frequency signals for wireless communications

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