JPH02298069A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent breakdown of an element due to large electromagnetic field change while electric power is not supplied by using a means to short-circuit or to clamp two counter electrodes at a low voltage when electric power is not supplied to a semiconductor integrated circuit and to make them open when electric power is supplied. CONSTITUTION:A substrate potential of a semiconductor integrated circuit is approximately a grounding potential when electric power is not supplied; therefore, an NMOS transistor Tr1 (8) is conductive. Accordingly, charge of a capacitor 1 which develops due to electromagnetic field induction is short-circuited through the transistor 8, thereby holding potential of two counter electrodes 11, 12 the same and preventing breakdown of the capacitor 1. Meanwhile, when electric power is supplied to the semiconductor integrated circuit, a negative voltage is directly applied through an external power source, or a negative voltage which is developed by a substrate bias voltage development circuit which is formed on the semiconductor integrated circuit is applied to a substrate. At this time, the transistor 8 becomes conductive and the two counter electrodes 11, 12 of the capacitor 1 become open, thereby carrying out a normal circuit operation. Breakdown of the semiconductor integrated circuit under a circumstance of a large electromagnetic field change can be prevented in this way.

Description

[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for configuring a semiconductor integrated circuit, which is made to prevent damage to the semiconductor integrated circuit due to electromagnetic field induction.0 [Prior Art] Recent years As the miniaturization of semiconductor integrated circuits progresses, the phenomenon of destruction of semiconductor integrated circuits due to changes in strong electromagnetic fields has become more prominent and has become a problem. The mechanism of this destruction, which is particularly noticeable when stored in a large place, will be explained using a diagram. Figure 4 is a circuit diagram showing an N-channel UOS transistor and a delay capacitor, which are part of a semiconductor integrated circuit.Capacitor (1) in the figure is designed to have a relatively large capacitance value because it is intended for signal delay. Therefore, the layout area is large. If power is not being supplied to this semiconductor integrated circuit,
vo. Terminal (2) is 0 or N, which is at P1 ground potential.
MO8 transistor Trllf3) and Trl! ! (
Assume that the gate potential in 4) is also almost the ground potential, and in this state, a large electromagnetic field change occurs in the environment around the semiconductor integrated circuit. At this time, node 1 (5) has a large parasitic component (6) and O component, so it becomes a high voltage.

[Problem to be solved by the invention]

Since the conventional semiconductor integrated circuit is configured as described above, the transistor Tr11 and the transistor Tr12 are in a non-conducting state, so there is nowhere for the charge induced at the node 1 to escape, and the charge is eventually discharged to the capacitor/transistor. leading to destruction,
On the other hand, during operation, either transistor Tr11 or transistor Tr12 is conductive, so the induced charge escapes through this transistor and does not cause damage. The problem was that they were easily destroyed in environments with varying field strength.

This invention was made to solve the above-mentioned problems, and by providing a means for short-circuiting the opposing electrodes of a large capacitor when power is not supplied to a semiconductor integrated circuit, it can be used in an environment with large electromagnetic field changes. The purpose is to prevent destruction of semiconductor integrated circuits.

[Means to solve the problem]

The semiconductor integrated circuit according to the present invention includes first and second capacitors facing each other. A short-circuit means is provided between the second electrodes, and the short-circuit means is in a short-circuit state when power is not being supplied to the semiconductor integrated circuit;
The short circuit means is opened when power is being supplied.

[Effect]

The short-circuiting means in this invention short-circuits the opposing electrodes of the capacitor when power is not being supplied to the semiconductor integrated circuit to discharge accumulated wtN and charges, and when power is being supplied, the short-circuiting means is opened to normalize the semiconductor integrated circuit. enables the following actions.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. Reference numerals (1) to (4) in the drawings are the same as those of the prior art, so explanations thereof will be omitted. In the figure, the shorting means (7), which performs its function only when power is not supplied to the semiconductor integrated circuit, is connected to the opposing electrode α11 (2) of the capacitor (1).
) is constructed so that this shorting means (7) is opened during power supply.

FIG. 2 is a circuit diagram showing a specific embodiment of this shorting means (7). As shown, the shorting means (7) consists of a depletion type NMO81' transistor (8), the drain end of which is connected to one electrode of the capacitor (1).
Its source end is connected to the other electrode (6) of the capacitor (1). Also, the gate end has a substrate potential of 1'! IB
◇ Next, the operation will be explained.0 When the semiconductor integrated circuit is not supplied with power, the substrate potential is almost the ground potential, so the IJMOB transistor.

1 (8) becomes conductive 0 Therefore, at this time, the charge of the capacitor (1) generated by the electromagnetic field is short-circuited via the transistor (8), and the potentials of the two opposing electrodes 002 are kept the same. This can prevent damage to the capacitor (1). On the other hand, when power is being supplied to the semiconductor integrated circuit, a negative voltage is applied directly to the substrate from an external power supply, or a negative voltage generated by a substrate bias voltage generation circuit formed on the semiconductor integrated circuit is applied to the substrate. A voltage is applied to 0, so at this time the transistor (8) is in a non-conducting state, and the two opposing electrodes 0 (2) of the capacitor (1) are in an open state,
Note that in the above embodiment, a depressing type NIJO13 transistor (8) is used as the short circuit means (7), but a circuit as shown in FIG. Good too. In the figure, (9) is an N-channel OS transistor, α
O is a P-channel uos transistor.

As shown in the figure, the counter electrode α11 (a) of the capacitor (1)
An enhancement type N-channel vos transistor (9) and a P-channel 1ios transistor qO are connected between them, and their gate electrodes are connected to a ground wiring and a power supply wiring, respectively. At this time, it is assumed that a positive charge is induced on the electrode of the capacitor (1) due to a change in the electromagnetic field.

Now, when the semiconductor integrated circuit is in a non-powered state, the power supply wiring is almost equal to the ground potential, so the potential of electrode 0 is lowered by the P-channel MO8 transistor αG, which is equal to the potential of the P-channel oS transistor αO. Clamped at threshold voltage. On the other hand, when a negative charge is induced in the electrode (2), the N-channel type MOS transistor (9) becomes conductive, and the potential of the electrode (2) becomes -IN channel type -OS transistor (9) threshold value 1 (V ) is clamped.

As described above, in the embodiment shown in FIG.
Since the potential difference between the electrodes (111Q2 and 111Q2 is suppressed to the threshold of the -08 transistor, destruction of the capacitor can be prevented.On the other hand, when power is being supplied to the semiconductor integrated circuit, Since both are in a non-conductive state, the capacitor (1) can normally perform its role.

〔Effect of the invention〕

As described above, according to the present invention, two opposing electrodes forming a capacitor, which is a constituent device of a semiconductor integrated circuit, are short-circuited or clamped to a certain low voltage when power is not supplied to the semiconductor integrated circuit. In addition, by using a means to open the device when power is being supplied, it is possible to prevent the element from being destroyed due to large changes in the electromagnetic field when power is not being supplied, and a highly reliable semiconductor integrated circuit can be obtained. be.

[Brief explanation of drawings]

FIG. 1 is a conceptual diagram showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of the short-circuiting means of the present invention, and FIG. 3 is a schematic diagram showing another embodiment of the short-circuiting means of the present invention. FIG. 4 is a circuit diagram showing an embodiment of the present invention, and is a circuit diagram in which destruction of a capacitor occurs due to electromagnetic induction in a conventional semiconductor integrated circuit. In the figure, (1) is a capacitor, (2) is a terminal, and (3
)(4) is an N-channel MOS transistor, (7) is a short-circuiting means, (8) is an N-channel transistor, (9) is an N-channel-〇S transistor, and αO is a P-channel MOS transistor.
S transistor, 0 (2) indicates the electrode of the capacitor (1). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] The first and second opposing electrodes of a capacitor, which is a component of a semiconductor integrated circuit, are short-circuited or clamped at a constant low voltage when power is not being supplied to the semiconductor integrated circuit, and the power is not being supplied. 1. A semiconductor integrated circuit comprising means for being in an open state when the circuit is open.