JPH02298069A - Semiconductor integrated circuit - Google Patents
Semiconductor integrated circuitInfo
- Publication number
- JPH02298069A JPH02298069A JP1119212A JP11921289A JPH02298069A JP H02298069 A JPH02298069 A JP H02298069A JP 1119212 A JP1119212 A JP 1119212A JP 11921289 A JP11921289 A JP 11921289A JP H02298069 A JPH02298069 A JP H02298069A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor integrated
- integrated circuit
- supplied
- transistor
- capacitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 239000003990 capacitor Substances 0.000 claims abstract description 24
- 230000005672 electromagnetic field Effects 0.000 abstract description 10
- 239000000758 substrate Substances 0.000 abstract description 8
- 230000006698 induction Effects 0.000 abstract description 2
- 230000015556 catabolic process Effects 0.000 abstract 3
- 230000006378 damage Effects 0.000 description 9
- 238000010586 diagram Methods 0.000 description 9
- 230000000694 effects Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 1
- 230000000881 depressing effect Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は半導体集積回路の電磁界誘導による破壊を防
止するためになされた半導体集積回路の構成法に関する
ものである0
〔従来の技術〕
近年、半導体集積回路の微細化が進むに従って半導体集
積回路の強電磁界変化による破壊という現象が顕著にな
り問題となっている0この破壊は半導体集積回路に給電
されていない時、即ち、電磁界変化の大きい場所に保存
されているような場合に特に顕著となる0この破壊のメ
カニズムを図を用いて説明する。第4図は半導体集積回
路を構成する一部であるNチャンネルuosトランジス
タと遅延用キャパシタを示す回路図で、図のキャパシタ
(1)は信号遅延を目的としているため比較的大きな容
量値に設計されており、そのためレイアウト面積も大き
い。もし、この半導体集積回路に給電されていない時、
vo。端子(2)ははP1接地電位になっている0又N
MO8トランジスタTrllf3)及びTrl!! (
4)のゲート電位もほぼ接地電位になってい私、この状
態の時に、半導体集積回路の周りの環境に大きな電磁界
変化が生じたとする。この時、ノード1(5)は大きな
寄生り成分(6)やO成分を有しているため高い電圧に
なる。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to a method for configuring a semiconductor integrated circuit, which is made to prevent damage to the semiconductor integrated circuit due to electromagnetic field induction.0 [Prior Art] Recent years As the miniaturization of semiconductor integrated circuits progresses, the phenomenon of destruction of semiconductor integrated circuits due to changes in strong electromagnetic fields has become more prominent and has become a problem. The mechanism of this destruction, which is particularly noticeable when stored in a large place, will be explained using a diagram. Figure 4 is a circuit diagram showing an N-channel UOS transistor and a delay capacitor, which are part of a semiconductor integrated circuit.Capacitor (1) in the figure is designed to have a relatively large capacitance value because it is intended for signal delay. Therefore, the layout area is large. If power is not being supplied to this semiconductor integrated circuit,
vo. Terminal (2) is 0 or N, which is at P1 ground potential.
MO8 transistor Trllf3) and Trl! ! (
Assume that the gate potential in 4) is also almost the ground potential, and in this state, a large electromagnetic field change occurs in the environment around the semiconductor integrated circuit. At this time, node 1 (5) has a large parasitic component (6) and O component, so it becomes a high voltage.
従来の半導体集積回路は以上のように構成されていたの
で、トランジスタTr11及びトランジスタTr12は
非導通状態にあるためノード1に誘起さtた電荷は逃げ
るところがなく、遂にはキヤ/ぐシペ・の破壊に至り、
一方、動作時にはトランジスタTr11或はトランジス
タTr12のどちらかが導通しているために、誘起され
た電荷はこのトランジスタを介して逃げ破壊にはならな
い0このことが給電されていない半導体集積回路が大き
な電磁界強度変化のある環境下で破壊し易いという問題
点を有していた。Since the conventional semiconductor integrated circuit is configured as described above, the transistor Tr11 and the transistor Tr12 are in a non-conducting state, so there is nowhere for the charge induced at the node 1 to escape, and the charge is eventually discharged to the capacitor/transistor. leading to destruction,
On the other hand, during operation, either transistor Tr11 or transistor Tr12 is conductive, so the induced charge escapes through this transistor and does not cause damage. The problem was that they were easily destroyed in environments with varying field strength.
この発明は上記のような問題点を解決するためになされ
たもので、半導体集積回路の非給電時に大きなキャパシ
タの対向電極間を短絡する手段を設けることにより、電
磁界変化の大きい環境下での半導体集積回路の破壊を防
止することを目的とする。This invention was made to solve the above-mentioned problems, and by providing a means for short-circuiting the opposing electrodes of a large capacitor when power is not supplied to a semiconductor integrated circuit, it can be used in an environment with large electromagnetic field changes. The purpose is to prevent destruction of semiconductor integrated circuits.
この発明に係る半導体集積回路はキャパシタの相対向す
る第1.第2の電極間に短絡手段を設け、半導体集積回
路への給電されていない時は短絡手段を短絡状態とし、
給電されている時には短絡手段を開放するようにしたも
のである。The semiconductor integrated circuit according to the present invention includes first and second capacitors facing each other. A short-circuit means is provided between the second electrodes, and the short-circuit means is in a short-circuit state when power is not being supplied to the semiconductor integrated circuit;
The short circuit means is opened when power is being supplied.
この発明における短絡手段は半導体集積回路への給電さ
れていない時にはキャパシタの相対向する電極間を短絡
することによって蓄wtN、荷を放電させ、給電時には
短絡手段を開放することによって半導体集積回路の正常
な動作を可能にする。The short-circuiting means in this invention short-circuits the opposing electrodes of the capacitor when power is not being supplied to the semiconductor integrated circuit to discharge accumulated wtN and charges, and when power is being supplied, the short-circuiting means is opened to normalize the semiconductor integrated circuit. enables the following actions.
以下、この発明の一実施例を図について説明するO
第1図はこの発明における半導体集積回路の一実施例を
示す概念図である。図中符号(1)〜(4)は前記従来
のものと同一につき説明は省略する。図において、半導
体集積回路に給電しない時のみ、その機能を発揮する短
絡手段(7)をキャパシタ(1)の対向電極α11(2
)間に設けたものである0又、給電時にはこの短絡手段
(7)が開放になるように構成されている。An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a conceptual diagram showing an embodiment of a semiconductor integrated circuit according to the present invention. Reference numerals (1) to (4) in the drawings are the same as those of the prior art, so explanations thereof will be omitted. In the figure, the shorting means (7), which performs its function only when power is not supplied to the semiconductor integrated circuit, is connected to the opposing electrode α11 (2) of the capacitor (1).
) is constructed so that this shorting means (7) is opened during power supply.
第2図はこの短絡手段(7)の具体的実施例を示した回
路図である。図示のように、短絡手段(7)はデプレッ
ション型NMO81’ランジスタ(8)からなっており
、そのドレイン端はキャパシタ(1)の一方の電極叩、
そのソース端はキャパシタ(1)の他方の電極(6)に
接続されている。又、ゲート端は、基板電位1’!IB
に接続されている◇
次に動作について説明する0半導体集積回路が給電され
ていない状態では基板電位はほぼ接地電位になっており
、このためIJMOBトランジスタで。FIG. 2 is a circuit diagram showing a specific embodiment of this shorting means (7). As shown, the shorting means (7) consists of a depletion type NMO81' transistor (8), the drain end of which is connected to one electrode of the capacitor (1).
Its source end is connected to the other electrode (6) of the capacitor (1). Also, the gate end has a substrate potential of 1'! IB
◇ Next, the operation will be explained.0 When the semiconductor integrated circuit is not supplied with power, the substrate potential is almost the ground potential, so the IJMOB transistor.
1(8)は導通状態になる0従って、この時電磁界誘電
によシ生じるコンデンサ(1)の電荷は、トランジスタ
(8)を介して短絡され、2つの対向電極002の電位
は同一に保たれ、キャパシタ(1)の破壊が防止できる
。一方、半導体集積回路に給電されている状態では、基
板は外部電源により直接食の電圧が印加されたり、或は
半導体集積回路上に形成された基板バイアス電圧発生回
路によシ発生される負の電圧が印加される0従って、こ
の時トランジスタ(8)は非導通状態になり、キャパシ
タ(1)の2つの対向電極0(2)は開放状態になり、
正常な回路動作を行なうことができる0
なお、上記実施例では短絡手段(7)としてデプレツシ
目ン型のNIJO13トランジスタ(8)を用いた場合
を示したが、第3図に示すような回路としてもよい。図
において、(9)はNチャネル−OSトランジスタ、α
OはPチャネルuos トランジスタである。1 (8) becomes conductive 0 Therefore, at this time, the charge of the capacitor (1) generated by the electromagnetic field is short-circuited via the transistor (8), and the potentials of the two opposing electrodes 002 are kept the same. This can prevent damage to the capacitor (1). On the other hand, when power is being supplied to the semiconductor integrated circuit, a negative voltage is applied directly to the substrate from an external power supply, or a negative voltage generated by a substrate bias voltage generation circuit formed on the semiconductor integrated circuit is applied to the substrate. A voltage is applied to 0, so at this time the transistor (8) is in a non-conducting state, and the two opposing electrodes 0 (2) of the capacitor (1) are in an open state,
Note that in the above embodiment, a depressing type NIJO13 transistor (8) is used as the short circuit means (7), but a circuit as shown in FIG. Good too. In the figure, (9) is an N-channel OS transistor, α
O is a P-channel uos transistor.
図のように、キャパシタ(1)の対向電極α11(イ)
間にエンハンスメント型のNチャンネルvosトランジ
スタ(9)とPチャンネル1iosトランジスタqOを
接続し、そのゲート電極はそれぞれ接地配線及び電源配
線に接続されている。このとき、キャパシタ(1)の電
極但に電磁界変化により正の電荷が誘起されたとする。As shown in the figure, the counter electrode α11 (a) of the capacitor (1)
An enhancement type N-channel vos transistor (9) and a P-channel 1ios transistor qO are connected between them, and their gate electrodes are connected to a ground wiring and a power supply wiring, respectively. At this time, it is assumed that a positive charge is induced on the electrode of the capacitor (1) due to a change in the electromagnetic field.
今、半導体集積回路が無給電状態にあるとした時は、電
源配線は接地電位にほぼ等しくなっているので、Pチャ
ンネル型MO8トランジスタαGにより、電極0の電位
はPチャンネル鑓oSトランジスタαOのしきい値電圧
でクランプされる。一方、電極(2)に負の電荷が誘起
された時はNチャンネル型MOSトランジスタ(9)が
導通し、電極■の電位は−INチャンネル型−OSトラ
ンジスタ(9)のしきい値1(V)でクランプされる。Now, when the semiconductor integrated circuit is in a non-powered state, the power supply wiring is almost equal to the ground potential, so the potential of electrode 0 is lowered by the P-channel MO8 transistor αG, which is equal to the potential of the P-channel oS transistor αO. Clamped at threshold voltage. On the other hand, when a negative charge is induced in the electrode (2), the N-channel type MOS transistor (9) becomes conductive, and the potential of the electrode (2) becomes -IN channel type -OS transistor (9) threshold value 1 (V ) is clamped.
以上のように、第3図の実施例では、キャパシタ(1)
の電極(111Q2間の電位差は−08トランジスタの
しきい値に抑えられるため、キャパシタの破壊を防ぐこ
とができる。一方、半導体集積回路に給電されている場
合は、Pチャンネル及びNチャンネル型MOSトランジ
スタは、共に非導通状態となるのでキャパシタ(1)は
正常にその役割を果たすことができる。As described above, in the embodiment shown in FIG.
Since the potential difference between the electrodes (111Q2 and 111Q2 is suppressed to the threshold of the -08 transistor, destruction of the capacitor can be prevented.On the other hand, when power is being supplied to the semiconductor integrated circuit, Since both are in a non-conductive state, the capacitor (1) can normally perform its role.
以上のようにこの発明によれば、半導体集積回路の構成
デバイスであるキャパシタを形成スる2つの対向電極を
、半導体集積回路への給電がなされない時は、短絡或は
、ある低電圧にクランプし、かつ、給電時は開放にする
手段を用いたことによシ、非給電時の大きな電磁界変化
による素子の破壊を防止することができ、高信頼性の半
導体集積回路が得られる効果がある。As described above, according to the present invention, two opposing electrodes forming a capacitor, which is a constituent device of a semiconductor integrated circuit, are short-circuited or clamped to a certain low voltage when power is not supplied to the semiconductor integrated circuit. In addition, by using a means to open the device when power is being supplied, it is possible to prevent the element from being destroyed due to large changes in the electromagnetic field when power is not being supplied, and a highly reliable semiconductor integrated circuit can be obtained. be.
第1図はこの発明の半導体集積回路の一実施例を示す概
念図、第2図はこの発明の短絡手段の具体的実施例を示
す回路図、第3図はこの発明の短絡手段の他の実施例を
示す回路図、第4図は従来の半導体集積回路においてキ
ャパシタの電磁誘導による破壊を発生する回路図である
。
図において、(1)はキャパシタ、(2)は端子、(3
)(4)はNチャネルMOSトランジスタ、(7)は短
絡手段、(8) ハNチャネルトランジスタ、(9)は
Nチャネル−〇Sトランジスタ、αOはPチャネルMO
Sトランジスタ、0(2)はキャパシタ(1)の電極を
示す。
なお、図中、同一符号は同一、または相当部分を示す。FIG. 1 is a conceptual diagram showing an embodiment of the semiconductor integrated circuit of the present invention, FIG. 2 is a circuit diagram showing a specific embodiment of the short-circuiting means of the present invention, and FIG. 3 is a schematic diagram showing another embodiment of the short-circuiting means of the present invention. FIG. 4 is a circuit diagram showing an embodiment of the present invention, and is a circuit diagram in which destruction of a capacitor occurs due to electromagnetic induction in a conventional semiconductor integrated circuit. In the figure, (1) is a capacitor, (2) is a terminal, and (3
)(4) is an N-channel MOS transistor, (7) is a short-circuiting means, (8) is an N-channel transistor, (9) is an N-channel-〇S transistor, and αO is a P-channel MOS transistor.
S transistor, 0 (2) indicates the electrode of the capacitor (1). In addition, in the figures, the same reference numerals indicate the same or equivalent parts.
Claims (1)
び第2の対向電極間を、前記半導体集積回路への給電が
なされていない時は短絡、或は一定の低電圧でクランプ
し、かつ、給電がされている時は開放状態となる手段を
有することを特徴とする半導体集積回路。The first and second opposing electrodes of a capacitor, which is a component of a semiconductor integrated circuit, are short-circuited or clamped at a constant low voltage when power is not being supplied to the semiconductor integrated circuit, and the power is not being supplied. 1. A semiconductor integrated circuit comprising means for being in an open state when the circuit is open.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1119212A JPH02298069A (en) | 1989-05-12 | 1989-05-12 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1119212A JPH02298069A (en) | 1989-05-12 | 1989-05-12 | Semiconductor integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH02298069A true JPH02298069A (en) | 1990-12-10 |
Family
ID=14755717
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1119212A Pending JPH02298069A (en) | 1989-05-12 | 1989-05-12 | Semiconductor integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH02298069A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020171157A (en) * | 2019-04-04 | 2020-10-15 | 株式会社日立製作所 | Short circuit device of filter capacitor, short circuit/unit device, and short circuit method |
-
1989
- 1989-05-12 JP JP1119212A patent/JPH02298069A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020171157A (en) * | 2019-04-04 | 2020-10-15 | 株式会社日立製作所 | Short circuit device of filter capacitor, short circuit/unit device, and short circuit method |
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