JPH02296457A - Solid-state image pickup device - Google Patents

Abstract

PURPOSE:To read a picture at a faster speed than a conventional speed by reading the picture for a time corresponding to a 1/2 period of a clock signal having not been used for picture reading in a conventional system. CONSTITUTION:First switch means 31,33'... use, e.g. an L level pulse of a clock signal to sequentially make conductive between 1st photo transistors(TRs) 11, 13... and an output terminal 2a. Second switch means 32,34... use, e.g. an L level pulse of an inverted clock signal having an inverted phase of the said clock signal to sequentially make conductive between 2nd photo TRs 12, 14... and an output terminal 2b. Then a signal is sent respectively to the output terminal consecutively and alternately from the 1st and 2nd photo TRs. A signal synthesis section synthesizes signals sent from the 1st and 2nd photo TRs, then the quantity of information of the signals sent from the signal synthesis section is doubled more than that of a conventional system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a solid-state imaging device provided in a facsimile machine or the like.

[Prior Art] Solid-state imaging devices used in facsimile machines, etc.
As shown in the figure, in order to read an image, a plurality of phototransistors l-1, for example 64 phototransistors arranged in a row,
1-2,..., l-64 (representative phototransistor 1
) is connected to the output side of each phototransistor l, and the signal output terminal (
Switches 3-1, 3-2, . . . , 3-64 (representatively shown as switch 3) that control the sending of signals to 2 (denoted as StC in the figure) and synchronized with the supplied clock signal. 6. Sends a signal to turn on the switches 3 one after another.
It includes a 4-bit shift register 4 and a switch 6 that controls conduction and non-conduction between the output side of the switch 3 and a ground terminal (denoted as AGND in the figure) 7 in synchronization with the clock signal.

To explain the operation of the solid-state imaging device configured in this way, when a high (l) level signal is supplied to the star in (Sl) terminal 5, the noft register 4 outputs a low (L) level signal of the clock signal. In synchronization with the level, the 1-(level signal is sent out in the order of switches 3-1, 3-2, etc.) [Since the switch 3 supplied with the level signal is turned on, the phototransistor l The output side of the phototransistors l-1, 1-2, . . . is output to the signal output terminal 2 in this order.

However, when the clock signal is at I (level), the switch 6 is turned on and the signal output terminal 2 is connected to the ground terminal (AGN
D) becomes conductive with 7. Therefore, when the clock signal is at H level, the signal level at the signal output terminal 2 is forcibly pulled down to the ground level. Therefore, the clock signal supplied to the shift register 4 and the signal output terminal 2
The relationship with the signal level appearing in is as shown in Figure 6.
The relationship is such that the output signals sent out from the phototransistors 11.1-2, . . . appear in response to the high level of the τ knock signal, and are pulled down to the ground level in response to the H level of the clock signal.

[Problems to be Solved by the Invention] In the solid-state imaging device configured as described above, a half cycle of one cycle of the supplied clock signal is used for sending a signal from the phototransistor l;
The remaining half cycle is unrelated to the output signal of the phototransistor l and is wasted time.

Note that in order to read the output signal of the phototransistor i appearing at the signal output terminal 2, it is necessary for the output signal to rise to about 90% of the wave height, as shown in FIG. It takes time.

Therefore, the frequency of the clock signal for reading the signal sent out from the phototransistor I is necessarily about IMI.
lz is the limit.

For example, when scanning an image drawn on B4 size paper at the same magnification, the number of pixels in one line is 2048, and each line is 2.5 m.
If you read it at s, the frequency of the clock signal is 819
．． It becomes 2KHz. Therefore, there is a problem in that current solid-state imaging devices have limitations in increasing the number of phototransistors to obtain clearer images or in order to read images at higher speed.

The present invention has been made to solve these problems, and its first object is to provide a solid-state imaging device that can read images at higher speed.

[Means for Solving the Problems] The present invention provides 19 first branch and second phototransistors arranged alternately in one row, and a clock signal being supplied to the first branch and second phototransistors. 1- A first switch means that sequentially brings the transistor and the output terminal into a conductive state, and an inverted clock signal obtained by inverting the clock signal is supplied, so that the second The phototransistor is characterized by comprising: a second switch means that sequentially turns on the phototransistors; and a signal synthesis section that synthesizes the respective signals sent out by the first and second phototransistors.

[Function] By configuring as above, the first switch means:
For example, 1. 1 in sequence with level pulses
The phototransistor and the output terminal (are brought into conduction).

The second switch means sequentially brings the second phototransistor and the output terminal into conduction using, for example, an L-level pulse of an inverted clock signal having an inverted phase of the clock signal. Therefore, signals are alternately and continuously sent from the first and second phototransistors to their respective output terminals. Furthermore, the first and second phototransistors are arranged alternately in one row, and the signal combining section combines the signals sent out from the first and second phototransistors. The amount of information in the signal sent out is twice that of the conventional method.

[Embodiment] In FIG. 1 showing an embodiment of the solid-state imaging device of the present invention, four terminals 5 constitute a shift register 20, which is indicated as a start inlet (in pronation, S!) to which a signal of level I (level I) is supplied. The first stage [-1] is connected to the data input terminal 21a of the block circuit 21, and the clock signal terminal 8a is connected to the data input terminal 21a of the flip-flop circuit 21. The output side of the flip-flop circuit is connected to the data input terminals 23a, 25a, etc. of the next-stage flip-flop circuit. 11.13.15,・
... output side and odd number signal output terminal (SIG and 2 in the figure)
7) It is connected to the enable terminals 31a, 33a, . . . of active high transmission gates 31, 33, 35, . . .

On the other hand, the start-in (Sl) terminal 5 facing the shift register 404 and supplied with the II level signal is connected to the start-in (Sl) terminal 5 of the first-stage frisobuf [J-tub circuit 42] that constitutes the shift register 40, similarly to the shift register 20. An inverted clock signal terminal 8b connected to the data input terminal 42a and supplied with an inverted clock signal obtained by inverting the phase of the clock signal is a clock signal input to each flip-flop circuit 42, 44, . . . forming the soft register 40. terminal 42
b144b. The output side of each flip-flop circuit is connected to the data input terminals 44a, 46a, etc. of the next-stage flip-flop circuit, and is also connected to the output side of the even-numbered phototransistors 12, It is connected to enable terminals 32a, 34a, . . . of active high transmission gates 32, 34, 36, .

The phi transistors 11, 12, 13, etc. are arranged in a line as in the conventional example.

The odd number signal output terminal 2a and the even number signal output terminal 2b are connected to a composite signal generation circuit 50 as shown in FIG.

The composite signal creation circuit 50 is a circuit that combines the signals supplied from the odd signal output terminal 2a and the even signal output terminal 2b into one signal, and
Similar circuits are connected to the and even number signal output terminals 2b, respectively.

The odd number signal output terminal 2a is connected to the positive terminal 51a of the operational amplifier 51. In addition, one end of the human power line of the positive side terminal 51a is connected to a capacitor 5 that is grounded.
2, and the clock signal is connected to an enable terminal 53.
The input side of an active high transmission gate 53 supplied to a is connected. Further, the output side of the transmission gate 53 is grounded. The negative side terminal 51b of the operational amplifier 51 is connected to the feedback line of the operational amplifier 51 through a resistor, and is grounded through a variable resistor 54.

The output side of the operational amplifier 5I is connected to the output terminal 56 via an active high transmission gate 55, in which the knock signal is supplied to the enable terminal 55a.

On the other hand, the circuits connected to the even-numbered signal output terminal 2b side -L
The enable terminal 57 of the transmission gate 1, 57 corresponding to the transmission gate 53 has the same configuration as the circuit connected to the odd signal output terminal 2a described above, and the same components are given the same reference numerals.
The difference is that a knock signal is supplied to the transmission gate 55, and a clock signal is supplied to the enable terminal 58a of the transmission gate 1-58.

With this configuration, when a signal is supplied from the phototransistors 11, 13, etc. to the odd-numbered signal output terminal 2a, that is, when the clock signal is at L level, the transmission gate 53 is in the off state, and the transmission Since the transmission gate 55 is in the on state since the enable terminal 55a of the gate 55 is supplied with a signal of level I, the odd signal Ill output terminal 2a and the composite signal output terminal 56 are connected. When the transmission gate 57 connected to the even number signal output terminal 2b side is turned on, the even number signal output terminal 2
Since the b side is grounded and the transmission gate 58 is turned off, the even signal output terminal 2b and the composite signal output terminal 56 are not connected. Therefore, only the optical signals sent from the odd-numbered]--to transistors are output to the composite signal ratio horn terminal 56.

Conversely, when an optical signal is supplied from an even-numbered phototransistor to the even-numbered signal output terminal 2b, the inverted clock signal is at L level, so the transmission gate 57
is off, and the clock signal is at H level, so the transmission gate 58 is on, and the even signal output terminal 2b and the composite signal output terminal 56 are connected. At this time, the transmission gate 53 connected to the odd signal output terminal 2a side is turned on, the odd signal output terminal 2b side is grounded, and the transmission gate 55 is turned off.
a and the composite signal output terminal 56 are in a disconnected state. Therefore, only the optical signals sent from the even-numbered phototransistors are output to the composite signal output terminal 56.

The operation of the solid-state imaging device of this embodiment configured as described above will be described below.

As shown in FIG. 3, when a 1-level clock signal is supplied to the clock signal terminal 8a from time L1 to t2, a flip-flop circuit 2I provided in the shift register 20 causes a transmission signal to be transmitted from time t2 to t2. An H level signal is sent to the gate 31, and the transmission gate 31 is turned on. Therefore, the phototransistor 11 sends out an optical signal from time L2 to L4, but from time t3 to time t14, the signal level on the output side of the phototransistor 2 is lowered by the circuit (not shown) as in the conventional solid-state imaging device described above. It will be lowered to ground level. Therefore, from phototransistor II, time t2
During the period from 1 to 13, an optical signal is sent to the odd-numbered signal output terminal 2a via the transmission gate 31.

From time tl to t2 when the optical signal is supplied to the odd-numbered signal output terminal 2a, the clock signal is at the L level, while the inverted clock signal is at [Level]. , from time t2 to 13
The optical signals sent out from the phototransistor II until then are sent out from the composite signal output terminal 56.

Next, when an H-level inverted clock signal is supplied to the inverted clock signal terminal 8b from time t2 to t3, the flip-flop circuit 42 provided in the shift register 40 outputs the signal to the transmission gate 3 from time L3 to t5.
A high level signal is sent to the transmission gate 2, and the transmission gate 32 is turned on. Therefore, an optical signal is sent from the phototransistor I2 to the even signal output terminal 2b via the transmission gate 32 from time t3 to time t4 according to the same operation as the phototransistor 11 described above.

Time t3 when the optical signal is supplied to the even signal output terminal 2b
Until t4, the clock signal is at the H level, while the inverted clock signal is at the L level.
Only the optical signal sent out from the composite signal output terminal 56 is sent out from the composite signal output terminal 56.

Also, from time t3 to L4, as described above, the odd number signal output terminal 2a and the composite signal output terminal 56 are not electrically connected, so even if a noise signal enters the odd number signal output terminal 2a, the signal is not connected to the odd number signal output terminal 2a. is not sent to the composite signal output terminal 56.

Since the clock signal and the inverted clock signal have opposite phases, the composite signal output terminal 56 outputs the optical signal transmitted from the third phototransistor from time t4 to 15, and from time t5 to L6, the optical signal is transmitted from the composite signal output terminal 56. The optical signal is sent out from the several phototransistors, and in the same way, every time the clock signal CK changes from 1 to 1, the optical signal is sent out from the odd-numbered phototransistor that has proceeded one step to the right. On the other hand, the inverted clock signal CK h<
When changing from H to I, an optical signal is read out from the even-numbered phototransistor that advances one step to the right, and the optical signal from the 67 phototransistor 15, 16, 17 is sent out from the composite signal output terminal 56. be done.

Therefore, the composite signal sent out from the composite signal output terminal 56 becomes a continuous signal without the signal state being lowered to the ground level, as shown in FIG. 3e.

In this way, if the solid-state imaging device of the present invention is used, it is possible to perform reading even when reading is not performed compared to conventional phototransistors. The speed at which one line of an image can be read can be doubled compared to other devices. Furthermore, if the time required to read one line is the same as that of a conventional solid-state imaging device, the number of phototransistors provided in one line can be doubled compared to the conventional one, improving image reading density. becomes possible.

The composite signal n1 sent from the composite signal output terminal 56 has a waveform in which the pulse rises without being completely lowered to the ground level, as described above, but when the next stage device outputs the composite signal from the composite signal output terminal 56. As shown in FIG. 4, 200 ns immediately before the change point of the clock signal or inverted clock signal is sufficient to capture the signal sent out, and the signal sent out from the composite signal output terminal 56 is as described above. Even if the waveform changes, there will be no problem in capturing the signal.

[Effects of the Invention] As described in detail above, according to the present invention, the clock signal corresponding to the 1/2 period of the clock signal, which has not been used conventionally for image reading, can be
By reading the image even during the downtime, it is possible to read the image faster than in the past.

[Brief explanation of the drawing]

1 and 2 are block diagrams showing an example of the configuration of the solid-state imaging device of the present invention, FIG. 3 is a time chart showing the operation of the solid-state imaging device of the invention, and FIG. 4 is a diagram showing signal capture. , FIG. 5 is a block diagram showing the configuration of a conventional solid-state imaging device, FIG. 6 is a time chart showing the operation of the conventional solid-state imaging device, and FIG. 7 is a diagram showing the waveform of a signal sent from a phototransistor. be. IO...Phototransistor, 20...Shift register, 30...Switch, 40
...Shift register, 50...Synthetic signal generation circuit. Patent applicant: Ricoh Co., Ltd. − Agent: Patent attorney Aoyama Hao! Name figure 74 t5 t6 figure 300~400ns

Claims (1)

[Claims] (1) A plurality of first and second pieces arranged alternately in one row
a phototransistor; a first switch means that sequentially brings the first phototransistor and the output terminal into conduction when supplied with a clock signal; and an inverted clock signal obtained by inverting the clock signal. a second switch means for sequentially bringing the second phototransistor and the output terminal into conduction; and a signal combining section for combining respective signals sent out by the first and second phototransistors. A solid-state imaging device characterized by: