JPH022955A - Ic testing apparatus - Google Patents

Abstract

PURPOSE:To simplify the constitution and to decrease the cost of production by commonly inputting high level voltages and low level voltages which are supplied to test-signal generating means and measuring-signal detecting means from D/A converters which are provided for the individual channels. CONSTITUTION:High level voltages VH1 to VHn and low level voltages VL1 to VLn which are generated in signal converting parts COV1 to COVn are imparted to drivers 21-1 to 21-n (test-signal generating means) for channels corresponding to the specified pins of an IC under test 28 as control voltages VIH1 to VIHn and VIL1 to VILn. The voltages are also imparted to comparators 22-1 to 22-n (measuring-signal detecting means) for the channel corresponding to the specified pins of the IC under test 28 as detecting voltages VOH1 to VOHn and VOL1 to VOLn. The test-signal generating means and the measuring-signal detecting means are not operated at the same time. D/A converters 11-1 to 11-n and 12-1 to 12-n which generates control voltages or the detecting voltages to be supplied to both means are provided one set for each channel.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an IC testing device, and in particular, it is possible to configure a circuit without causing any functional deterioration in level measurement tests for ICs such as analog/digital mixed ICs and linear ICs. Regarding the simplification of .

[Prior Art] An example of a conventional IC (integrated circuit, hereinafter the same) testing device is shown in FIG. 2, and is roughly divided into a tester body 50, a test head portion 20, and the like. The tester main body 50 controls and operates the entire device and processes various data, and performs digital/analog conversion (hereinafter referred to as D/A conversion) or analog/digital conversion (hereinafter referred to as A) of various signals for testing. It includes signal conversion units C0N1 to C0Nn, etc., which perform /D conversion). Transmission and reception of various signals between the control section 59 and each signal conversion section C0N1 to C0Nn is performed via the data bus DB.

The signal converters C0NL to C0Nn are provided for each channel depending on the number of tester pins. Each signal converter C0
N1 to C0Nn are D/A converters 51-1 to 51-n,
52-1 to 52-n, 53-1 to 53-n, 54-1 to
54-n and an A/D converter (not shown). D/A converters 51-1 to 51-n, 52-1 to 52
-n are analog high-level control voltages VIH1 to VIH1 based on digital test data given from the control unit 59.
This is a digital/analog converter that generates VIHn and low level control voltages VILI to VILn, respectively, and outputs them to the drivers 21-1 to 21-n. Also, D/A
Converters 531 to 53-n.

54-1 to 54-n are analog high level detection voltages VOHI to VOHn and low level detection voltages VOLI to
Generate VOLn respectively and comparator 22-1 = 22-n
This is a digital/analog converter that outputs signals.

Further, the signal converters C0NI to C0Nn also include an A/D converter that converts the analog detection signals C1 to Cn inputted from the test head unit 20 into digital signals. Also.

Pulse signals 81 to Sn are supplied from the control section 59 to the drivers 21-1 to 21-n of the test head section 20 via the signal conversion sections C0NI to C0Nn, respectively.

The test head unit 20 outputs test signals OPI to OPn to be applied to predetermined pins of the IC under test 28, and
Measurement signal KSI output from a predetermined pin of the IC28
~Input KSn. Input/output sections PEI to PEn, output switches OW1 to ○Wn, and input switches IWI to IWn
and pin selection switches SWI to SWn.

Input/output sections PEI to PEn are provided for each channel corresponding to the number of tester pins, and test signals OPI to OPn are provided for each channel corresponding to the number of tester pins.
Drivers 21-1 to 2l-rl that generate
Comparators 22-1 to detect the states and characteristics of SI to KSn
22-n, etc. Driver 21-1~2
1-n is the input pulse signal 81-Sn.
Control voltages VIHI to VIH each input in synchronization with T
'0 of pulse signals S1 to Sn, where n is a high level voltage.
'', test signals OPI to ○Pn are generated with the control voltages VILI to VILn as low level voltages, respectively. These test signals OPI to OPn are generated by output switches ○W1 to O.
The signals are output to predetermined pins P1 to Pn of the IC under test 28 via Wn and pin selection switches SWI to SWn, respectively.

The comparators 22-1 to 22-n have a high level detection voltage vO.
Based on H1 to voHn, the high level voltages of the measurement signals KSI to KSn inputted from the IC 28 under test via the pin selection switches SW1 to SWn and the input switches IWI to IWn are compared and detected, and the low level detection voltage VOL is
The low level voltages of the measurement signals KSI to KSn are compared and detected for I to VOLn, respectively. The analog detection signals C1 to Cn that are compared and detected here are sent to the signal converters C0N1 to C0N of the channels corresponding to each of the tester main body 50.
After the signal is output to N and subjected to analog/digital conversion, it is provided to the control unit 59, where various data processing is executed. In addition, in the input/output sections PEI to PEn of the same channel,
Test signals OPI to O by drivers 21-1 to 21-n
The operation of generating Pn and the operation of detecting the states and characteristics of the measurement signals KSI to KSn by the comparators 22-1 to 22-n are not executed simultaneously, and when one is in the operating state, the other is in the standby state. and if the other is in the operating state, one is in the standby state, or both are in the standby state.

Output switches OWL to OWn are drivers 21-1 to 21
-n outputs, and the other pin selection switches SWI to SWn and input switches IWI to IW.
They are respectively connected to the midpoints of n. The output switch OWL
~OWn is turned on corresponding to the channel drivers 21-1 to 21-n that are in an operating state generating test signals OPI to OPn. The test signals OPI to OPn output from the drivers 21-1 to 21-n are sent to predetermined pins P1 to OPn of the IC under test 28 corresponding to the channels via output switches OW1 to ○Wn and pin selection switches SWI to SWn. Give to Pn.

Input switches IWI to IWn are comparators 22-1 to 22-2.
One side is connected to the human power of 2-n, respectively, and the other side is the output switch OWL~OWn and the pin selection switch SWI~S.
It is connected to the midpoint of Wn.

The input switches IWI to IWn receive measurement signals KS1-K
It is turned on corresponding to the channel that inputs Sn to the comparators 22-1 to 22-n. At this time.

In the corresponding channel, the predetermined measurement signal KS1~
KSn is selected from predetermined pins P1 to Pn of the IC under test 28 to pin selection switches SWI to SWn and the input switch IWI.
~IWn to the inputs of the comparators 22-1 to 22-n, respectively.

One side of the pin selection switches SWI to SWn is connected to the midpoint between the output switches OW1 to OWn and the input switches IWI to IWn, and the other side is connected to the IC via the signal bus T.
It is connected to socket 29.

The pin selection switches SWI to SWn are connected to a predetermined driver 21-1 via output switches OWL to OWn.
~21-n output or input switches IW1~IW
This is a switch that selectively connects the inputs of predetermined comparators 22-1 to 22-n and predetermined pins P1 to Pn of the IC under test 28 mounted in the IC socket 29 via the pins P1 to Pn.

Test signal O output from drivers 21-1 to 2L-n
Switches of channels corresponding to predetermined pins P1 to Pn of the IC under test 28 to which PI to OPn are applied are turned on, and measurement signals KSI to KSn are applied to the IC under test 28.
from predetermined pins P1 to Pn of comparators 22-1 to 22-n.
The switch corresponding to the channel to be compared and detected is turned on.

Note that the test signals OPI to OPn or the measurement signals KSI to KSn are transmitted and received between the pin selection switches SW1 to SWn and the IC socket 29 via the signal bus T.

For example, assume that a predetermined waveform is applied to a pin of the IC 28 under test, a measurement signal is extracted from the pin 13 corresponding to the pin 2, and a digital level is measured for the IC 2B. In the control section 59.

The level and waveform characteristics of the test signal OP2 corresponding to the characteristics of the IC 28 and the detection level and timing for comparing and detecting the measurement signal KS13 are set.

Also, in order to apply the test signal OP2, the output switch O
While turning on P2 and pin selection switch SW2,
The input switch IWI3 and the pin selection switch 5W13 are set in advance to be turned on.

In the input/output section PE2, only the driver 21-2 is in an operating state and the comparator 22-2 is in a standby state.

D/A in synchronization with '1''' of input pulse signal S2
High level control voltage V given from converter 51-2
Test waveform OP in which IH2 is set to high level and low level control voltage VIL2 given from D/A converter 52-2 is set to low level in synchronization with 110'' of pulse signal S2.
Generates 2. The test waveform OP2 is the output switch OW2
and is applied to pin 2 of the IC under test 28 via pin selection switch SW2. The measurement signal KS13 output from pin 13 of the IC under test 28 is sent to the pin selection switch SW.
I3 and input/output section P via input switch IWI3
It is applied to comparator 22-13 of E13.

In this input/output section PE13, only the comparator 22-13 is in the operating state, the driver 21-13 is in the standby state, and the low level detection voltage V given from the D/A converter 54-13
The rise time from the low level of OL13 to the high level of the high level detection voltage VOH13 applied from the D/A converter 53-13 and from the high level of the high level detection voltage VOH13 to the low level detection voltage VO
The falling time until L13 reaches the low level is detected, and the slew rate (response characteristic) of the IC 28 under test is determined.

In addition, as a test for an IC, the difference in transit time of test waveforms between multiple pins may be measured. for example,
Driver 21 for pins 2 and 3 of IC under test 28
-2.21-3 to predetermined test signal OP2. OP3 is applied respectively, measurement signals KSI2 and KS13 are taken out from pins 12 and 13 corresponding to pin 2.3 and sent to the comparator 22-
12. Compare and detect the passage time by 22-13.

The control unit 59 determines the delay time difference between the measurement signal KS12 and the measurement signal KS13 between the pins 12 and 13 based on the data detected by the comparators 22-12 and 22-13. In this case, driver 21-2.
Comparator 22-2.22 of the channel corresponding to 21-3
-3 and D/A converter 53-2.53-3.54-2.5
4-3 is not used, similarly comparator 22-12.22-
Driver 21-12゜21 of the channel corresponding to 13
-13 and D/A converter 51-12.51-13.52-
12.52-13 is not used.

[Problem to be Solved by the Invention] In the above-mentioned test for an IC, the pin of the IC under test to which the test signal is applied is different from the pin of the IC from which the measurement signal to be compared and detected is taken out, and Each driver 21- in the input/output sections PEI to PEn
1 to 21-n and the respective comparators 22-1 to 22-n do not operate simultaneously. For example, in the input/output section PEI, when the driver 21-1 is operating in a state where the test signal OPI is applied to pin 1 of the IC under test 28, the comparator 22-1 is not used and is in a standby state. . Also, the comparator 22-1 outputs the measurement signal K from the 1st pin of the IC 28.
When the SI is input and comparison detection is being performed, the driver 21
-1 is in standby state.

Therefore, the signal converters C0NI to C0N of each channel
n, D corresponding to drivers 21-1 to 2 L-n
/A converters 51-1 to 51-n, 52-1 to 52-n and D/A converters 53 corresponding to comparators 22-1 to 22-n.
-1 to 53-n and 54-1 to 54-n, only one set of D/A converters is used, and the other set of D/A converters is not used and is in a standby state.

In recent years, there has been a tendency for ICs to become more highly integrated and have more pins, and in response to this, the number of tester pins in IC testing equipment has also increased, leading to higher functionality and more complexity. For example, when testing an IC with 128 pins, the signal converter C
D/A converters 51-1 to 51- to 0NI to C0N128
128.52-1 to 52-128 and D/A converter 53-
1~53-128. Total of 54-1~54-128 51
It is necessary to provide two D/A converters. In the same way,
When testing an IC with 512 pins, a total of 204
It requires as many as eight D/A converters.

Therefore, there have been problems in that the configuration of the IC testing device becomes complicated and large, and the manufacturing cost increases.

This invention was made in view of the above points, and by simplifying the circuit configuration while maintaining the conventional functions, it is possible to make the device configuration more compact and reduce the manufacturing cost. The purpose of this invention is to provide an IC wiping device that provides the following features.

[Means for Solving the Problems] An IC testing device according to the present invention includes, for each pin of an IC under test, first digital data indicating a high-level voltage of a test signal to be applied to the pin; second digital data indicating the low level voltage of the signal;
Third digital data indicating a reference high level voltage for comparing and detecting the measurement signal taken out from the pin, and fourth digital data indicating a reference low level voltage for comparing and detecting the δU constant signal. and are generated according to predetermined test programs, and
when the first and second digital data are generated corresponding to a predetermined first pin to which a test signal is applied;
The third and fourth digital data corresponding to the pins are not generated, but the predetermined second pin outputs the 81g constant signal in response to the test signal applied to the first pin. In the IC testing apparatus, the first and third digital data are commonly input, and the IC test apparatus includes a test control means for generating the third and fourth digital data in response to the input digital data. A high-level digital/analog conversion means that outputs an analog voltage according to the data, and a low-level digital/analog converter that receives the second and fourth digital data in common and outputs an analog voltage according to the input digital data. digital/analog conversion means, and the high level digital/analog conversion means;
a test signal generating means for generating the test signal based on a high level analog voltage generated in the analog converting means and a low level analog voltage generated in the low level digital/analog converting means; Using the high-level analog voltage generated in the analog conversion means and the low-level analog voltage generated in the low-level digital/analog conversion means as reference voltages, the IC under test is
a measurement signal detection means for detecting the measurement signal taken out from the test signal, and selectively outputting either the output of the test signal generation means or the input of the measurement signal detection means to the corresponding pin according to the control of the test control means. and switch means for connection.

[Operation] The test control means stores, for each pin of the IC under test, first digital data that indicates the high level voltage of the test signal to be applied to the pin, and second digital data that indicates the low level voltage of the test signal. Third digital data indicating a reference high level voltage for comparing and detecting the digital data and the measurement signal taken out from the pin, and fourth digital data indicating a reference low level voltage for comparing and detecting the measurement signal. digital data respectively according to a predetermined test program, and when the first and second digital data are generated corresponding to a predetermined first pin to which a test signal is applied, the first The third pin corresponding to
and fourth digital data is not generated, but third and fourth digital data are generated in response to a predetermined second pin that outputs a 311 constant signal in response to a test signal applied to said first pin. Generate digital data.

The switch means selectively connects either the output of the test signal generation means or the input of the measurement signal detection means to the corresponding pin according to the control of the test control means. In the high-level digital/analog conversion means corresponding to the first pin to which a predetermined test signal is applied, first and third digital data are commonly input, and an analog voltage corresponding to the input digital data is input. Output.

In the low level digital/analog conversion means of the channel corresponding to the predetermined pin that outputs the 81'J constant signal, the second and fourth digital data are inputted in common,
Outputs an analog voltage according to the input digital data. The test signal generating means generates a test signal based on the high level analog voltage generated in the high level digital/analog conversion means and the low level analog voltage generated in the low level digital/analog conversion means. In the measurement signal detection means.

A high-level analog voltage generated in the high-level digital/analog conversion means and a low-level analog voltage generated in the low-level digital/analog conversion means are used as reference voltages, and a measurement signal taken out from the IC under test is detected. In addition, if an example of the device configuration is shown assuming that the IC test equipment is composed of a tester body 10 and a test head section 20 as shown in FIG. 1, the test control means corresponds to the control section 19, and the high The level digital/analog conversion means is a D/A converter 11-
1 to 11-n, low level digital/analog conversion means to D/A converters 12-1 to 12-n, test signal generation means to drivers 21-1 to 21-n, and measurement signal detection means to comparison In the devices 22-1 to 22n, the switch means are switches SWI to SWn, OW1 to OWn.
, IW1 to IWn, respectively.

As described above, according to the IC testing device according to the present invention, the test signal generating means and the measuring signal detecting means of the channel corresponding to a predetermined pin do not operate simultaneously, and the test signal generating means or the measuring signal detecting means 1llllllllll When one of the Tadashin stages is in the operating state, the other is in the standby state,
Or, since both are in a standby state, the high-level digital/analog conversion means and the low-level digital/analog conversion means that generate the control voltage or detection voltage to be supplied to the test signal generation means or measurement signal detection means are One set may be provided for each channel. Therefore, by simplifying the digital/analog conversion means corresponding to each channel, it is possible to downsize the device configuration and expect a reduction in production costs.

[Example] Hereinafter, an example of an IC testing device according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an IC testing apparatus according to the present invention, which is roughly divided into a tester body 10 and a test head section 20. The tester main body 10 has a control section 19
and signal converters C0V1 to C0Vn, etc.,
The control unit 19 controls and operates the entire device and also performs various data processing. Various signals are sent and received between the control unit 19 and each of the signal conversion units C0v1 to C0Vn via the data bus DB.

The signal converters C0V1 to C0Vn have D/A converters 11-1 to 11 for each channel corresponding to the number of tester pins.
-n, 12-1 to 12-n, and an A/D converter (not shown). The D/A converters 11-1 to 11-n are digital/analog converters that generate analog high-level voltages VHI to VHn based on digital data provided from the control section 19. D/A converter 12-1
~12-n are analog low level voltages VL1~VLn based on digital data given from the control unit 19.
It is a digital/analog converter that generates High level voltages VHI to VHn and low level voltages VLI to VL generated in the signal converters C0V1 to C0Vn
n is the driver 21-1 to 21-n of the channel corresponding to the predetermined pin of the IC under test 28 to which the test signal is applied.
For control voltage VIHI ~ VIHn, VIL1 ~ VI
Detection voltages VOH1 to VO for the comparators 22-1 to 22-n of the channels corresponding to predetermined pins of the IC under test 28 from which measurement signals are to be taken out.
Hn, given as VOL 1 to VOL n.

The test head section 20 has a configuration that performs the same function as that explained in FIG.
The high level detection voltages vOH1 to ■oHn of ~22-n are connected in parallel to the high level voltages VHI to VHn that are the outputs of the D/A converters 11-1 to 11-n, and the drivers 21-1 to 21 − n control voltage V I L 1− V
I L n and the low level detection voltages VOL1 to VOLn of the comparators 22-1 to 22-n are connected to the D/A converter 12-1-.
Low level voltage VHI~VHn which is the output of 12-0
are connected in parallel.

Next, the operation of each part in the above configuration will be explained. For example, it is assumed that the test signal OPI is applied to pin 1 of the IC under test 28 and the measurement signal KS6 is extracted from pin 6 corresponding to pin 1 and detected.

Digital data instructing the high level voltage VIHI of the test signal OPI to be applied to the IC under test 28 is transmitted to the control unit 1.
9 to the D/A converter 11-1, and digital data indicating the low level voltage VILI of the test signal OPI is also provided to the D/A converter 12-1. Also, the measurement signal KS output from pin 6 of the IC under test 28
The reference high level detection voltage v for comparing and detecting 6
Digital data instructing OH6 is sent from the control unit 19 to D.
/A converter 11-6, and the measurement signal KS
Digital data indicating the low level voltage VOL6 of 6 is applied to the D/A converter 12-6.

D/A converter 11-1゜12-1 of signal converter covi
Then, based on the digital data given from the control section 19, an analog high level voltage H1 and a low level voltage VLI are generated, respectively.

The high level voltage VHI and low level voltage VL1 are
Driver 21 of input/output unit PEI corresponding to the channel
-1, it is output as a high level control voltage VIHI and a low level control voltage VILI.

In the driver 21-1 of the input/output section PEI, the signal conversion section C
A test signal OPI is output based on the high level control voltage VIHI and low level control voltage VILI given from 0Vl and the clock pulse Sl, and is applied to pin 1 of the IC under test 28 via the output switch ○W1 and pin selection switch SW1.

Note that in this case, the comparator 22-1 is in a standby state.

In addition, the D/A converter 11-6.1 of the signal converter C0V6
At step 2-6, analog high level voltage VH6 and low level voltage VL6 are generated based on the digital data given from control section 19, respectively. The high level voltage VH
6 and the low level voltage V L 6 are applied to the comparator 22-6 of the input/output unit PE6 corresponding to the channel, as the high level detection voltage VIH6 and the low level detection voltage VIL6.
is output as

In the comparator 22-6 of the input/output section PE6, the signal conversion section C0
Based on the high level detection voltage VIH6 and low level detection voltage VIL6 given from V6, the pin selection switch SW6 and input switch I are selected from pin 6 of the IC under test 28.
The Ml'l constant signal KS6 given via W6 is compared and detected. This detection signal C6 is converted into a digital signal by the signal converting section C0V6 and given to the control section 19, where various data processing is executed. Note that in this case, the driver 21-6 is in a standby state.

In this kind of IC test, the driver 21 for each channel is
-1 to 21-n and the comparators 22-1 to 22-n are not activated at the same time; only one of the drivers or comparators is activated, or both are in a standby state. Therefore, the drivers 21-1 to 12-n of each channel
The high level voltage and low level voltage applied to the comparators 22-1 to 22-n are supplied to the common D/A converters 11-1 to 11-1.
1-n and 12-1 to 12-n, the number of D/A converters is only two for each channel. For example, assuming that the number of tester pins is 128 pins, the D/A converters 11-1 to 11-128.12- constitute the signal conversion units C0VI to C0V128 corresponding to the human output units PEI to PE128 for each channel. 1-1
2-128 requires a total of 256 pieces.

In this embodiment, the number of channels corresponds to the number of tester pins, but the number of channels is not limited to this and may be any other appropriate number of channels. For example, pins P1 to IC28 under test
When the number of channels m is half of Pn, the IC under test
28 and the input/output sections PE1 to PEm, a matrix switch is provided between each of the arbitrary drivers 21-1 to 12-m or the comparators 22-1 to 22-m and the arbitrary one of the IC under test 28. The pins P1 to Pn may be selectively connected to each other.

[Effects of the Invention] As described above, according to the IC testing apparatus according to the present invention, the high level voltage and the low level voltage Y voltage to be supplied to the test signal generation means and measurement signal detection means provided for each channel, respectively, can be , the D/A converter that generates high-level voltage and the D/A converter that generates low-level voltage provided for each channel are commonly operated manually, which simplifies the device configuration. This has the excellent effect of reducing production costs.

2 is a block diagram illustrating an example of FIG.

10...Tester body, 19...Control unit, 20...
Test head section, C0V1 to C0Vn... Signal conversion section, 11-1 to 11-n, 12-1 to 12-n... Digital/analog converter, DB... Data bus, PE
l ~ P E n-person output section, 21-1 ~ 21-n
-... Driver, 22-1 to 22-n... Comparator,
OW1~OWn...output switch, IWI~IWn・
...Input switch, SWI~SWn...Pin selection switch, T...Signal bus, 28...IC under test,
29...IC socket.

Claims (1)

[Claims] Regarding each pin of the IC under test, first digital data indicating a high level voltage of a test signal to be applied to the pin, and second digital data indicating a low level voltage of the test signal. and a third voltage that indicates a reference high level voltage for comparing and detecting the measurement signal taken out from the pin.
and fourth digital data indicating a reference low level voltage for comparing and detecting the measurement signal, respectively, according to a predetermined test program; When data is generated corresponding to a predetermined first pin to which a test signal is applied, said third and fourth digital data corresponding to said first pin are not generated, but when said first pin IC testing comprising test control means for generating the third and fourth digital data in response to a predetermined second pin that outputs the measurement signal in response to the test signal applied to the IC tester. In the apparatus, the first and third digital data are commonly input, and high level digital/analog conversion means outputs an analog voltage according to the input digital data; and the second and fourth digital data. A low-level digital/analog converter that inputs data in common and outputs an analog voltage according to the input digital data, and a high-level analog voltage generated in the high-level digital/analog converter and the low level. test signal generation means for generating the test signal based on the low level analog voltage generated in the high level digital/analog conversion means; and the high level analog voltage generated in the high level digital/analog conversion means and the low level digital /measurement signal detection means for detecting the state of the measurement signal taken out from the IC under test using a low-level analog voltage generated in the analog conversion means as a reference voltage; and a corresponding pin according to the control of the test control means. 1. An IC testing device characterized in that a processing channel is provided for each pin, and a switch means for selectively connecting either the output of the test signal generating means or the input of the measurement signal detecting means to the IC tester.