JPH0229272B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a video signal processing circuit using a clamp circuit. In that case, this clamp circuit is
It consists of a clamp diode, a reference voltage that defines the clamp level, and a capacitor connected in series with the video signal source to clamp the synchronization pulse to a predetermined level.

As is known, a video signal consists of a chrominance signal, a luminance signal, a blanking signal and a synchronization signal. This composite signal is processed in many individual stages. The video signal is fed in particular to a stage which processes the synchronization signal and also generates the control signals necessary for horizontal and vertical deflection. This stage is provided within one integrated circuit. The integrated circuit is provided with a synchronization signal separation stage, as well as an oscillator stage and a phase comparator stage that generates a frequency and phase correct deflection frequency. Modern television sets can be connected to various video signal sources, such as tuners, video recorders, video cameras, etc. These video signal sources are connected to the subsequent signal processing stage via video switches. In this case, a problem arises in that the pulse-to-signal ratio, that is, the ratio of the synchronization pulse to the video signal, is not predetermined or constant because the connected video signal sources have different internal resistances. That is, integrated circuits for processing synchronization pulses require a constant pulse-to-signal ratio, which is not available. Even if the video signal is simply amplified before being fed to this stage, the pulse
The signal ratio is not improved and the sync pulse separation stage is therefore unable to process the sync pulses as desired.

British Patent No. 2,084,839 discloses a circuit using a sample circuit. However, such a circuit cannot be used if the synchronization pulses are taken out after a changeover switch for various video signal sources. Because the sample circuit is
This is because when the internal resistance values of various video signal sources are large and different from each other, it cannot be controlled.

Also, Federal Republic of Germany Patent Application Publication No. 2645534
The publication discloses a clamp circuit that sets a reference level by manually adjusting a variable resistor. However, even this clamp circuit cannot automatically match the different internal resistances of multiple video signal sources.

OBJECTS OF THE INVENTION It is an object of the invention to widen the above-mentioned reduced pulse-signal ratio, independent of the connected video signal source and its internal resistance, so that a synchronization pulse can be generated uniquely in the subsequent pulse processing stage. The goal is to make it possible to separate them.

According to the present invention, this problem is solved by the configuration described in the claims.

Next, the present invention will be briefly described. That is, the present invention is a circuit that processes a video signal using a clamp circuit, and a resistor that acts as a part of the operating resistance of a differential amplifier is inserted and connected to the clamp circuit. This resistance experiences an additional voltage drop during the duration of the synchronization pulse. This additional voltage drop then compensates for the reduction in the ratio of the sync pulse to the video signal (pulse-to-signal ratio) due to the internal resistance of the video signal source.

DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to embodiments with reference to the drawings.

FIG. 1 is a block circuit diagram of a known clamp circuit. This clamp circuit allows the synchronization pulse of the video signal applied to input side 1 to be applied to the reference voltage.
It is clamped to a value obtained by subtracting the voltage drop Vbe determined by the clamp diode 2 from Vref. The clamp level is formed by capacitor 3. A current I flows through the clamp diode 2 for a short time when the synchronization pulse is at its peak value. Video signal source 4
has an internal resistance 5 of value Ri, this internal resistance compresses the synchronization pulse, ie the clamping level is relatively high in the signal direction shown in FIG. This level shift is performed depending on the value Ri of the internal resistance 5. Since the internal resistance value Ri varies depending on the type of video signal source, the amount of displacement of the clamp level also varies accordingly. Therefore, the pulse-to-signal ratios for the subsequent integrated pulse separation stages will also be different. As mentioned above, this pulse-signal ratio is the ratio between the video signal and the synchronization pulse.

FIG. 2 shows how a video signal source such as a tuner 6, a video recorder 7, a video camera 8, etc.
1 is a block circuit diagram showing how the chroma signal stage 12 and the luminance signal stage 13 are connected. In addition
The SCART plug panel is designed to plug the video signal source described above.

Referring now to FIG. 3, a circuit according to the invention which eliminates the above-mentioned drawbacks will also be described. However, this circuit is provided for all the individual signal sources shown in FIG.

The illustrated video signal source 15 has an internal resistor 16 and is connected to a differential amplifier 18 via a coupling capacitor 17 in which the clamping level is determined. The clamp level is generated by a reference voltage Vref applied to the base of transistor 19. In other words, a clamp level Vref-Vbe is formed at the emitter of this transistor, which is conductive only while the negative synchronization pulse lasts, which is smaller than the reference voltage Vref by the base-emitter voltage Vbe. According to the invention, the collector of transistor 19 has a resistance value
It is connected to the positive voltage VCC through the resistor 20 of RM. Resistor 20 is part of the operating resistance of differential amplifier 18. The collector circuit of the transistor 21 of the differential amplifier 18 is provided with a resistor 22 having a value R2. The emitter circuit of this transistor has a value
A resistor 23 of R1 is provided. The resistor 23 has
The emitter resistor 24 (resistance value R1) of the second transistor 25 of the differential amplifier 18 is coupled.
The collector of transistor 25 is connected to voltage source VCC. The two resistors 23 and 24 are connected to a reference potential via a constant current source 26. A bias voltage of the value Vref-Vbe is applied to the base of the transistor 21.

The operation of this circuit will be explained with reference to the video signal waveform diagram in FIG.

At the emitter of transistor 19, a clamp level as shown in FIG. 4A is formed. As mentioned above, the synchronization pulse is compressed. In other words, the pulse-signal ratio becomes smaller. This is due to the internal resistance 16 of the signal source 15. The purpose of the circuit shown in Figure 3 is to restore this pulse-to-signal ratio, i.e. to compensate for the reduction in synchronization pulse amplitude without changing the signal, thus restoring the predetermined pulse-to-signal ratio. That's true. This is done as follows. That is, an additional current I flows through transistor 19 during the duration of the synchronization pulse, thereby causing an additional voltage drop across resistor R20 (see FIG. 4B). This additional voltage drop is superimposed on the output 27 of the differential amplifier 18, so that a video signal with a restored pulse-to-signal ratio appears at this output (see FIG. 4C).

The resistance value RM of the resistor 20 is selected in such a way that the synchronization pulse is compensated accurately depending on the internal resistance 16 of the signal source 15. In other words, RM=R2×Ri/
The resistance value is chosen such that R1. Also resistance value
If the RM is selected accordingly, it is possible to compensate for the synchronization pulse by more than the actual amount of compression, if necessary.

[Brief explanation of drawings]

FIG. 1 is a waveform diagram of a known clamp circuit and the video signal obtained by it, FIG. 2 is a block diagram showing the connection relationship between a television receiver and various video signal sources, and FIG. 3 is a diagram of a circuit according to the present invention. The block circuit diagram in FIG. 4 is a video signal waveform diagram for explaining the operation of the circuit shown in FIG. 3. 1...Input side, 2...Clamp diode,
3, 17... Capacitor, 4, 15... Video signal source, 5, 16... Internal resistance, 6... Tuner,
7...Video recorder, 8...Video camera, 9
... SCART plug panel, 10 ... Video switch, 11 ... Synchronization pulse stage, 12 ... Chroma signal stage or chromaticity signal stage, 13 ... Luminance signal stage, 1
4...TV receiver, 18...Differential amplifier, 1
9, 21, 25...transistor, 20, 22,
23, 24...Resistor, 26...Constant current source, 27...
...Output side, Vref...Reference voltage.

Claims (1)

[Claims] 1 A clamp circuit consisting of a clamp diode, a reference voltage for forming a clamp level, and a capacitor connected in series with the video signal source and for clamping the synchronization pulse to a predetermined level is provided, and in this case, internal resistances are varied. In a video signal processing circuit using a clamp circuit, in which a plurality of signal sources are connected to a luminance signal channel, a chroma signal channel or a chromaticity signal channel, and an amplitude separator via a changeover switch, the changeover switch 1
A differential amplifier 18 is installed in front of the plurality of input sides of 0, respectively.
A resistor 20 is inserted and connected to the differential amplifier as a part of the operating resistance, and the connection point between the resistor and another resistor 22 which is a part of the operating resistance of the differential amplifier 18 is connected to the collector electrode of the transistor 19. By connecting, during the duration of the synchronization pulse, a voltage drop occurs across the resistor 20 due to the additional current (I), and the emitter of the transistor 19 is connected to the base of the transistor 25 of the differential amplifier 18.
and a capacitor 17 in series with the video signal source, and the base of the transistor 19 is connected to the reference voltage Vref, so that during the duration of the synchronization pulse the collector-emitter section of the transistor 19 is connected to the resistor 20. A video signal processing circuit using a clamp circuit that generates a current.