JPH02291711A - Surface acoustic wave element - Google Patents

Surface acoustic wave element

Info

Publication number
JPH02291711A
JPH02291711A JP11267389A JP11267389A JPH02291711A JP H02291711 A JPH02291711 A JP H02291711A JP 11267389 A JP11267389 A JP 11267389A JP 11267389 A JP11267389 A JP 11267389A JP H02291711 A JPH02291711 A JP H02291711A
Authority
JP
Japan
Prior art keywords
single crystal
crystal substrate
silicon single
idts
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11267389A
Other languages
Japanese (ja)
Inventor
Kazuyoshi Sukai
須貝 和義
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Faurecia Clarion Electronics Co Ltd
Original Assignee
Clarion Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Clarion Co Ltd filed Critical Clarion Co Ltd
Priority to JP11267389A priority Critical patent/JPH02291711A/en
Publication of JPH02291711A publication Critical patent/JPH02291711A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To satisfactorily increase the feed-through suppression despite the large capacity of an IDT (transducer) by forming a 1st high density impurity dispersion area in an area held between the IDTs on the surface of a high resistance silicon single crystal substrate and also forming a 2nd high density density impurity dispersion area under each IDT. CONSTITUTION:A 1st high density impurity dispersion layer 8 is formed in an area held between the IDTs 4 on the surface of a high resistance single crystal substrate 7. At the same time, the 2nd high density impurity dispersion areas 6 and 6 are formed under the IDTs 4 respectively. In such a constitution, the effective resistance is increased between both IDTs and the impedance is equivalently increased between the IDTs. Then the field-through suppression is satisfactorily increased despite the large capacity of the IDT.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は,非圧電性基板上に圧電薄膜を形成した弾性表
面波素子の改良に関するものである.[発明の概要] 本発明は、上記弾性表面波素子において、素子特性に影
響を与える電磁波の直達波( feadthrough
・フィード・スルー)を抑圧するように構成したもので
ある. [従来の技術〕 従来、非圧電性基板上に圧電薄膜を形成した弾性表面波
(SAW)素子として、第4図および第5図に示すもの
がある. 第4図に示した弾性表面波素子は、低抵抗シリコン単結
晶基板1上にシリコン酸化膜2を形成し、さらにZnO
圧電薄膜3を形成したもので,4はZnO圧電薄膜3上
に設けられたSAWの送受信用金属電極である. 第5図に示した弾性表面波素子は、前記と同様な低抵抗
シリコン単結晶基板1とシリコン酸化膜2との間にエピ
タキシャルSi層5を設け,さらにIDT(}−ランス
デューサ)の励振効率を上げるために金属電極4下のエ
ピタキシャルSi層S内に高濃度不純物拡散領域6を設
けたものである.上記のようなZnO/Si構造のSA
W素子は様々なものが知られているが、とりわけ特に電
気機械結合係数の大きなセザワ波を用いる素子の構造は
第4図、第5図に示すものに帰着する.上記素子のSi
基板として低抵抗基板を用いるのは.SAWと半導体中
のキャリアとのA−E(acousto − elec
tric)  相互作用によるエネルギー損失を最小限
にするためで、第4図に示す構成は、主にSAWフィル
ターを実現する構造である.さらにA−E相互作用を積
極的に利用した機能素子、たとえばコンボルバなどを実
現するには、比較的に薄いエピタキシャルSi層5を設
けた第5図の構成が採用される. もちろん、上記構成に、目的とする機能を′与えるため
にゲート電極、pnダイード.FET、グレーティング
など種々の付加構造が設けられて,実際の素子が実現さ
れている. [発明が解決しようとする課M] しかしながら、上記素子構造で、IDTの対数が非常に
多くなったり,IDTの容量が大きくなった場合、電磁
波の直達波(フィード・スルーfeed throug
h)が素子特性に大きく影響する場合がある.このフィ
ード・スルーの原因は、(1)マッチング・コイルなど
で誘導的な結合が生ずる. (2)送受信トランスデューサの基板表面で生じる容量
結合, (3)送受信トランスデューサのバルク基板を通じて生
じる容量結合 などがある. 上記素子構造では、フィード・スルー抑圧のため,従来
は実効的な結合係数の向上もかねて平衡駆動が採用され
ている.トランスデューサの容量が小さい場合は、十分
な抑圧が達成されるが、容量が大きくなると平衡駆動だ
けでは十分な抑圧度は実現されない. 前記コイル間の結合を抑えるためにシールドしたり,あ
るいはIDT/IDT間にシールド電極を設けるなどの
手段は通常おこなわれているが,フィード・スルーの原
因(3)による容量結合の抑圧はむづかしい. つまり,第4図および第5図に示した素子構成は.ID
Tの容量が大きい場合,フィード・スルー抑圧がむづか
しいという欠点を有していると言える. [発明の目的] 本発明は,非圧電性基板上に形成された圧電薄膜を有す
る弾性表面波素子構造で、IDTの容量が大きくなって
も、フィード・スルーが十分に抑圧される基本構造を提
供することを目的としているものである. [課題を解決するための手段] 本第1の発明は,少なくとも高抵抗シリコン単結晶基板
と圧電薄膜とからなる積層体と,前記圧電薄膜上に所定
間隔をもって形成された1対のトランスデューサと、前
記高抵抗シリコン単結晶基板表面部における前記トラン
スデューサに挟まれた区域に形成された第1の高濃度不
純物拡散領域と,各トランスデューサ下の前記高抵抗シ
リコン単結晶基板表面部にそれぞれ形成された第2の高
濃度不純物拡散領域とを含む構成を要旨としているもの
である. さらに,本第2の発明は,少なくとも高抵抗シリコン単
結晶基板と,エピタキシャルSL層と圧電薄膜とからな
る積層体と、前記圧電薄膜上に所定間隔をもって形成さ
れた1対のトランスデューサと、前記高抵抗シリコン単
結晶基板表面部における前記トランスデューサに挾まれ
た区域に形成された第1の高濃度不純物拡散領域と、各
トランスデューサ下の前記エピタキシャルSL層表面部
にそれぞれ形成された第2の高濃度不純物拡散領域とを
含む構成を要旨としているものである.[作用] 上記構成の弾性表面波素子においては、IDT間の抵抗
が実効的に大きくなり、IDT間のインピーダンスが等
価的に高くなり、IDTの容量が大きくなっても、フィ
ード・スルー抑圧を十分大きくすることが可能となる. [実施例] 実施例にさきだって,第1図に前述した第4図および第
5図に示した従来の弾性表面波素子構造のフィード・ス
ルーのバスを示す. この第1図から判るように、前記素子構造は入出力ポー
ト間が大きな容量値をもつコンデンサと、低抵抗の抵抗
の直列接続という等価回路とみなせる.この図から、フ
ィード・スルーを抑圧するには、抵抗を大きくすること
で、理想的には無限大にすれば良いことがわかる. 第2図は、前記の考え力を素子構造に適用した本発明の
一実施例を示したものである。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement in a surface acoustic wave element in which a piezoelectric thin film is formed on a non-piezoelectric substrate. [Summary of the Invention] The present invention provides a surface acoustic wave device that uses direct waves of electromagnetic waves that affect device characteristics.
・Feed-through) [Prior Art] Conventionally, there are surface acoustic wave (SAW) elements shown in FIGS. 4 and 5 in which a piezoelectric thin film is formed on a non-piezoelectric substrate. The surface acoustic wave device shown in FIG. 4 has a silicon oxide film 2 formed on a low resistance silicon single crystal substrate 1, and a ZnO
A piezoelectric thin film 3 is formed, and 4 is a metal electrode for transmitting and receiving SAW provided on the ZnO piezoelectric thin film 3. The surface acoustic wave device shown in FIG. 5 has an epitaxial Si layer 5 between a low resistance silicon single crystal substrate 1 and a silicon oxide film 2 similar to those described above, and further improves the excitation efficiency of the IDT (}-transducer). A high concentration impurity diffusion region 6 is provided in the epitaxial Si layer S under the metal electrode 4 in order to increase the concentration. SA with ZnO/Si structure as above
Various types of W elements are known, but the structure of an element using Sezawa waves with a particularly large electromechanical coupling coefficient is the one shown in FIGS. 4 and 5. Si of the above element
Using a low resistance board as the board. A-E (acousto-elec) between SAW and carrier in semiconductor
tric) This is to minimize energy loss due to interaction, and the configuration shown in Figure 4 is a structure that mainly realizes a SAW filter. Furthermore, in order to realize a functional element that actively utilizes the A-E interaction, such as a convolver, the configuration shown in FIG. 5 in which a relatively thin epitaxial Si layer 5 is provided is adopted. Of course, in order to provide the desired function to the above structure, a gate electrode, a pn diode, etc. Various additional structures such as FETs and gratings are provided to realize actual devices. [Problem M to be solved by the invention] However, in the above element structure, when the number of logarithms of the IDT becomes very large or the capacity of the IDT becomes large, direct waves of electromagnetic waves (feed through
h) may have a large effect on device characteristics. The causes of this feed through are (1) inductive coupling that occurs in matching coils, etc. (2) Capacitive coupling that occurs on the substrate surface of the transmitting and receiving transducer; (3) Capacitive coupling that occurs through the bulk substrate of the transmitting and receiving transducer. In the above element structure, balanced drive has conventionally been adopted to suppress feed-through and also to improve the effective coupling coefficient. When the capacitance of the transducer is small, sufficient suppression is achieved, but when the capacitance becomes large, sufficient suppression cannot be achieved with balanced drive alone. In order to suppress the coupling between the coils, measures such as shielding or providing a shield electrode between IDTs are usually used, but it is difficult to suppress the capacitive coupling due to cause (3) of feed-through. In other words, the element configuration shown in Figures 4 and 5 is. ID
It can be said that it has the disadvantage that it is difficult to suppress feed-through when the capacity of T is large. [Object of the Invention] The present invention is a surface acoustic wave element structure having a piezoelectric thin film formed on a non-piezoelectric substrate, and provides a basic structure in which feed-through is sufficiently suppressed even when the capacitance of an IDT becomes large. It is intended to provide. [Means for Solving the Problems] The first invention includes a laminate including at least a high-resistance silicon single crystal substrate and a piezoelectric thin film, a pair of transducers formed at a predetermined interval on the piezoelectric thin film, A first high-concentration impurity diffusion region formed on the surface portion of the high-resistance silicon single crystal substrate between the transducers, and a first high-concentration impurity diffusion region formed on the surface portion of the high-resistance silicon single crystal substrate below each transducer. The gist of this is a configuration including a second high concentration impurity diffusion region. Furthermore, the second invention includes a laminate including at least a high-resistance silicon single crystal substrate, an epitaxial SL layer, and a piezoelectric thin film, a pair of transducers formed at a predetermined interval on the piezoelectric thin film, and the high-resistance silicon single crystal substrate. A first high-concentration impurity diffusion region formed in a region between the transducers on the surface of the resistive silicon single crystal substrate, and a second high-concentration impurity diffused region formed in the surface of the epitaxial SL layer below each transducer. The gist of this is a configuration that includes a diffusion region. [Function] In the surface acoustic wave device having the above configuration, the resistance between the IDTs becomes effectively large, the impedance between the IDTs becomes equivalently high, and even if the capacitance of the IDTs becomes large, feed-through can be sufficiently suppressed. It is possible to make it larger. [Example] Before starting the example, Fig. 1 shows a feed-through bus of the conventional surface acoustic wave element structure shown in Figs. 4 and 5 described above. As can be seen from Figure 1, the element structure can be regarded as an equivalent circuit consisting of a capacitor with a large capacitance value and a resistor with low resistance connected in series between the input and output ports. From this figure, we can see that to suppress feed-through, the resistance should be increased, ideally to infinity. FIG. 2 shows an embodiment of the present invention in which the above idea is applied to the element structure.

同図において、7は高抵抗シリコン単結晶基板、2はシ
リコン酸化膜、3はZnO圧電薄膜、4はトランスデュ
ーサであり、前記高抵抗シリコン単結晶基板7の表面部
には、トランスデューサ4,4に挟まれた区域に、第1
の高濃度不純物拡散領域8が形成され、さらに各トラン
スデューサ下にはそれぞれ第2の高濃度不純物拡散領域
6,6が形成されている. 前記高抵抗シリコン単結晶基板7を用いたのは,バルク
基単結晶基板での直列抵抗を大きくするためである.完
全な絶縁性を有するSi基板は実現が困難である.その
ため,高抵抗シリコン単結晶基板7内をSAWが伝播す
ると、A−E相互作用によるエネルギー損失があるため
、IDT間の高抵抗シリコン単結晶基板7内に高濃度不
純物拡散領域6とは分離して高濃度不純物拡散領域8を
設けている. 第3図に示したものは、本発明の他の実施例であって,
7は高抵抗シリコン単結晶基板、5はエピタキシャルS
i層,2はシリコン酸化膜,3は圧電薄膜であり,前記
エピタキシャルSi層5内に高濃度不純物拡散領域6,
6が形成され、前記高抵抗シリコン単結晶基板7内に高
濃度不純物拡散領域8が形成されたものである. なお、コンボルバのように、素子の縦方向に電界をかけ
る必要がある場合は.ZnO圧電薄膜上にゲート電極を
設け,相互作用領域外のエピタキシャルSi層5内に高
濃度に不純物を打ち込み,大きな面積でオーミック・コ
ンタクトをとれば、直列抵抗を上げずにゲートと高濃度
不純物拡散領域8との間に電界を印加できる. 前記各実施例では、圧電薄膜にZnO を用いているが
、A EI N , Ta, O,などを用いても、前
記と同じ効果が得られる. [発明の効果] 以上に述べたように,本発明の弾性表面波素子構成によ
れば、IDT間の抵抗が実効的に大きくなり、IDT間
のインピーダンスが等価的に高くなり.IDTの容量が
大きくなっても、フィード・スルー抑圧を十分大きくす
ることができる.
In the figure, 7 is a high resistance silicon single crystal substrate, 2 is a silicon oxide film, 3 is a ZnO piezoelectric thin film, and 4 is a transducer. In the sandwiched area, the first
A high concentration impurity diffusion region 8 is formed, and second high concentration impurity diffusion regions 6, 6 are formed under each transducer. The reason for using the high resistance silicon single crystal substrate 7 is to increase the series resistance in the bulk single crystal substrate. It is difficult to realize a Si substrate with perfect insulation properties. Therefore, when the SAW propagates within the high-resistance silicon single-crystal substrate 7, there is energy loss due to the A-E interaction. A high concentration impurity diffusion region 8 is provided. What is shown in FIG. 3 is another embodiment of the present invention, which includes:
7 is a high resistance silicon single crystal substrate, 5 is an epitaxial S
The i layer, 2 is a silicon oxide film, 3 is a piezoelectric thin film, and in the epitaxial Si layer 5 there are high concentration impurity diffusion regions 6,
6 is formed, and a high concentration impurity diffusion region 8 is formed in the high resistance silicon single crystal substrate 7. In addition, when it is necessary to apply an electric field in the vertical direction of the element, such as in a convolver. If a gate electrode is provided on the ZnO piezoelectric thin film, and impurities are implanted at a high concentration into the epitaxial Si layer 5 outside the interaction region, and ohmic contact is established over a large area, the high concentration impurity can be diffused between the gate and the high concentration impurity without increasing the series resistance. An electric field can be applied between the region 8 and the region 8. In each of the above embodiments, ZnO is used for the piezoelectric thin film, but the same effect as described above can be obtained by using A EI N , Ta, O, or the like. [Effects of the Invention] As described above, according to the surface acoustic wave element configuration of the present invention, the resistance between the IDTs becomes effectively large, and the impedance between the IDTs becomes equivalently high. Even if the IDT capacity increases, feed-through suppression can be sufficiently increased.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の原理を説明する弾性表面波素子構成図
、第2図および第3図はそれぞれ本発明の実施例を示す
弾性表面波素子の側面図、第4図および第5図は従来の
弾性表面波素子の側面図である. 1・・・・・・・・・低抵抗Si単結晶基板、2・・・
・・・・・・シリコン酸化膜、3・・・・・・・・・Z
nO圧電薄膜、4・・・・・・・・・トランスデューサ
、5・・・・・・・・・エピタキシャルSi層、6・・
・・・・・・・高濃度不純物拡散領域, 7・・・・・
・・・・高抵抗シリコン単結晶基板、8・・・・・・・
・・高濃度不純物拡散領域. 特許出願人    クラリオン株式会社代理人 弁理士
  永 田 武 三 郎第4図 第5図 第 I 図
FIG. 1 is a configuration diagram of a surface acoustic wave device explaining the principle of the present invention, FIGS. 2 and 3 are side views of the surface acoustic wave device showing embodiments of the present invention, and FIGS. 4 and 5 are FIG. 2 is a side view of a conventional surface acoustic wave device. 1...Low resistance Si single crystal substrate, 2...
・・・・・・Silicon oxide film, 3・・・・・・・・・Z
nO piezoelectric thin film, 4...Transducer, 5...Epitaxial Si layer, 6...
...High concentration impurity diffusion region, 7...
...High resistance silicon single crystal substrate, 8...
...High concentration impurity diffusion region. Patent Applicant Clarion Co., Ltd. Agent Patent Attorney Takesaburo Nagata Figure 4 Figure 5 Figure I

Claims (2)

【特許請求の範囲】[Claims] (1)少なくとも高抵抗シリコン単結晶基板と圧電薄膜
とからなる積層体と、 前記圧電薄膜上に所定間隔をもって形成された1対のト
ランスデューサと、 前記高抵抗シリコン単結晶基板表面部における前記トラ
ンスデューサに挟まれた区域に形成された第1の高濃度
不純物拡散領域と、 各トランスデューサ下の前記高抵抗シリコン単結晶基板
表面部にそれぞれ形成された第2の高濃度不純物拡散領
域とを含むことを特徴とする弾性表面波素子。
(1) A laminate including at least a high-resistance silicon single crystal substrate and a piezoelectric thin film, a pair of transducers formed on the piezoelectric thin film at a predetermined interval, and the transducer on the surface of the high-resistance silicon single crystal substrate. A first high concentration impurity diffusion region formed in the sandwiched area, and a second high concentration impurity diffusion region formed on the surface portion of the high resistance silicon single crystal substrate under each transducer. surface acoustic wave device.
(2)少なくとも高抵抗シリコン単結晶基板とエピタキ
シャルSi層と圧電薄膜とからなる積層体と、 前記圧電薄膜上に所定間隔をもって形成された1対のト
ランスデューサと、 前記高抵抗シリコン単結晶基板表面部における前記トラ
ンスデューサに挟まれた区域に形成された第1の高濃度
不純物拡散領域と、 各トランスデューサ下の前記エピタキシャルSi層表面
部にそれぞれ形成された第2の高濃度不純物拡散領域と
を含むことを特徴とする弾性表面波素子。
(2) A laminate including at least a high-resistance silicon single crystal substrate, an epitaxial Si layer, and a piezoelectric thin film, a pair of transducers formed at a predetermined distance on the piezoelectric thin film, and a surface portion of the high-resistance silicon single crystal substrate. a first high-concentration impurity diffusion region formed in an area sandwiched between the transducers; and a second high-concentration impurity diffusion region formed in a surface portion of the epitaxial Si layer under each transducer. Characteristic surface acoustic wave device.
JP11267389A 1989-05-01 1989-05-01 Surface acoustic wave element Pending JPH02291711A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11267389A JPH02291711A (en) 1989-05-01 1989-05-01 Surface acoustic wave element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11267389A JPH02291711A (en) 1989-05-01 1989-05-01 Surface acoustic wave element

Publications (1)

Publication Number Publication Date
JPH02291711A true JPH02291711A (en) 1990-12-03

Family

ID=14592618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11267389A Pending JPH02291711A (en) 1989-05-01 1989-05-01 Surface acoustic wave element

Country Status (1)

Country Link
JP (1) JPH02291711A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019111893A1 (en) * 2017-12-06 2019-06-13 株式会社村田製作所 Acoustic wave device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2019111893A1 (en) * 2017-12-06 2019-06-13 株式会社村田製作所 Acoustic wave device

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