JPH02290329A - Logic circuit - Google Patents

Abstract

PURPOSE:To lead the level of an output terminal to logic H without a malfunction by providing a current absorbing means, activating the means in response to the L level designation of L, H designation signal and absorbing a current given to the control electrode of a transistor(TR) provided between a high level point and the output terminal. CONSTITUTION:While the level of an input terminal 33 is logic L, when the level is lowered up to 1.5V, the level is equal to a voltage between the bases of TRs Q42, 41, which are turned on and the current path of a current absorbing circuit 80 from the base of a TR Q9 to a low level power connection terminal 32 is established and the base current of the TR Q9 is extracted at the high speed. While the level of the terminal 33 is logic L, the TR Q1 is turned on and TRs Q2, Q3 and diodes 10, 43, 44 are turned off, the base level of the TRs Q42, 41 is equal to each other and the TRs keep the ON state and the current absorbing circuit 80 is activated. When the level at the terminal 32 is lowered, the base current flows to a FET 9, while the base level of a FET 42 is nearly 2V with respect to the terminal 33 and the level of the FET 42 is nearly 2V with respect to the terminal 32, and since the difference is slight, the circuit 80 is kept active and the base current to the FET 9 is absorbed immediately by the low level power connection terminal 32 and the FET 9 is not turned on. Thus, when the level of the input terminal 33 is logic L, even when the level of the terminal 32 is lowered, the level of the output terminal 34 is not tentatively inverted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to logic circuits, particularly for example ALSTTL (
＾dvance Low Power Schottk
y Transistor-Transistor L
This relates to the output circuit of Logic.

[Conventional technology]

Figure 3 shows the 1987 Mitsubishi Semiconductor Data Book <ALS
Semiconductor integrated circuit M74ALS2 disclosed in TTL>
FIG. 2 is a circuit diagram showing a part of the output circuit of 44AP. This output circuit consists of PNP } transistor 1, NPN with Schottky clamp } transistor 2 to 8, NP connected between high voltage level mR connection terminal 31 and low potential power supply connection terminal 32.
It includes an NI-transistor 9, a PN junction diode 10, Schottky barrier diodes 11-14, and resistors 15-23, and is configured to output a non-inverted signal of the signal applied to the human power terminal 33 to the output terminal 34.

When the potential of the human input terminal 33 is at a low level, transistors 1, 4.7 are turned on, transistors 2, 3, and 8.9 are turned off, and the potential of the output terminal 34 is at a low level. When the potential of the input terminal 33 changes from low level to high level, transistor 1 is turned off, and then transistors 2, 3, .
4 turns on, on, and off in sequence. When transistor 4 is turned off, transistor 7 is turned off, and transistor 8 is also turned off.
, 9 are turned on. As a result, the potential of the output terminal 34 changes from low level to high level.

[Problem to be solved by the invention]

Since the conventional logic circuit is configured as described above, if the potential of the low-potential power supply connection terminal 32 decreases significantly due to noise or the like, the output terminal 34 will change when a low-level signal is applied to the input terminal 33. There was a problem that the potential temporarily became /\I level. That is, when the potential of the input terminal 33 is at a low level, the transistor 1 is turned on, so the base potential of the transistor 2 is lowered, and therefore the transistors 2 and 3 and the diode 10 are turned off. However, the potential of the low potential power supply connection terminal 32 is
Transistors 2 and 3 are lower than the base potential of transistor 2.
When the voltage becomes lower than the total threshold voltage of diode 10, transistor 2.3 and diode 10 are turned on. When transistor 3 and diode 10 are turned on, transistor 4 is turned off, and in response to this, transistor 7 changes from on to off, and transistors 8 and 9 change from off to on. As a result, the potential of the output terminal 34, which should be at a low level in response to the low level of the input terminal 33, temporarily becomes a high level until the potential of the low potential power supply connection terminal 32 recovers.

This invention was made to solve the above-mentioned problems, and it provides a logic circuit in which the signal level of the output terminal does not change even if the potential of the low-potential power supply connection terminal decreases due to noise etc. The purpose is to obtain.

[Means to solve the problem]

In the logic circuit according to the present invention, a human power means for receiving a signal specifying low or high of an output terminal, a control electrode is operatively coupled to the input means, and the first and second electrodes are connected to a high potential point and a high potential point, respectively. A first transistor connected to the output terminal and turned on in response to a high designation of a signal that designates low or high of the output terminal and turned off in response to a low designation, and a control electrode that is operatively connected to the input means. The first and second electrodes are connected to the output terminal and the low potential point, respectively, and turn on in response to a low designation of a signal that designates low or high of the output terminal, and in response to a high designation. a second transistor that is connected to the control electrode of the first transistor and the input means, and is activated in response to a low designation of a signal that designates low or high of the output terminal applied to the input means; and current absorbing means for absorbing the current applied to the control electrode of the first transistor.

[Effect]

The current absorbing means in this invention is the output terminal row. It is activated in response to designation of a low signal that designates high, and absorbs the current applied to the control electrode of the first transistor provided between the high potential point and the output terminal. Therefore, when specifying low, the first transistor for guiding the output terminal to high will not be erroneously turned on.

〔Example〕

FIG. 1 is a circuit diagram showing an embodiment of a logic circuit according to the present invention. This logic circuit is constructed by adding a PNP transistor 41, an NPN transistor with Schottky clamp 42, and a PN junction diode 43 to the conventional logic circuit shown in FIG.
It also has a configuration in which a current absorption circuit 80 consisting of Schottky barrier diodes 44 and 45 is added.

In FIG. 1, a buffer is provided between the input terminal 33 and the base of the Schottky clamped NPN transistor 4 to invert the level of the signal applied to the input terminal 33 and apply it to the base of the transistor 4. An inverter 50 is provided. The inverter 50 includes a PNP l-transistor 1 whose base is connected to the input terminal 33, an NPN transistor 2 with a Schottky clamp whose base is connected to the emitter of the transistor 1, an anode to the emitter of the transistor 2, and an anode to the base of the transistor 1. an NPN transistor 3 with a Schottky clamp whose base is connected to the emitter of the transistor 3; an anode connected to the emitter of the transistor 3;
It consists of PN junction diodes 10 each having a cathode connected to a terminal 32 for connecting a low potential power source. diode 12
extracts the base charge of the transistor 3 when the potential of the input terminal 33 is reversed from high level to low level,
It serves to hasten the turn-off of transistor 3. The connection point between the emitter of transistor 1 and the base of transistor 2 is connected to a high potential fT! via a resistor 15. ll connection terminal 3
1, and the collector of the transistor 1 is connected to the low potential power supply connection terminal 32. The collector of the transistor 2 is connected to the cathode of the horizontal-sol-chivalry diode 44.

Further, the collector of the transistor 3 which provides the output of the inverter 50 is connected to the base of the transistor 4 and also connected to the high potential power supply connection terminal 31 via the resistor 17.

The emitter of the transistor 4 serves as an active pull-down circuit and is connected to the base of an NPN transistor 7 with a Schottky clamp via a square circuit 60. The collector of the transistor 7 is connected to the output terminal 34, and the emitter and the output terminal are connected to the low potential power supply connection terminal 32. Square circuit 60 is NPN with Schottky clamp
It consists of a transistor 6 and resistors 21 and 22. The base of the transistor 6 is connected to the connection point between the emitter and the base of the transistor 7 through a resistor 21 and the collector through a resistor 22, respectively, and the emitter is connected to a terminal 32 for connecting a low potential power supply. connected to.

The square circuit 60 has the role of extracting the base charge of the transistor 7 when the transistor 7 is turned off to hasten the turn-off, or to flow a part of the base current to the low potential side when an excessive base current is supplied to the base of the transistor 7. do.

The collector of the transistor 4 is connected to an output Darlington circuit 70, which is functionally equivalent to one transistor element, and is also connected to a high potential power supply connection terminal 31 via a resistor 18. The output Darlington circuit 70 is
NPN transistor 8 and N with Schottky clamp
It consists of a PN transistor 9. The base of transistor 8 is connected to the collector of transistor 4, the collector is connected to the collector of transistor 9, and the emitter is connected to the base of transistor 9.
each connected to the The emitter of the transistor 9 is connected to the output terminal 34, and the collector is connected to the high potential power supply connection terminal 31 via the resistor 20. The base of the transistor 9 is connected to a low potential power supply connection terminal 32 via a pull-down resistor 23.

Between the output terminal 34 and the collector of the transistor 4,
A Schottky barrier diode] 3 and an NPN transistor 5 with a Schottky clamp are connected in series.

The emitter of the transistor 5 is connected to the collector of the transistor 4, the collector to the cathode of the diode 13, and the base to the high potential power supply connection terminal 31 via a resistor 19. The anode of the diode 13 is the output terminal 34
connected to. The transistor 5 is turned on when the transistor 7 is turned on, and serves to supply a base current from the output terminal 34 to the base of the I transistor 7 via the transistor 4, thereby speeding up the turn-on of the transistor 7. The diode 13 is for preventing current backflow.

Between the input terminal 33 and the low potential power supply connection terminal 32,
An input clamp Schottky barrier diode 11 is connected to supply current from the low potential power supply connection terminal 32 to the input terminal 33 when the low level potential of the input terminal 33 undershoots. Further, between the output terminal 34 and the low-potential power supply connection terminal 32, there is provided an output for supplying current from the low-potential power supply connection terminal 32 to the output terminal 34 when the low-level potential of the output terminal 34 undershoots. A clamp Schottky barrier diode 14 is connected.

The base of the transistor 9 in the output Darlington circuit 70 is connected to a current absorption circuit 80 for absorbing the current flowing into the base of the transistor 9 when the potential of the input terminal 33 is at a low level.

In the configuration of current absorption circuit 80, the anode of diode 45 is connected to the base of transistor 9, and the cathode is connected to the collector of transistor 42. The emitter of the transistor 42 is connected to the emitter of the transistor 41, the base is connected to the anode of the diode 43, and the high potential power supply connection terminal 3 is connected via the resistor 16.
Connected to 1. The cathode of the diode 43 is connected to the anode of the diode 44, and the cathode of the diode 44 is connected to the reflector of the transistor 2.

The collector of the transistor 41 is the low potential power supply connection terminal 3
Connected to 2.

The transistor 42 establishes an absorption path for the base current of the transistor 9 by becoming conductive when the potential of the human input terminal 33 is at a low level. As level shifting means for setting the operating point of transistor 42 in relation to the potential of input terminal 33, the base-emitter junction of transistor 41 and diodes 43, 44 are utilized as will be explained in more detail below. The transistor 41 also transfers the absorbed base current of the transistor 9 to the low potential power supply connection terminal 32.
It plays the role of letting people escape to the other side. The diode 45 prevents current from flowing from the high-potential power supply connection terminal 31 to the base of the transistor 9 through the base-collector junction of the transistor 42 when the potential of the output terminal 34 is at a low level, that is, when the transistor 9 is off. fulfill the role of

In the normal operation of the logic circuit shown in FIG.
When the potential of transistor 3 is at a low level, transistor 1 is turned on, and since the collector potential of transistor 1, that is, the base potential of transistor 2 decreases, transistor 2 is turned off. As a result, the supply of base current to the transistor 3 is stopped, so the transistor 3 is turned off, and the collector potential of the transistor 3 becomes high level. That is, the low level applied to the input terminal 33 is inverted by the inverter 50 and becomes high level. Transistor 4 turns on in response to this high level, and current is supplied to the base of transistor 7 through transistor 4, so transistor 7 turns on. On the other hand, since the collector potential of transistor 4, that is, the base potential of transistor 8 decreases, transistor 8 is turned off, and transistor 9
Since the supply of base current to the transistor 9 is stopped, the transistor 9 is turned off. Therefore, a current is sucked from the output terminal 34 to the low potential power supply connection terminal 32 via the transistor 7, so that the potential of the output terminal 34 becomes low level.

Next, when the potential of the input terminal 33 is inverted from the low level to the high level, the transistor 1 is turned off, and the collector potential of the transistor 1, that is, the base potential of the transistor 2 increases, so that the transistor 2 is turned on. As a result, transistor 2 is turned off and current is supplied to the base of transistor 3, so transistor 3 is turned on and the collector potential of transistor 3 becomes low level. That is, the high level applied to the input terminal 33 is applied to the inverter 5.
It is inverted by 0 and becomes low level. transistor 4
turns off in response to this low level, and the supply of base current to transistor 7 is stopped, so transistor 7
is turned off. On the other hand, since the collector potential of the transistor 4, that is, the base potential of the transistor 8 increases, the transistor 8 is turned on, and the base current is supplied to the transistor 9, so that the transistor 9 is turned on. For this reason, resistance 2
Since current is supplied from the high-potential power supply connection terminal 31 to the output terminal 34 via the transistor 9 and the transistor 9, the potential of the output terminal 34 becomes high level.

In the logic circuit shown in FIG. 1, the high-level threshold of the input terminal 33 is given by the following equation with reference to the potential of the low-potential power supply connection terminal 32.

v +v +v −v
F10 BE3 11E2
[IEl1 0. 75 + 0.75 +
0.75 - 0.75 - 1.5 (V)
...(1)
Here, ■ is the forward voltage of the diode 10, F10 V, ■ and V are the transistor BE3, respectively.
I3E2 is the base-emitter voltage of 8EI stars 3, 2 and 1. That is, in the logic circuit shown in FIG. 1, when the potential of the input terminal 33 increases by 1.5 V or more based on the potential of the low-potential power supply connection terminal 32, a high level is output to the output terminal 34, and otherwise a low level is output. be done. For example, the input signal applied to the input terminal 33 has a high level of 2. OV may be a signal whose low level has a logic amplitude of 0.5V.

Next, the operation of the current absorption circuit 80 will be explained.

When the potential of the human power terminal 33 is at a high level, the transistor 1 is off and the transistors 2 and 3 and the diode 10 are on, as described above. Since the collector potential of transistor 2 decreases, diodes 43 and 44 are turned on. The heath potential of the transistor 42 at this time is given by the following equation with reference to the potential of the low potential power supply connection terminal 32.

v +v +v +v +vFIO
BF:3 CE2 F44 F43-
0.75 + 0.75 + 0.25 +
0.5+ 0.75-3.0(V)
...(2) Here, ■ is the voltage between the collector and CB2 of transistor 2, and ■ and V are the voltage between the collector and CB2, respectively.
4 P43 is the forward voltage of diodes 44 and 43.

Now, the high level of the input terminal 33 is 2. OV, the potential difference between the base of transistor 42 and the base of transistor 41 is 3.0 −2.0 −
1.0 (V) ...(3). In order for transistors 42 and 41 to turn on, v +v =0.75+ is applied between their bases.
A potential difference of 0.75-1.5 (V) 13E42 BE41 (4) is required. In addition, V, ■ Haso BE4
2 nE41 is the base-emitter voltage of the transistors 42 and 41, respectively. Therefore, transistors 42 and 41 are not turned on. Therefore, a current absorption path in the current absorption circuit 80 from the base of the transistor 9 in the output Darlington circuit 70 to the low potential power supply connection terminal 32 is not established. In this way, when the potential of the input terminal 33 is at a high level, the current absorption circuit 80 is disabled, and the output Darlington circuit 7
The base current of transistor 9 in 0 is not withdrawn, and transistor 9 can continue to be turned on as usual.

During the transition period in which the potential of the human power terminal 33 is reversed from high level to low level, the potential of the human power terminal 33 is 1.5V.
When the potential difference between the base of transistor 42 and the base of transistor 41 decreases to 3.0 −1.5 −1.5 (V)
-(5), and the transistors 42 and 41 are immediately turned on. Therefore, a current absorption path within the current absorption circuit 80 from the base of the transistor 9 to the low potential power supply connection terminal 32 is established, and the base current of the transistor 9 is drawn out at high speed through this current absorption path. As a result, the transistor 9 is turned off earlier than in the case where the base current is slowly drawn out by the high-resistance pull-down resistor 23, so that the potential of the output terminal 34 falls from a high level to a low level more quickly.

While the potential of the input terminal 33 is at a low level, the transistor 1
is on, transistor 2.3 and diode 10 are off, and diodes 43 and 44 are turned off in response to transistor 2 being turned off. Therefore, the base potential of transistor 42 is approximately the same as the potential of high potential power supply connection terminal 31. be equal. Thus, transistors 41-42 remain on and current absorbing circuit 80 remains activated. At this time,
When the potential of the low-potential power supply connection terminal 32 undershoots due to noise or the like, the transistors 2 and 3 and the diode 10, which had been off, are turned on, as described above. For example, if the low level of the input terminal 33 is 0.5■, the base potential of the transistor 2 is 0.5+V - 0.
5+ 0.75 - 1.25 (V)[3E1...(6) Therefore, the potential of the low potential power supply connection terminal 32 is 1.2
5-V-V-VI3E2
BE3 PIO- 1.25-0
．． 75 - 0.75 - 0.75--
t. O(V)・
...(7) When the voltage drops to or below, the transistor 2.3 and the diode 10 are turned on.

As a result, transistor 4 is turned off, and in response, transistor 8 is turned on, so that base current is supplied to transistor 9. On the other hand, in response to transistor 2.3 and diode 10 being turned on, diodes 43 and 44 are turned on. At this time, the base potential of the transistor 42 is 0.5+V +V I3E41 8B42 -0.5 +0.75+0.75-2.0 (V) based on the potential of the input terminal 33.
．． (8) Based on the potential of the low potential power supply connection terminal 32, -t. o+v +v +v
+v +v1'lO BE3. CB2
F44 I'43- -1.0+ 0.75+
0.75 + O: 25 0.5 + 0.75-2.
0 (V) ... (9
). In other words, the potential of the low potential power supply connection terminal 32 is -t. Even if it drops below OV, the amplitude of the base potential of the transistor 42 is very small, and the amplitude of the base potential of the transistor 42 is transiently
2.41 remains on and the current absorbing circuit 80 remains activated. Therefore, the base current supplied to the base of the transistor 9 via the transistor 8 is immediately absorbed into the low potential power supply connection terminal 32 via the current absorption path consisting of the diode 45, the transistor 42, and the transistor 41 in the current absorption circuit 80. 1/Rangister 9
is not turned on. As a result, even if the potential of the low-potential power supply connection terminal 32 undershoots due to noise or the like when the input terminal 33 is at a low level, the potential of the output terminal 34 will not be temporarily reversed to a high level.

In the logic circuit of FIG. 1, the operating point related to the potential of the input terminal 33 of the transistor 42, which acts as a switch for opening and closing the current absorption path, is determined by using the base-emitter junction of the transistor 41 and the diodes 43, 44 as level shifting means. By this, l. It is set to 5V.

If the transistor 41 is used only as a level shifting means, a diode having an anode connected to the emitter of the transistor 42 and a cathode connected to the input terminal 33 may be used in place of the transistor 41. In this case, the base current of the transistor 9 absorbed through the current absorption path in the current absorption circuit 80 is supplied to the human power terminal 33, which causes the potential of the input terminal 33 to fluctuate. Therefore, it is desirable to provide a transistor 41 which is also used as a level shift means as in the circuit shown in FIG. 1, and to release the absorbed current to the low potential power supply connection terminal 32 via the transistor 41.

FIG. 2 is a circuit diagram showing another embodiment of the logic circuit according to the present invention. This embodiment has a configuration in which a Schottky barrier diode 46 is added to the current absorption circuit 80 of the embodiment shown in FIG.

The anode of the Schottky barrier diode 46 is connected to the base of the transistor 8 in the output Darlint circuit 70, and the cathode is connected to the collector of the transistor 42. The other configurations are similar to the embodiment shown in FIG.

In this embodiment, current absorption circuit 80 includes transistor 9
Since the output Darlington circuit 70 is turned off by drawing out not only the base current of the transistor 8 but also the base current of the transistor 8, the output Darlington circuit 70 can be turned off more quickly and reliably. The extracted base current flows through the diode 45
．． 46 and transistors 42 and 41, the current is absorbed by the low potential power supply connection terminal 32.

The diode 46 serves to prevent current from flowing from the high potential power supply connection terminal 31 to the base of the transistor 8 via the base-collector junction of the transistor 42 . The on/off timing of the transistors 42 and 4l, that is, the activation timing of the current absorption circuit 80, is the same as in the previous embodiment. Therefore, in this embodiment as well, the input terminal 33 is at a low level. Even if the potential of the low-potential power supply connection terminal 32 undershoots due to noise or the like, the current absorption circuit 80 prevents the potential of the output terminal 34 from inverting to the noise level at one point in time.

In each of the above embodiments, a circuit using a Schottky clamp transistor and a Schottky barrier diode has been described, but other transistors or diodes can be used by making appropriate changes to the circuit.

〔Effect of the invention〕

As explained above, according to the present invention, the first terminal provided between the high potential point and the output terminal is activated in response to the designation of low of the signal that designates the low or high of the output terminal. Since a current absorption means is provided to absorb the current applied to the control electrode of the first transistor, the first transistor will not be accidentally turned on when specifying LOW, and for example, the potential of the low potential point will not drop due to noise, etc. This has the effect that a logic circuit can be obtained in which the signal level of the output terminal does not change even if the output terminal is changed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing one embodiment of a logic circuit according to the present invention, FIG. 2 is a circuit diagram showing another embodiment of the logic circuit according to the invention, and FIG. 3 is a circuit diagram showing a conventional logic circuit. be. In the figure, 7 and 8 are NPNI- with Schottky clamps.
transistor, 9 is NPN} transistor, 31 is high potential r1#. Connection terminal, 32 is a low potential power supply connection terminal, 3
3 is a human power terminal, and 34 is an output terminal. 70 is an output Darlington circuit, and 80 is a current absorption circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) A logic circuit that performs low and high logic output by selectively connecting the output terminal to either a low potential point or a high potential point according to a signal specifying low or high of the output terminal. an input means for receiving a signal specifying low or high of the output terminal; a control electrode operatively coupled to the input means; and a first and second electrode connected to the high potential point and the output terminal, respectively; a first transistor connected to the output terminal and turned on in response to a high specification of a signal specifying low or high of the output terminal, and turned off in response to a low specification; a control electrode actuated by the input means; and first and second electrodes are connected to the output terminal and the low potential point, respectively, and turn on in response to designation of low or high of a signal that designates low or high of the output terminal. a second transistor that is turned off in response to the designation of the output terminal; and a second transistor that is connected to the control electrode of the first transistor and the input means, and that is connected to the control electrode of the first transistor and that is supplied to the input means to designate the low or high level of the output terminal. a logic circuit comprising current absorbing means that is activated in response to a designation and absorbs a current applied to a control electrode of the first transistor.