JPH0229024A - Phase shifter and multiplying circuit - Google Patents

Abstract

PURPOSE:To keep the phase shift of an output signal of a phase shifter constant even with respect to a frequency change in an input signal by controlling a variable capacitive component or a variable resistive element in an RC phase circuit so that the level of an output signal is constant with respect to the input signal. CONSTITUTION:A circuit comprising a resistor 211 and a variable capacitor 231 is a low pass filter type phase circuit and the phase of an output signal Vout1 is controlled to be led by 45 deg. to that of an input signal Vin. Moreover, a circuit comprising a resistor 221 and a variable capacitor 241 is a high pass filter type phase circuit and the phase of an output signal Vout2 is controlled to be lagged by 45 deg. to that of the input signal Vin. The phase difference between the voltages Vout1 and Vout2 is 90 deg.. The peak of the amplitude of the voltage Vout1 is detected by a peak detector 321, the peak value and an output signal Vin/2<1/2> are compared by a peak detector 331, the output of the error detector 331 is given as the control input of capacitors 231, 241 so that they are equal to each other thereby applying the feedback control, then the phase difference between the voltages Vout1 and Vout2 is kept constant against the frequency change in the signal Vin.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Field of Application Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Operation Example 1, Structure and operation of phase shifter (i) No. 1st Example (11) 2nd Example (iii) 3rd Example (iv) 4th Example (v) 5th Example (vi) 6th Example ■, Structure and operation of multiplier circuit Effects of the invention [Overview] Regarding a frequency change compensation type phase shifter in which the amount of phase shift of the output signal does not change even when the input signal frequency changes, and a multiplier circuit using this phase shifter, In order to maintain the phase shift amount of the output signal constant, an RC phase circuit including a variable capacitance element or a variable resistance element, and an input signal and an output signal of the RC phase circuit are input. The lever includes a comparison circuit that compares the input signal and the output signal, and the comparison circuit has R so that the level of the output signal is a predetermined ratio to the level of the input signal.
It is configured to provide a control input to the C phase circuit.

Further, a control input is provided to the RC phase circuit so that the phase difference between the two output signals of the RC phase circuit becomes a predetermined value.

Further, these phase shifters are configured to control the phase difference between the two output signals to 90° and to obtain the exclusive OR of these output signals.

[Industrial application field]

The present invention relates to a frequency change compensation type phase shifter in which the amount of phase shift of an output signal does not change even when the frequency of an input signal changes.

The present invention also relates to a multiplier circuit using this phase shifter.

Note that in this specification, a circuit that obtains an output signal with a predetermined phase difference with respect to an input signal, or a circuit that obtains a plurality of output signals with a predetermined phase difference, is referred to as a "phase shifter."

[Conventional technology]

FIG. 12 shows a conventional example of a phase shifter (referred to as the conventional example (■)). In the figure, 921, 923 are resistors, 925,
927 indicates Chiabashita, respectively. resistor 92
1 and resistor 923 have a resistance value of R, R2, respectively, and chia resistor 925 and chia resistor 927 each have a resistance value of CI
, C! chia pasitance. This phase shifter shifts the phase of the input signal ■in by +45° and -45', respectively, to obtain two output signals Vout, Voutt with the same amplitude value and a phase difference of 90°. .

The conditions under which the phase difference between the output signals VouL+ and Vout2 of this conventional phase shifter is 90° are determined based on the following equation.

...(1) ...(2) Therefore, R,=1/ωC2 ...(3) R2=1/ωC2...(4) To (and, Vout+= (1+ j) Vin/2 -(5
)Voutz=(1j) Vin/2-(6)
Therefore, the complex representation of the output signals Vout+ and Voutz is shown in FIG. 13, and therefore the output signal ■ou
t1 and Voutl have a phase difference of 90''.

Further, FIG. 14 shows another conventional example of a phase shifter (referred to as the conventional example (■)). In the figure, 931 and 933 are resistors, 935 is a chiavascilla, and 937° and 939 are signal sources, respectively. The resistor 931 and the resistor 933 have resistance values of R2 and Rz, respectively, and the resistor 935 has a resistance value of C.
It has a chiavasitance of This phase shifter is a signal source 93
2 with inverted polarity output from each of 7,939.
This is to obtain two output signals Voutl and Voutz with a phase difference of 90° based on one input signal Vin.

The conditions under which the phase shift amount of the output signals VoutI and Vout2 of this phase shifter is 90° are determined based on the following formula.

Vout+ = (1(ωC)” (R+” Rz”
)j 2(1)CRI) ・Vin/ni-(7)
Voutz= (1((1)C)” (R1” R2
”) + j 2 ωCRz ) ・Vin/K−(
8) However, K=1+(ωc (R1+Rz))" Therefore, R+>Rz...(9) If we set ωC(R+Rz)=1...0ω, then Vout+= (2ωC(Rz +j Rυ)- Vi
n/K − (10 Vout, = (2ωC(R+jRz))・vin
/K...021, and the complex representation of the output signals Vout+ and Voutz becomes as shown in FIG. 15, so the output signal Vou
tl and Voutz have a phase difference of 90°.

[Problem to be solved by the invention]

By the way, in the conventional example (2) mentioned above, the output signal V
In order to give an accurate phase difference of 90'' to out+ and Voutz, it is necessary to satisfy conditional expressions (3) and (4).Here, R=R,=R.

C=C=C.

Then, from conditional expressions (3) and (4), R=1/ωC, and therefore the frequency f0 of the input signal Vin is f,=
ω/(2π)=1/(2πCR), which is determined in one way for the values of C and R. Therefore, the frequency f of the input signal Vin. When Vout+ and Voutz change, the output signals Vout+ and Voutz
The phase difference between the two ends also changes from 90°. Like this ■
The conventional phase shifter has a problem in that the phase difference of the output signal cannot be maintained constant against changes in the frequency of the input signal Vin.

In addition, in the conventional example (3), the output signals Vout+ and V
In order to give an accurate 90° phase difference to outz, it is necessary to satisfy conditional expression 00), so the frequency f0 of the input signal is fo = C/2π = 1/(2πC(R1-R2)). One way is determined for the values of C, R, , R2. Therefore, similar to the conventional example (2), there is a problem in that the phase difference of the output signal cannot be maintained constant with respect to changes in the frequency of the input signal (2)in.

On the other hand, there is a multiplier circuit that needs to follow such changes in the frequency of an input signal. A conventional multiplier circuit is shown in FIG. 16(a), where 941 represents an exclusive OR gate and 943 represents a delay circuit. Further, FIG. 16(b) shows the signal states of each part of the multiplier circuit shown in FIG. 16(a). "Signal A" is the input signal,
"Signal B" indicates the output signal of the delay circuit 943, and "2x output" indicates the output signal of the exclusive OR game 1-941.

An input signal is input as is to one input terminal of the exclusive OR gate, and a signal obtained by delaying the input signal by a delay circuit 943 is input to the other input terminal. By calculating the exclusive OR of these two inputs, a signal with twice the frequency of the input signal can be obtained.

By the way, the amount of signal delay by the delay circuit 943 of this conventional multiplier circuit needs to be changed depending on the frequency of the input signal. If the frequency of the input signal is fo, the period T0
becomes To ``” 1 / f o, and this T0/4
need to be delayed for an amount of time. However, when the delay circuit 943 is constructed of a delay line or the like, it is difficult to easily change the amount of delay, so there is a problem that it cannot easily follow changes in the frequency of the input signal.

The present invention was created in view of these points, and aims to provide a frequency-compensated phase shifter that can maintain a constant phase shift amount of an output signal even when the frequency of an input signal changes. The purpose is

Another object of the present invention is to provide a multiplier circuit that can easily follow changes in the frequency of an input signal.

[Means to solve the problem]

Figure 1(a) is a block diagram of the principle of the phase shifter according to claim 1.

In the figure, the RC phase circuit 111 includes a variable capacitive element or a variable resistance element.

The comparison circuit 113 receives the input signal and output signal of the RC phase circuit 111, and compares the input signal and the output signal.

Overall, the comparator circuit 113 is configured to provide a control input to the RC phase circuit 111 so that the level of the output signal is at a predetermined ratio to the level of the input signal.

j Shinko 2 l FIG. 1(b) is a block diagram of the principle of the phase shifter according to claim 2.

In the figure, the first capacitive element 123 has one end connected to the input terminal, the other end connected to the first output terminal, and is grounded via the first resistive element 121.

The second capacitive element 127 has one end grounded, the other end connected to the second output terminal, and also connected to the input terminal via the second resistive element 125.

The comparison circuit 129 compares the phases of two output signals output from the first output terminal and the second output terminal.

Overall, at least one of the first capacitive element 123 and the second capacitive element 127 is a variable capacitive element. The capacitive element is configured to provide a control input.

FIG. 1(C) is a basic block diagram of the phase shifter according to claim 3.

In the figure, the first resistive element 131 has one end grounded, the other end connected to the first output terminal, and also connected to the input terminal via the first capacitive element 133.

The second resistive element 135 has one end connected to the input terminal, the other end connected to the second output terminal, and is grounded via the second capacitive element 137.

Comparison circuit 139 compares the phases of two output signals output from the first output terminal and the second output terminal.

Overall, the first resistance element 131 and the second resistance element 1
35 is a variable resistance element, and the comparator circuit 13 is arranged so that the phase difference between the two output signals becomes a predetermined value.
9 to give a control input to this variable resistance element.

1#%’■尤朋.

FIG. 1(d) is a principle block diagram of a phase shifter according to a fourth aspect of the present invention.

In the figure, the variable capacitive element 145 has one end connected to the first output terminal and the first resistive element 141.
is connected to the first input terminal via the second resistive element 1, and the other end is connected to the second output terminal.
43 to the second input terminal.

The comparison circuit 147 compares the phases of two output signals output from the first output terminal and the second output terminal.

As a whole, an input signal having an inverted phase is supplied to each of the first input terminal and the second input terminal, and
The comparator circuit 147 is configured to provide a control input to the variable capacitive element 145 so that the phase difference between the two output signals becomes a predetermined value.

FIG. 1(e) is a block diagram of the principle of the phase shifter according to claim 5.

In the figure, a first resistive element 151 has one end connected to a first input terminal, the other end connected to a first output terminal, and also connected to one end of a capacitive element 155.

The second resistive element 153 has one end connected to the second input terminal, the other end connected to the second output terminal, and the other end of the capacitive element 155.

Comparison circuit 157 compares the phases of two output signals output from the first output terminal and the second output terminal.

As a whole, an input signal having an inverted phase is supplied to each of the first input terminal and the second input terminal, and at least one of the first resistance element 151 and the second resistance element 153 is a variable resistance element, The comparator circuit 157 is configured to provide a control input to this variable resistance element so that the phase difference between the two output signals becomes a predetermined value.

The multiplier circuit according to claim 6 controls the phase difference between the two output signals of the phase shifter according to claims 2 to 5 to 90', and determines the exclusive logic of these two output signals. It is configured to obtain a sum output.

[For production]

f) Engineering 1 In the RC phase circuit 111 in the phase shifter of claim 1, the phase difference between the input signal and the output signal is φ. Then, the ratio of the output signal level to the input signal level is the phase difference φ. It is a constant value determined by . This holds true regardless of the frequency value of the input signal. Therefore, the RC phase circuit 111 is configured to include a variable capacitance element or a variable resistance element, and as a control input for these elements, a comparison circuit 1 and 3 is used so that the level of the output signal is a constant ratio with respect to the input signal.
so that the output is fed back. Thereby, the amount of phase shift of the output signal of the phase shifter can be maintained constant even when the frequency of the input signal changes.

In the phase shifter according to claim 2, the input signal supplied to the input terminal and the output signal output from the first output terminal are:
The first resistive element 121 and the first capacitive element 123 have a predetermined phase difference determined by the first resistive element 121 and the first capacitive element 123.

Further, this input signal and the output signal output from the second output terminal have a predetermined phase difference determined by the second resistive element 125 and the second capacitive element 127.

By configuring at least one of these capacitive elements 123 and 127 as a variable capacitive element, and controlling the capacitance of this variable capacitive element according to the phase difference between the two output signals,
It becomes possible to maintain the phase difference between the two output signals constant despite changes in the frequency of the input signal.

iii. In the phase shifter according to claim 3, the input signal supplied to the input terminal and the output signal output from the first output terminal are:
The first resistive element 131 and the first capacitive element 133 have a predetermined phase difference determined by the first resistive element 131 and the first capacitive element 133.

Further, this input signal and the output signal output from the second output terminal have a predetermined phase difference determined by the second resistive element 135 and the second capacitive element 137.

By configuring at least one of these resistive elements 131 and 135 as a variable resistance element, and controlling the resistance value of this variable resistance element according to the phase difference between the two output signals, it is possible to respond to changes in the frequency of the input signal. It becomes possible to maintain a constant phase difference between the two output signals.

iv"; H in 14 In the phase shifter according to claim 4, the two output signals have a predetermined phase difference determined by the first resistance element 141, the second resistance element 143, and the variable capacitance element 145. .

This variable capacitive element 1
By controlling the capacitance of 45, it is possible to maintain the phase difference between the two output signals constant against changes in the input signals supplied to the first and second input terminals.

(1) In the phase shifter according to claim 5, the two output signals are transmitted through the first resistance element 151. It has a predetermined phase difference determined by the second resistive element 153 and the capacitive element 155.

By configuring at least one of these resistance elements 151 and 153 as a variable resistance element, and controlling the resistance value of this variable resistance element according to the phase difference between the two output signals, the first
And it becomes possible to maintain a constant phase difference between the two output signals with respect to frequency changes of the input signal supplied to the second input terminal.

vi”; 16. ■ In the multiplier circuit of claim 6, by calculating the exclusive OR of two output signals of the phase shifter with a phase difference of 90°, a multiplier output having twice the frequency of the input signal is obtained. get.

The phase shifter according to claims 2 to 5 always outputs two output signals having a phase difference of 90° due to changes in the frequency of the input signal. You can get borrowing power.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 2 shows the configuration of the RC phase circuit of the embodiment.

Further, FIG. 3 shows the configuration of a phase shifter that controls the control input of the RC phase circuit shown in FIG. 2 to obtain an output signal having a phase difference of 90°.

In FIG. 2, 211, 221 are resistors, 231.
Reference numeral 241 indicates a voltage-controlled variable capacitance capacitor. The resistance values of resistors 211 and 221 are respectively R,
, R, binding, and the capacitances of the variable capacitance capacitors 231 and 241 are respectively c and C2.

The input terminal to which the input signal Vin is supplied is grounded via the variable capacitor 231 and the resistor 211, and is also grounded via the resistor 221 and the variable capacitor 241. Further, a connection point between the resistor 211 and the variable capacitor 231 is connected to a first output terminal, and an output signal Vout+ is output from this output terminal. Furthermore, a resistor 221 and a variable capacitor 2
A connection point with 41 is connected to a second output terminal, and an output signal Voutt is output from this output terminal.

The circuit composed of the resistor 211 and the variable capacitance capacitor 231 is a low-pass filter type phase circuit, and the output signal Vo
utI is controlled so that its phase leads by 45° with respect to the input signal Vin. Further, the circuit constituted by the resistor 221 and the variable capacitance capacitor 241 is a high-pass filter type phase circuit, and the output signal VouL2 is controlled so that the phase lags the input signal Vin by 45 degrees. As a result, the phase difference between the output signals Vout and Voutz becomes 90'.

3, 311 is the RC phase circuit shown in FIG. 2, 321 is a peak detector, 331 is an error detector, and 341 is a coefficient multiplier.

The peak detector 321 is a circuit that detects the peak value of the output signal Vout, +, and its peak value Vop is input to one input terminal of the error detector 331.

Further, the coefficient unit 341 applies a coefficient 1/, ff to the input signal Vin.
The multiplication output is sent to the error detector 33.
It is input to the other input terminal of 1. The output signal of the error detector 331 is output from the variable capacitor capacitor 2 of the RC phase circuit 3]1.
31 and 241 as control inputs.

The operation of this embodiment phase shifter will be explained below. In other words, in order for the output signals Vout+ and Voutg to have a phase difference of 90°, the following relationship is required: R, 1/ωC2...plane Rz-1/ωC2...round. If this relationship is satisfied,
The output signal Voutl has a phase angle of 45° with respect to the input signal Vin, and at this time, the output amplitude of the output signal Vout is Vouti = 1, as is clear from equation (5).
(1+j)/21 ・Vin=Vin/JT”
...It becomes 0. The same applies to the output signal Voutz.

The phase difference between the output signals Vout and Voutz is set to 90° with respect to the change in the frequency of the input signal Vin, that is, the angular frequency ω.
In order to maintain this, it is sufficient to satisfy the above-mentioned side and equation 04), and to do so, it is sufficient to change the chiabassitances C8 and 02 with respect to changes in the angular frequency ω.

It can be known that 03) 2 and 0/8 formula hold true by 05) formula holding true.

Therefore, the peak value of the amplitude of the output signal Vout+ is detected by the peak detector 321, and this peak value and the coefficient
The error detector 331 compares the output signal Vin/ff of Even when the frequency changes, the phase difference between the output signals Voutl and Voutz is kept constant.

Further, FIG. 4 shows another example of the configuration of the phase shifter. In the figure,
Reference numeral 411 indicates a switching type phase detector, and reference numeral 421 indicates a loop filter.

The two input terminals of the switching type phase detector 411 receive the output signal Vout output from the RC phase circuit 311.
, , Vout, are supplied, respectively. The switching type phase detector 411 outputs a voltage value according to the phase difference between the two inputs. For example, when the phase difference is 90°, the output voltage is O(V), and a voltage value corresponding to the deviation of the phase difference from 90° is output. The loop filter 421 creates a control signal according to the output of the switching type phase detector 411 and supplies it to the RC phase circuit 311 as a control input.

Therefore, by controlling the control input of the RC phase circuit 311 according to the phase difference between the two output signals Vout, , Voutz, the two output signals Vout, , V
The phase difference of ou5 is maintained at 90°.

Note that various modifications can be made to the embodiments described above. In the above embodiment, the phase shift is performed via the input signal so that the phase difference between the two output signals is 90 degrees, but the phase difference is not limited to 90 degrees. The phase difference can also be changed to other values by changing the output level of the switching type phase detector 411.

Furthermore, in the above-described embodiment, two output signals are obtained, which are either leading or lagging in phase with respect to the input signal.
Of course, only one of the output signals may be obtained.

Figure 5 shows the above-mentioned phase shifter (as shown in Figures 3 and 4) in a phase variable circuit suitable for semiconductor integration that can vary the phase of the output signal in the range of 0° to 360°. FIG. 2 is a block diagram showing an example using the phase shifter shown in FIG. This type of variable phase circuit has been proposed in a patent application filed on September 19, 1986, entitled "Phase Circuit", the name of the invention of the present applicant. There is a problem in that the phase angle of the phase shifter changes due to the change, making it impossible to perform a phase shift in the range of 0° to 360°, but this problem can be solved by applying the phase shifter according to the present invention. This is something that can solve the problem.

In FIG. 5, 500 is a phase shifter according to the present invention having the same circuit configuration as shown in FIG. 3 or 4,
Two output signals of 0° phase and 90° phase are output with respect to the input signal. These two output signals are sent to a divider 511
and 521 respectively, thereby 0°, 90
A signal with a fixed phase angle of 180° is produced. These three signals are further combined with each other by subsequent combiners 531 to 591 while the signal amplitude is variably controlled by the control voltage Vcn, and the phase angle is thereby variably controlled according to the amplitude ratio at the time of combination. , an output signal varying in the range of 0° to 360° is finally obtained from the synthesizer 591.

- Mouth if No. 101 dish FIG. 6 shows another configuration of the RC phase circuit.

In FIG. 6, 611 and 621 indicate field effect transistors (FETs), and 631 and 641 indicate transistors, respectively. Let the chia pasitance of chia 631 and 641 be C, C2, respectively, and FET611 and 621
The resistance value between the drain and source of is Rds, ,
Let it be Rds2.

Generally, the drain-source resistance Rds can be expressed as follows.

However, in formula 00, Wg is the gate width, t and g are the gate lengths, vth is the threshold value of the FET, KO and α are element constants, and Vgs is the gate-source voltage.

By appropriately selecting the gate width Wg and gate length Lg and making the gate-source voltage Vgs variable, a voltage-controlled variable resistor having an arbitrary variable range can be realized.

Therefore, by making the control input (gate-source voltage Vgs) supplied to each gate of FET611, 621 variable, the above-mentioned side formula and 04 formula (resistance values R1, Rz) can be changed to the drain and source of FET611, 621, respectively. It becomes possible to maintain the phase difference between the two output signals Vout and Voutz at 90'' by satisfying the relationship between the two output signals Vout and Voutz.

Further, the phase shifter using this RC phase circuit and its application example are the same as those shown in FIGS. 3 to 5 described above, and the explanation thereof will be omitted.

101 dishes of ``Ichiro Luru Kaya'' FIG. 7 shows another configuration of the RC phase circuit.

In FIG. 7, 711 and 713 are field effect transistors (FETs), 721 is a chiabasita, and 731.73 is a field effect transistor (FET).
3 each indicates a signal source.

Chiapacitance 72] is set to C, and FET7
Let the resistance values between the drain, in, and 'north of 117i3 be Rds and lRds2, respectively. In addition, the signal source 731
, 733 output an input signal Vin whose phase is significantly inverted.

The 170 phase circuit shown in FIG. 7 is equivalent to the circuit shown in FIG.
becomes. 06) By changing the gate-source voltage Vgs as shown in the formula, FET711゜713
It is possible to control the resistance value between the drain and source of
Through this control, the equation 00) is satisfied.

, (1 Yamashi) 1 FIG. 8 shows another configuration of the RC phase circuit.

In FIG. 8, 741, 761, 763 represent field effect transistors (FETs), 743, 745. 791, 7
93 is a resistor, 751,753゜755 is a chiabacitor, 765,767.795゜797 is a constant current source, 7
Reference numeral 81 indicates a front drive circuit. FET74
The resistance value between the drain and source of 1 is Rds, and the resistor 74
Let the respective resistance values of 3,745 be R'x and Ra,
The chiavasitance of Chiabasita 751 is assumed to be C.

One output terminal of the predrive circuit 781 is connected to the gate terminal of the FET 761. In addition, the drain terminal of FET 761 is grounded, and the source terminal is constant current source 7
65.

On the other hand, the other output terminal (inverted output terminal) of the pre-drive circuit 781 is connected to the gate terminal of the FET 763.

In addition, the drain terminal of FET763 is grounded,
The source terminal is connected to a constant current source 767.

In addition, the source terminal of FET 761 is connected to resistor 743, F
It is connected to one end of the filter 751 via ET741 (between drain and source).

The source terminal of FET 763 is connected to the other end of capacitor 751 via resistor 745.

The supplied input signal Vin is amplified by the pre-drive circuit 781, and a signal having the same phase as the input signal Vin is sent to the FET 7.
A signal having an opposite phase to the gate terminal of FET 61 is supplied to the gate terminal of FET 763. As a result, signals whose phases are inverted to each other are supplied to one end of each of the resistors 743 and 745, and the function equivalent to that of the signal sources 731 and 733 shown in FIG. 7 can be achieved.

Also, Chiapacita 753. '755 is for removing the DC component, and these Kiabashita 753.75
5, only the alternating current component is extracted.

One end (output side) of the chia capacitor 753 is connected to a resistor 791.
Both are grounded via a constant current source 795 and connected to a constant current source 795. The level is set by this resistor 791 and constant current source 795, and the output signal Vou of an arbitrary level is set.
You can get L.

Similarly, one end (output side) of the capacitor 755 is grounded via a resistor 793 and a constant current source 797.
It is connected to the. This resistor 793 and constant current source 797
The output signal Voutz of any level can be obtained by setting the level by using the following.

Note that output signals Vout at the same level but with a phase difference of 90°,
and Voutt, resistors 791 and 793
make the resistance values of

The RC phase circuit shown in Fig. 8 is similar to the FET shown in Fig. 7.
711 to resistor 743. FET741, FET713
is replaced with resistor 745, and therefore 0
ω formula (resistance value R in 00 formula.

is the resistance value (R3+Rds), and the resistance value R2 is the resistance value R
4), it becomes possible to maintain the phase difference between the two output signals 'Voutr and Vout2 at 90°.

(LL 1st implementation FIG. 9 shows another configuration of the RC phase circuit.

In FIG. 9, 81L 813, 821, 823 indicate field effect transistors (FETs). Note that other symbols are the same as those used in FIG.

In the RC phase circuit shown in FIG. 8, the RC phase circuit shown in FIG.
．． Constant current source 765 to FET811゜821, FET7
63. Resistor 745. Constant current source 767 is connected to FET813.
823 respectively. The FET has a property that the mutual conductance gm changes depending on the current flowing between the drain and the source, and this mutual conductance gm is expressed as gm = 1/Rgs -07). Therefore, Rgs=1/gm -08).

FET8121 and 823 are for current control, and this FET
By controlling each gate voltage (voltage between gate 1 and source) of ET82], 823, FE"r"81],
It becomes possible to control the resistance value Rgs between each gate and source of 813.

Therefore, the resistance value Rds between each drain and source of FETs 711 and 713 in FIG.
Replace it with the resistance value Rgs between the gate and source of T811 and T813 so that the formula 00 is satisfied.

1j Yu”L rainbow nine theft example FIG. 10 shows another configuration of the RC phase circuit.

In FIG. 10, reference numeral 831 indicates a voltage-controlled variable capacitance converter, and reference numerals 841 and 843 indicate resistors.

The RC phase circuit shown in FIG. 10 is obtained by replacing the chia capacitor 935 in FIG. 14 with a variable capacitance chia capacitance 831, and by controlling the gear capacitance C of this variable capacitance chia capacitance 831, it satisfies the equation 00). do.

In addition, each of the above-mentioned figures 7 to 1 () (1, ′″
'The RC phase circuit shown can be applied to the phase shifters of FIGS. 3 to 5.

■ Next, a doubler circuit using the above-mentioned phase shifter will be explained.

FIG. 11(a) shows the configuration of the doubler circuit according to the embodiment of the present invention. In FIG. 11(a), 911 is 0 for the input signal.
This is a phase shifter that obtains two output signals with a phase difference of 90° and 90°. Further, 913 is an exclusive OR gate that calculates the exclusive OR of two inputs.

This phase shifter 911 has two output signals Vout+, Vout, and Vout in the phase shifter shown in FIG. 3 or 4.
The phase difference with respect to the input signal Vin is set to 0° and 90°. In addition, the RC phase circuit 31 in FIGS. 3 and 4
1 is R shown in each of Fig. 2 and Fig. 6 to Fig. 10.
Let us consider a C-phase circuit.

Further, FIG. 11(b) shows the signal states of each part of the doubling circuit shown in FIG. 11(a). In the figure, the "input signal" is supplied to the multiplier circuit 911 or the multiplier circuit 91
1 (for example, generated by the signal sources 731 and 733 in FIG. 7), the "signal A" is multiplied by the multiplication circuit
11 with a phase difference of 0°, "signal B" shows the output signal of the multiplier circuit 911 with a phase difference of 90°, and "2 output" shows the output signal of the exclusive OR gate 911. There is.

The phase shifter 911 supplies two output signals having a phase difference of 0° (signal A) and 90° (signal B) with respect to the input signal (clock signal) to the exclusive OR gate 913. The exclusive OR gate 913 calculates and outputs the exclusive OR of these two inputs. This output signal is shown in FIG.
), the frequency of the input signal is doubled, resulting in a double output.

This phase shifter 911 can always obtain two output signals with a phase difference of 0° and 90° regardless of the frequency change of the input signal. Therefore, it is possible to configure a doubling circuit that can follow changes in the frequency of the input signal.

〔Effect of the invention〕

According to the invention of claim 1, the frequency of the input signal is controlled by controlling the variable capacitance element or the variable resistance element in the RC phase circuit so that the level of the output signal is a constant ratio with respect to the input signal. It becomes possible to maintain the phase shift amount of the output signal of the phase shifter constant even when the phase shifter changes.

According to the invention of claims 2 and 3, among the two resistive elements and the two capacitive elements that determine the phase difference between the two output signals, at least one of the two capacitive elements is a variable capacitive element. or by configuring at least one of the two resistance elements as a variable resistance element and controlling the capacitance of the variable capacitance element or the resistance value of the variable resistance element according to the phase difference between the two output signals. , it becomes possible to maintain the phase shift amount of the output signal of the phase shifter constant even when the frequency of the input signal changes.

According to the invention of claims 4 and 5, among the two resistance elements and one capacitive element that determine the phase difference between the two output signals, at least one of the two resistance elements is constituted by a variable resistance element. Alternatively, the frequency of the input signal can be adjusted by configuring the capacitive element as a variable capacitive element and controlling the capacitance of the variable capacitive element or the resistance value of the variable resistive element according to the phase difference between the two output signals. It becomes possible to maintain the phase shift amount of the output signal of the phase shifter constant even when the phase shifter changes.

According to the invention of claim 6, two output signals having a phase difference of 90° are output from the phase shifter of claims 2 to 5, and the exclusive OR of these two output signals is obtained. Accordingly, it is possible to realize a multiplier circuit that can easily follow changes in the frequency of an input signal.

[Brief explanation of the drawing]

Fig. 1 is a principle block diagram of a phase shifter and multiplier circuit of the present invention. Fig. 2 is a block diagram of an RC phase circuit according to an embodiment of the present invention. Fig. 3 is a block diagram of a phase shifter of an embodiment. , Fig. 4 is a block diagram of the phase shifter of the embodiment, Fig. 5 is a block diagram of the O'-360° phase variable circuit to which the phase shifter of the embodiment is applied, and Fig. 6 is the RC phase circuit of the embodiment. Fig. 7 is a block diagram of the RC phase circuit of the embodiment, Fig. 8 is a block diagram of the RC phase circuit of the embodiment, Fig. 9 is a block diagram of the RC phase circuit of the embodiment, and Fig. 10 is a block diagram of the RC phase circuit of the embodiment. A configuration diagram of the RC phase circuit of the embodiment, FIG. 11 is an explanatory diagram of the multiplier circuit of the embodiment, FIG. 12 is an explanatory diagram of the conventional example, FIG. 13 is an explanatory diagram of the conventional example, and FIG. 14 is an explanatory diagram of the conventional example. FIG. 15 is an explanatory diagram of a conventional example, and FIG. 16 is an explanatory diagram of a conventional example. In the figure, 111 is an RC phase circuit, 113.129, 139, 147, 157 are comparison circuits, 121.125, 131, 135, 141, 143.1
51 and 153 are resistive elements, and 123, 127, 133, 137, 145, and 155 are capacitive elements. (a) A1 (d 1 1 bow 1 (e) Figure 3 to the spirit of child benefit O1 To the top of the cup 4th figure (shi) (C) A thousand tamame principle 7゛077 Figure 1 Figure 111v) Tachibume [ro-en 57. ir diagram Figure 10 (l:l) September diagram of the unexpected and phantom L world S Figure 11 q is 315 Iku'J explanation Shimajiguchi Tsukiba] Figure 13 Follow! Figure 14 of the example of the forest shrine.

Claims (6)

[Claims] (1) An RC phase circuit (111) including a variable capacitance element or a variable resistance element, and an input signal and an output signal of the RC phase circuit (111) are input and the input signal and output signal are a comparison circuit (113) for comparison; the comparison circuit (113) applies a control input to the RC phase circuit (111) so that the level of the output signal is at a predetermined ratio with respect to the level of the input signal. A phase shifter characterized in that it is configured to give. (2) One end is connected to the input terminal, the other end is connected to the first output terminal, and the first resistance element (121
) a first capacitive element (123) that is grounded via
and a second capacitive element (127) whose one end is grounded and whose other end is connected to the second output terminal and connected to the input terminal via the second resistive element (125). and a comparison circuit (129) that compares the phases of two output signals output from the first output terminal and the second output terminal.
), at least one of the first capacitive element (123) and the second capacitive element (127) is a variable capacitive element, and the phase difference between the two output signals is a predetermined value. A phase shifter characterized in that the comparator circuit (129) is configured to provide a control input to the variable capacitive element so that the comparator circuit (129) provides a control input to the variable capacitive element. (3) A first resistive element (131) whose one end is grounded and whose other end is connected to the first output terminal and to the input terminal via the first capacitive element (133).
and a second capacitive element (137) with one end connected to the input terminal and the other end connected to the second output terminal.
), and a comparator circuit (139) that compares the phases of two output signals output from the first output terminal and the second output terminal.
), at least one of the first resistance element (131) and the second resistance element (135) is a variable resistance element, and the phase difference between the two output signals is a predetermined value. A phase shifter characterized in that the comparator circuit (139) is configured to provide a control input to the variable resistance element. (4) One end is connected to the first output terminal and the first input terminal via the first resistance element (141), and the other end is connected to the second output terminal. a variable capacitance element (145) connected to the second input terminal via the second resistance element (143); Comparator circuit (147) that compares the phases of two output signals
), supplying an input signal with an inverted phase to each of the first input terminal and the second input terminal, and supplying the input signal with an inverted phase to each of the first input terminal and the second input terminal, and supplying the input signal such that the phase difference between the two output signals becomes a predetermined value. From the comparison circuit (147) to the variable capacitive element (145)
A phase shifter configured to provide a control input to the phase shifter. (5) One end is connected to the first input terminal, the other end is connected to the first output terminal, and a capacitive element (15
5) is connected to one end of the first resistance element (151
), one end is connected to the second input terminal, the other end is connected to the second output terminal, and the capacitive element (155
) a second resistance element (153) connected to the other end of the
and a comparison circuit (157) that compares the phases of two output signals output from the first output terminal and the second output terminal.
), and supplies an input signal with an inverted phase to each of the first input terminal and the second input terminal, and supplies the first resistive element (151) and the second resistive element ( 1
53) is a variable resistance element, and the comparison circuit (157) is configured to give a control input to the variable resistance element so that the phase difference between the two output signals becomes a predetermined value. phase shifter. (6) The phase shifter according to claims 2 to 5 is characterized in that the phase difference between the two output signals of the phase shifter is controlled to 90°, and the exclusive OR output of these two output signals is obtained. Double circuit.