JPH02288728A - Output buffer - Google Patents

Abstract

PURPOSE:To block a short-circuit current from other IC connecting to a different power supply independently of ON/OFF of the power supply by providing a diode between a drain and an output terminal of an output P-channel MOS transistor(TR). CONSTITUTION:The output buffer consists of an output P-channel MOS TR 1 whose drain connects to the anode of a diode 3, an output N-channel MOS TR 2 whose source connects to GND and whose drain connects to a cathode of the diode 3 and an output terminal, and a control circuit 4 generating a signal applied to gates of the output MOS TRs 1, 2 with the input data and the control signal. A substrate 24 is a P-channel semiconductor, an anode region 19 is a P-channel semiconductor and a cathode region is an N-channel semiconductor. Thus, the anode region 19 and the cathode region 20, and the substrate 24 and the cathode region 20 are reverse-biased and no current flows between them respectively.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an output buffer used in an IC, and in particular, to an output buffer used in an IC.
Regarding state output buffer.

[Conventional technology]

Conventionally, this type of buffer includes an output PCh MOS transistor 1 and an output Nch MOS transistor 1, as shown in FIG.
OS) Each drain of transistor 2 was directly connected, and the output cuff was extended from the connection point.

[Problem to be solved by the invention]

The conventional 3-state output buffer described above may be connected in parallel with other buffers mounted on different devices, and in this case, the power supply of the other device (IC) is ONL, and this IC
The case may be that the power is OFF. A short-circuit current flows through the signal line from the Pch transistor of the IC that is powered on to the Pch transistor of the IC that is powered off, and this has the disadvantage that the potential of the signal line becomes unstable. There is.

This will be explained using the sectional view of FIG. source area 1
7. The drain region 18, well 16, and gate 14 are
It is assumed that the source region 34, drain region 33, well 30, and gate 31 are Pch MO8) transistors on different ICs. Further, a constant voltage is applied to the power supply wiring 35, and no power is applied to the power supply wiring 10, which is connected to GND.
Assume that it is at the same potential as When a low potential is applied to the gate 31 here, conduction occurs between the source region 34 and the drain region 33, and the aluminum wiring 32, the output signal line 36, and the aluminum wiring 11 have almost the same potential as the power supply wiring 35. Phc
Since it is a transistor (MOS), the drain region 15 is a P-type semiconductor, and the well 16 is an N-type semiconductor, and since the power supply wiring 10 is at the GND potential, the well 16
is also at GND potential. Therefore, a forward bias is applied to the PN junction between the drain region 18 and the well 16, and a large current flows.

[Means to solve the problem]

The output buffer according to the present invention has a diode provided between the drain of the output Pch transistor and the output terminal. In this way, short circuit current can be prevented regardless of whether the power is on or off.

〔Example〕

The details will be explained below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which an output PchMO3) transistor 1 whose source is connected to the power supply and whose drain is connected to the 7th node side of the diode 3, and whose source is connected to GND.
An output Nch MOS transistor 2 whose drain is connected to the cathode of the diode 3 and the output terminal, and an output MOS transistor 2 whose drain is connected to the cathode of the diode 3 and the output terminal
) A control circuit 4 generates a signal to be applied to the gates of transistors 1 and 2.

FIG. 2 is a sectional view of the output section of FIG. 1. Well 16.
The source region 17, the drain region 18, and the gate region 14 are the first
It constitutes the output PchMOS transistor in the figure. Well 23, source region 22, drain region 21
．． The gate 15 constitutes an output Nch MOS transistor. 7 node region 19 and cathode region 20 constitute diode 3.

In this embodiment, a P-type substrate is assumed, and the substrate is maintained at the GND potential by the surface terminal 25. When the power is turned off, the power terminal 5 and the power wiring 10 are at the GND potential. For this reason, well 16
, source region 17, drain region 18, wiring 11 . All of the anode regions 19 are at the GND potential. Here, when a voltage is applied to the output terminal 7 from the outside, the output terminal 7 and the wiring 1
2. The cathode regions 20 are all at the same potential and are higher than GND. In this embodiment, since a P-type substrate is considered, the substrate 24 is P-type, and the anode region 1 is
9 is a P-type semiconductor, and the cathode region is an N-type semiconductor. Therefore, between the 7-node region 19 and the cathode region 20 and between the substrate 24 and the cathode region 20, both are reverse biased and no current flows.

FIG. 3 shows a second embodiment of the invention. Instead of using the diode 3 in FIG. 1, this embodiment uses an Nch
This is an example in which a diode is constructed using a MOS transistor.

FIG. 4 is a sectional view of FIG. 3. The well 30, source region 27, drain region 28, and gate 29 constitute a Pch MOS transistor 26 in FIG.

By shorting the well 30 and the drain 28 and the gate 29 and the source 27, the PN junction between the source region 27 and the well is used as a diode.

〔Effect of the invention〕

As described above, the present invention provides a diode between the drain of the output Pch MO8) transistor and the output terminal to turn on the power.

Other ICs connected to different power sources regardless of whether they are OFF or not
This has the effect of preventing short-circuit current from flowing.

[Brief explanation of drawings]

Fig. 1 is a diagram of the first embodiment of the present invention, Fig. 2 is a sectional view of the first embodiment, Fig. 3 is a diagram of the second embodiment, and Fig. 4 is a sectional view of the second embodiment. , FIG. 5 is a conventional example, and FIG. 6 is a sectional view of the conventional example. 1... Output Pch) transistor, 2...
... Output Nch) transistor, 3... Diode, 4... Control circuit, 5... Power supply terminal, 6... GND terminal terminal. ...Output terminal, 8...Data input terminal, 9...
・Control signal input terminal, 10.35...Power supply wiring, 11.12.32...Wiring, 13...
・GND wiring, 14. 15, 29. 31...
Gate, 16.30...N type well, 17,
27.34...P-type source region, 18,28.
33...P-type drain region, 19...
Anode region, 20...Cathode region, 21.
...N type drain region, 22...N type source region, 23...P type well, 24...
・・P type breast straight, 25・・・・Back terminal,
26...PchMO3) transistor, 36...
····Signal line. Agent Patent Attorney Susumu UchiharaFigure 2Figure 4Figure 1Figure 3Figure 5Figure 6

Claims (1)

[Claims] A three-state output buffer whose output can take three states: low level, high level, and high impedance, characterized in that a diode is provided between one of the output transistors and the output terminal 2. output buffer.