JPH02288582A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To adjust the timing between a luminance signal and a chrominance signal by controlling a difference a write address and a readout address for a luminance signal memory and a chrominance signal memory. CONSTITUTION:The circuit is provided with a horizontal synchronizing signal separator circuit 31, an FIFO memory 34 for 1H length for luminance signal, an FIFO memory 35 for 1H for chrominance signal, a write system control signal generating circuit 36 controlling the two FIFO memories and a read system control signal generating circuit 37 controlling the two FIFO memories. The write address and read address of the memory are controlled to give a difference between the time from the write to readout in the 1st memory and to the time from the write to readout in the 2nd memory thereby adjusting the delay time between the luminance signal and the chrominance signal. Thus, the timing between the signals is adjusted and the existing memory is used, thin the circuit is realized without deteriorating the signal characteristic with low cost.

Description

[Detailed Description of the Invention] Industrial Application Field The present invention relates to a video tape recorder (hereinafter referred to as VTR).
The present invention relates to a video signal processing circuit that corrects the processing time of luminance signals and color signals that can be used for applications such as the following.

2. Description of the Related Art In recent years, with the development of memory technology, many VTRs with digital functions such as multi-screen, NR (noise reducer), and TBC (time pace corrector) have been released by various companies.

The video reproduction system of the VTR will be explained with reference to the drawings.

FIG. 4 is a block diagram of a reproduction system circuit of the VTR.

In FIG. 4, 61 is a video head, 62 is a reproduction preamplifier that amplifies the signal output from the head, 63 is an HPF that separates a luminance signal from the output of the reproduction preamplifier, and 6
5 is an FM demodulator, and 67 is an L that blocks the FM carrier frequency component.
PF, 64 is an LPF that separates the color signal from the output of the reproduction preamplifier, as is a frequency converter that converts the frequency to a high frequency band, 68 is a BPF, e9 is a digital signal processing circuit, 7
゜ is a delay circuit using an LPF.

First, the output of the head 61 is amplified by the reproduction preamplifier 62. Next, the HPF 63 and LPF 64 separate the signal into a luminance signal and a color signal. The luminance signal is then FM demodulated by the FM demodulator θ6, and the color signal is FM demodulated by the frequency converter 6.
6 converts it to a high frequency range. At this time, since the processing time for the chrominance signal system is longer than that for the luminance signal system, the chrominance signal lags behind the luminance signal.

The signal is processed by a digital signal processing circuit 69 such as NR ('TBC). At this time, the color signal is demodulated by color difference and separated into an RY signal and a BY signal before being A/D converted. The chrominance signals are mixed by a multiplexer.Due to this chrominance demodulation, the chrominance signals further lag behind the luminance signals.

In order to synchronize the timing of the luminance signal and color signal, conventionally, an LP constructed of LC is used as a delay circuit in the luminance signal system.
Fyo is used.

Problems to be Solved by the Invention However, with the above-mentioned delay circuit, there is a problem that it takes time to design a filter with a desired delay time, and that if the delay time is increased, the signal characteristics deteriorate. I had a problem.

In view of the above problems, the present invention provides a video signal processing circuit that adjusts the timing between signals by controlling the write address and read address of the memory of an existing digital signal processing circuit.

Means for Solving the Problems In order to solve the above problems, a video signal processing circuit of the present invention includes a first memory for storing a luminance signal and a second memory for storing a color signal. By controlling the write address and read address of the memory υ, by creating a difference between the time from writing to the first memory to reading it and the time from writing to the second memory to reading it, the brightness signal and It is equipped with a memory control circuit that can adjust the delay time of color signals.

Operation According to the present invention, the timing of the luminance signal and the color signal can be matched by controlling the difference between the write address and the read address of the luminance signal memory and the color signal memory with the above-described configuration.

Since the timing adjustment process is performed by a memory control circuit which is a digital circuit, the timing between signals can be easily adjusted.

Further, since the configuration uses an existing memory without providing a special delay circuit, signal characteristics do not deteriorate and it can be realized at low cost.

EXAMPLES Hereinafter, examples of the present invention will be described with reference to the drawings. A video signal reproduction system of a VTR equipped with a TBC function will be explained.

FIG. 1 is a block diagram of the recycled silk circuit of the VTR according to the embodiment of the present invention.

In FIG. 1, 11 is a video head, 12 is a reproduction preamplifier that amplifies the signal output from the 'head, and 13 is an HPF that separates a luminance signal from the output of the reproduction preamplifier.
15 is an FM demodulator, 17 is an LPF that blocks the FM carrier frequency component, and 14 is an LPF that separates the color signal from the output of the pre-reproduction amplifier.

16 is a frequency converter that converts the frequency to a high frequency band, 18 is B
PF, 1g is a digital signal processing circuit.

The digital signal processing circuit performs TBC processing using a line memory (hereinafter referred to as a 1H long line memory) capable of storing data for horizontal scanning lines, as well as processing of luminance signals and color signals provided by the present invention. This circuit performs video signal processing to match timing.

The digital signal processing and logic circuit 19 will be described below, except for the former TBC processing, and the latter video signal processing that matches the timing of the luminance signal and color signal.

FIG. 2 is a block diagram of the digital signal processing circuit 19. In FIG. 2, 31 is a horizontal synchronization signal separation circuit that separates a horizontal synchronization signal from a luminance signal, and 32 is a luminance signal A.
33 is an A/D converter for color signals, 34 is a 1H long FIFO memory for luminance signals, 36 is a 1H long FIFO memory for color signals, and 36 is a light system control that controls the two FIFO memories. Signal generation circuit, 37 is two FIFOs
A read system control signal generation circuit for controlling the memory, 38 a D/A converter for luminance signals, 39 a D/A converter for color signals,
40 is a clock generator.

The operation of the digital signal processing circuit configured as described above will be explained below with reference to FIGS. 2 and 3.

FIG. 3 is a timing chart showing the signal waveforms of each part in FIG.
) is the write reset pulse WR for both FIFO memories.
3T, (d) and (e) are FIFO for luminance signal
Memory read reset pulse YRR3T and color signal F
The read reset pulse number CRR5T of the IFO system is used, and (f) and (q) correspond to the luminance signal YOUT output from the digital signal processing circuit and the color signal number cOUT. Assume that a luminance signal YIN and a chrominance signal CIN whose timings are shifted as shown in (a) and (b) are input to a digital signal processing circuit. In this case, the color signal is more Δ than the luminance signal.
It is delayed by t.

First, YIN and C are connected to A/D converters 32 and 33.
/ D converted.

Next, use the write reseller (WR3T) synchronized with the horizontal synchronization signal HSYNC generated by the write system control signal generation circuit 36 to write FIFo memo for Y! FIF for J34 and C
Initialize the write address of O memory 36 at the same time,
The above A/D converted signals are written into each of the four FIFO memory arrays.

Then, in synchronization with the horizontal synchronizing signal H3YNC generated by the read system control signal generation circuit 37, the Y-reset pulse YRR3 is delayed by an arbitrary time from the WR3T pulse.
T(d),! :C lease set pulse CRR3T(e
) to initialize the read addresses of the Y FIFO memory and C FIFO memory, and read data from each FIFO memory. Here, change the YRR3T pulse to CRR3T
By generating the signal at a timing that is delayed by Δt from the pulse, the Y signal lags the C signal by Δt.
Luminance signal YouUT D/A converted by converter 39.39
(f) and the color signal C0UT ((1) have the same timing.

YRR8T parnu and CRR for read system control signal generation circuit
By providing an offset value input for adjusting the timing relationship of the 3T pulse, the timing of the luminance signal and color signal can be easily adjusted.

Therefore, when various signal processing is combined, the delay time between the Y signal and the C signal differs depending on the combination.
In the case of this embodiment, the timing can be easily adjusted simply by changing the offset value.

In this example, the timing of the luminance signal and the color signal was matched by making the write reset for the luminance signal and the color signal the same, and staggering the read reset for the luminance signal and the color signal. It is also possible to have a configuration in which the timings are made the same and the write resets of the luminance signal and color signal are shifted to match the timing.

Further, in this embodiment, a FIFO memory is used, but it is also possible to use a general-purpose memory. In this case, the configuration is such that a write address and a read address are input to the memory from the memory control circuit.

Effects of the Invention As described above, according to the present invention, the timing of the luminance signal and the color signal can be easily adjusted.

In addition, since it is configured with a special delay circuit and uses existing memory, the signal characteristics will not deteriorate.
Moreover, it can be realized at low cost.

[Brief explanation of the drawing]

FIG. 1 shows a TBC as a digital function of an embodiment of the present invention.
A block diagram of a video signal reproduction system of a VTR equipped with functions,
2 is a block diagram showing details of the digital signal processing circuit 19 in FIG. 1, FIG. 3 is a timing waveform diagram in FIG. 2,
FIG. 4 is a block diagram of a video signal reproduction system of a conventional VTR with a digital recording function. 11...Head, 12...Reproduction preamplifier, 13...HPF, 14...LP
F, 15...FM demodulator, 1e...Frequency converter, 17...LPF118...
・BPF, 19...Digital signal processing circuit,
31...Horizontal synchronization signal separation circuit, 32...
・・A/D converter for luminance signal, 33・! ...A/D converter for color signal, 34...1H length F for luminance signal
IFO memory, 35...1H long FIF for color signal
O memory, 36...Write system control signal generation circuit, 37.Read system control signal generation circuit, 38...
... D/A converter for luminance signal, 39 ... D/A converter for color signal, 40 ... Clock generation circuit.

Claims (2)

[Claims] (1) A video signal processing circuit that includes a first memory that stores a luminance signal and a second memory that stores a color signal, the circuit controlling the write address and read address of the memory so that the first memory An image characterized by being equipped with a memory control circuit that adjusts the delay time of a luminance signal and a color signal by creating a difference between the time from writing to the second memory to reading it and the time from writing to the second memory until reading from the second memory. signal processing circuit. (2) The video signal processing circuit according to claim 1, wherein the time difference can be freely set within the range of the memory by the memory control circuit.