JPH02288466A - Picture processing system - Google Patents

Abstract

PURPOSE:To attain the change in the size of a picture data and the addition of the data by controlling stored picture information so that it is subjected to access processing and displayed, thereby monitoring a printed-out picture data. CONSTITUTION:Picture information stored in storage means 102-104 to process the picture information is accessed by a direct memory access means 106, a processing means 109 processes the information and a control means 101 is provided, which controls the display of the information on a display means 110. Thus, before the processed picture is recorded, it is monitored at high speed and confirmed and the change in the size or the data addition is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a system for printing out a read image in multiple colors, and particularly relates to a technique for reading and monitoring images in color.

[Conventional technology]

In conventional copying machines and facsimiles, scanned images are directly printed out.

[Problem that the invention is trying to solve]

However, in the conventional example above, it is not possible to monitor the image data that is printed, so if you want to understand and utilize the information by changing the size of the image data, adding or overwriting separately stored data, The only way to do this is to use the actual printed results (which took a lot of effort).

[Means and operations for solving the problem] According to the present invention, in an image processing system that reads image information and outputs the image on a recording medium, there is provided a reading means for reading image information, and an image information read by the reading means. A storage means for storing image information, a display means for displaying image information, a direct memory access means, a processing means for processing the image information, and an image information stored in the storage means is accessed by the direct memory access means. and a control means for controlling the processed image to be processed by the processing means and displayed on the display means, the read image to be recorded is processed and the processed image is processed at high speed before being recorded. It was possible to monitor and confirm the results.

〔Example〕

FIG. 1 is a system configuration diagram of the present invention.

This system consists of boards with various functions using a system bus. CPU board CPUB1
01 connects all boards 102 to 108 to the system bus 11
It is controlled via 1.

Page memories PMR102, PMG103. PMB10
4 is an image buffer for one page corresponding to each color of red, green, and blue, and is connected to the scanner/printer system SCA/PR11 via the scanner/printer interface SPI/F105.
Connected to 09.

DMAC, a direct memory access controller
106 is the page memory PMR102, PMG10
3. Data is read from the PMB 104, transferred and written to the FM/DA board 107, which is a frame memory for monitoring. The FM/DA board 107 is
It has an A conversion circuit and displays images on the monitor 110.

The communication circuit 108 is a page page memory PMR102゜P.
MG103. PMB] Read the image data from 04,
It is possible to transmit images to another system that is the same as this system or to another system.

Next, an example of the configuration of the scanner/printer SCA/PR 1109 is shown in FIG. As shown in the figure, the apparatus shown in FIG. 2 has a digital color image reading device (hereinafter referred to as a color scanner) 1 at the top and a digital color image printing device (hereinafter referred to as a color printer) 2 at the bottom. This color scanner 1 reads color image information of a document for each color using color separation means and a photoelectric conversion element such as a CCD, and converts it into an electrical digital image signal. Further, the color printer 2 is an electrophotographic laser beam color printer that reproduces a color image in each color according to the digital image signal, and records the image by transferring it to recording paper multiple times in the form of digital dots.

First, an overview of the color scanner I will be explained.

3 is a document, 4 is a platen glass on which the document is placed, and 5 is a rod array for condensing the reflected light image from the document exposed and scanned by the halogen exposure lamp IO and inputting the image to the 1-magnification full color sensor 6. 5.6.7.
10 are integrated as a document scanning unit 11 as indicated by arrow A.
Exposure scan in the I force direction. The color separation image signal read line by line without exposure scanning is amplified to a predetermined voltage by the sensor output signal amplification circuit 7 and then sent to the signal line 5.
01, the signal is input to the video processing unit 12 and subjected to signal processing. 501 is a coaxial cable for ensuring faithful transmission of signals. A signal 502 is a signal line that supplies drive pulses for the same-magnification full-color sensor 6, and all necessary drive pulses are generated within the video processing unit 12.

8 and 9 are white plates and black plates for white level correction and black level correction of image signals, which will be described later, and by irradiating them with a halogen exposure lamp 10, signal levels of predetermined densities can be obtained, respectively, and the video signal Used for white level correction and black level correction. 13 is a control unit having a microcomputer, which uses a bus 508 to display on the operation panel 20, control keys manually, control the video processing unit 12, position sensor Sll,
In step S21, the position of the document scanning unit 11 is set to the signal line 50.
Further, the signal line 503 controls the stepping motor drive circuit that pulse-drives the stepping motor 14 for moving the scanning body 11, and the signal line 504 controls the 0N10FF of the halogen exposure lamp lO by the exposure lamp driver. It performs all controls of the color scanner unit l, such as control, light amount control, and control of the digitizer 16, internal keys, and display unit via the signal line 505. The color image signal read by the above-mentioned exposure scanning unit 11 during original exposure scanning is input to the video processing unit 12 via the amplification circuit 7 and the signal line 501, and is subjected to various processing described later in this unit 12. and sent to the printer section 2 via the interface circuit 56.

Next, an outline of the color printer 2 will be explained. 711 is a scanner, a laser output unit that converts the image signal from the color scanner unit 1 into an optical signal, and a polyhedron (for example, an octahedron).
polygon mirror 712, a motor (not shown) for rotating this mirror 712, and an f/θ lens (imaging lens)
713 etc. 714 is a reflecting mirror that changes the optical path of the laser beam, and 715 is a photosensitive drum. The laser beam emitted from the laser output section is reflected by a polygon mirror 712, passes through a lens 713 and a mirror 714, and linearly scans (raster scan) the surface of a photosensitive drum 715, forming a latent image corresponding to the original image. .

In addition, 717 is a primary charger, 718 is a full exposure lamp,
723 is a cleaner section that collects residual toner that has not been transferred; 724 is a pre-transfer charger; these members are arranged around the photosensitive drum 715.

7264:! It is a developing unit that develops an electrostatic latent image formed on the surface of the photosensitive drum 715 by laser exposure, and 731Y, 731M, 731C, and 731Bk are developing sleeves that directly develop the image in contact with the photosensitive drum 715.
730Y, 730M, 730C, and 730Bk are toner hoppers that hold spare toner; 732 is a screw that transports the developer; and these sleeves 731
Y~731Bk,) Napopper730Y~7308
and screw 732 to developer unit 726.
These members are connected to the rotation axis P of the developing unit.
are arranged around the. For example, when forming a yellow toner image, yellow toner development is performed at the position shown in this figure, and when forming a magenta toner image, the developing unit 726 is rotated around the axis P in the figure and exposed to light. A developing sleeve 731M in the magenta developing device is placed in contact with the body 715.
be arranged. Cyan and black development operate in the same way.

Further, 716 is a transfer drum that transfers the toner image formed on the photosensitive drum 715 onto paper, 719 is an actuator plate for detecting the moving position of the transfer drum 716, and 720 is a drum that is in close proximity to this actuator plate 719. A position sensor detects when the transfer drum 716 has moved to the home position, 7 and 25 are a transfer drum cleaner, 727 is a paper press roller, 728 is a static eliminator, and 729 is a transfer charger.
19.720.725.727°729 is transfer roller 7
It is arranged around 16.

On the other hand, 735,736. 737. is a paper feed cassette that stores paper (paper sheets). 738 is a cassette 735.73
Paper feed rollers that feed paper from 6, 739, 740, 7
Reference numeral 41 denotes a timing roller that takes the timing of paper feeding and conveyance, and the paper fed and conveyed via these is guided by a paper guide 749 and wrapped around the transfer drum 716 while its leading edge is carried by a gripper to be described later, forming an image. Shift to the formation process.

Further, 550 is a drum rotation motor, which rotates the photosensitive drum 715.
and the transfer drum 716 are rotated synchronously. 750 is a peeling claw that removes the paper from the transfer drum 716 after the image forming process is completed, 742 is a conveyor belt that conveys the removed paper, and 743 is an image fixing unit that fixes the paper that has been conveyed by the conveyor belt 742. The image fixing section 743 has a pair of heat pressure rollers 744 and 745.

Next, according to FIG. 3, control section 1 of the scanner section
3 will be explained.

The control unit is a microcomputer, CPU2.
2, including a lamp driver 21.2 for video signal processing control, exposure and scanning. Stepping motor driver 15, digitizer 16, and operation panel 20 are controlled through signal lines 508 (bus), 504, 503, 505, etc., respectively, to obtain a desired copy (program ROM 23.
RAM24. It is controlled organically according to RAM25. R
The non-volatility of AM25 is ensured by the battery 31.

505 is a commonly used signal line for serial communication.
The operator inputs information from the digitizer 16 according to a protocol between the PU 22 and the digitizer 16. That is, 505 is a signal line for inputting coordinates, area instructions, copy mode instructions, magnification ratio instructions, etc. when editing a document, for example, moving or compositing.

A signal line 503 is a signal line through which the CPU 22 instructs the motor driver 15 about scanning speed, distance, forward movement, backward movement, etc., and the motor driver 15 inputs predetermined pulses to the stepping motor 14 according to instructions from the CPU 22. and gives motor rotational action. Serial 1/F29,30
is a general circuit realized by a serial I/F LS1 such as Intel Corporation 8251, and the digitizer 16 and motor driver 15 also have similar circuits, although not shown.

Further, Sll and S21 are sensors for detecting the position of the original exposure scanning unit (FIG. 11), and S11 is the home position, at which white level correction of the image signal is performed. S21 is a sensor that detects the presence of the original exposure scanning unit at the leading edge of the image, and this position becomes the reference position of the original.

Signals ITOP, BD, VCLK, VID in Figure 2
E.O.

H3YNC and SRCOM (511 to 516) are signals for the interface between the color printer section 2 and the scanner section l shown in FIG. 1, respectively. The image signal VIDEO 514 read by the scanner section 1 is all sent to the color printer section 2 based on the above signals. ITOP is a synchronization signal in the image feed direction (sub-scanning direction), and is sent once for each screen, that is, 4 colors (yellow, magenta, cyan,
This occurs four times in total, once for each image (black), and
This is done so that when the leading edge of the transfer paper wrapped around the transfer drum 716 of the color printer section 2 receives a toner image transferred at the contact point with the photosensitive drum 715, the position of the leading edge of the transfer paper matches the image of the original. Drum 716, photosensitive drum 7
15, is sent to the video processing unit 12 in the scanner section l, and is further input as an interrupt to the CPU 22 in the controller 13 (signal 511).

The CPU 22 performs image control in the sub-scanning direction for editing and the like based on the ITOP interrupt. BD512 is a synchronization signal in the raster scan direction (main scanning direction) that is generated once per rotation of the polygon mirror 712, that is, once per raster scan. The data is sent line by line to the printer unit 2 in synchronization with the BD. VCLK 513 is a synchronous clock for sending an 8-bit digital video signal 514 to the color printer section 2, and sends out the video data 514 via a flip-flop circuit. H3YNC515 is a main scanning direction synchronization signal generated from the BD signal 512 in synchronization with VCLK513, and has the same period as the BD.
Strictly speaking, the VIDEO signal 514 is sent out in synchronization with the H3YNC 515. This is because the BD signal 515 is generated in synchronization with the rotation of the polygon mirror, so the polygon mirror 7
Contains a lot of jitter from the motor that rotates the BD
This is because if the double signal is synchronized as it is, jitter will occur in the image, so H3YNC515, which is generated based on the BD double signal in synchronization with VCLK without jitter, is required. S
ROOM is a signal line for half-duplex bidirectional serial communication, and carries instructions from the scanner unit l to the printer unit 2, such as color mode, cassette selection, etc., and status information of the printer unit, such as jam, no paper, etc. All information such as weights is exchanged via this communication line SROOM.

(Input of Image Data) The SCA/PR 1109, which is composed of the scanner section 1 and the printer section 2 as described above, is connected to the SP I/F 105 that is its interface. S
When the PI/F 105 receives an instruction to read an image from the CPU board CPUBIOI via the system bus lil, it activates the SCA/PR 1109 and reads the image.

The SCA/PR1109 is a frame-sequential scanner/printer, and each color component R, G, and B is input and output one page at a time.

The scanner/printer interface SPI/F 105, which has received the instruction to read the image, becomes a path master and transfers the image data directly to the high-speed bus 112 in real time.
Output to. At this time, the CPU board CPUBIOI waits for an interrupt, and the page memories PMR102, PMG103, . A signal (memory selection signal) specifying which board of the PMB 104 is to be accessed is transmitted through the scanner/printer interface SPI/
Supplied from F105. Page memory PMR102,
PMG103. Each PMB 104 determines whether the board number specified by the memory selection signal matches its own board number, and writes one page of the image data on the high-speed bus 112 into the memory only if they match. In this way, scanner/printer SCA/PR
1109 3 colors (R.

In accordance with the image data output of G, B), the corresponding page memories PMR102, PMG103. The PMB 104 sequentially reads images on the high-speed bus 112. Also, the scanner
Printer SCA/PR1109 prints image data for 3 colors (R
, G, and B) at the same time, by expanding the data bus width of the system bus 111, three page memories PMR102°PMG can be input and output in one scan
103. It can be written to PMB104.

When data is written to all page memories, the scanner/printer interface SPI/F 105 generates an interwoven signal to the high speed bus 112 and transfers control to the CPU.
Board CPUB101i:: Pass.

(Image display function) The DMA controller DMAC107 has page memory P
MR102, PMG103. PMB104G: Writes the stored image to the same size or by reducing the number of pixels by thinning out the image data to the memory section of the frame memory FM/DA108.The frame memory FM/DAI08 sequentially reads out image data from the memory section. It performs D/A conversion on the connected monitor 110 and outputs it. This frame memory FM/DA 108 is a 2-port memory, and even when an image is being displayed on the monitor 110, it is connected to the CPU board via the system bus 111.
BIOI or DMA: The Mz troller DMAC 107 can write image data, and the display screen will not be disturbed.

In this way, the image can be transmitted (sent) through the communication circuit 109 while or after checking the image on the monitor 110.

Further, when image data is received by the communication circuit 109, the communication circuit 109 directly transfers the received image data to the page memories PMR102 and PMG103 by DMA.
．． Write to the corresponding address in PMB104.

(Output of image data) Page memory PMR102゜P captured in this way
MG103. In order to obtain the image data of the PMB 104 as a hard copy, the image is transferred to the scanner printer SCA/PR 1106 using the scanner printer interface SPI/F 105 as an interface. S
Since PI/F105 does not have a page buffer,
Page memory PMR102, PMG103゜PMB10
4 and the printer of the scanner/printer SCA/PR1106 in real time. Here, page memories PMR102, PMG103. PMB104 and SP
Image signals flow between the I/Fs 105 using a high-speed bus. SPI/F105 is scanner/printer SC
The color components being printed by the A/PRII06 printer are output as high-speed bus control signals and stored in the page memory PMR102.
, PMG103. PMB104 (7) Each board determines whether it is selected based on its control signal, and if it is selected, the scanner/printer interface S
Image output is performed for each horizontal raster in synchronization with a synchronization signal output by the PI/F 105.

(DMA Method) FIG. 4 shows an embodiment of the DMA controller DMAC 107 for image display. First, DMA control-5DM
The AC107 has a register group 121 for writing operating conditions from the CPU board CPUBI01. Data is written into a corresponding portion of the register group 121 by an address decoder 133 and a data buffer 134 connected to the system bus 111. The register group 121 includes an address register 212 indicating which part of the frame memory FM/DA 108 is to be written, and page memories PMR 102, PMG 103 . A register 211 and page memories PMR102 and PMG103 for setting which address of PMB104 the image is read from.
．． A reduction register for setting the reduction ratio 1/R when transferring data from the PMB 104 to the frame memory FM/DA 108, and a reduction register for setting the reduction ratio R of 1/R when transferring data from the PMB 104 to the frame memory FM/DA 108. A transfer number register for setting whether to perform the transfer on the DA108, a data register and a DMA for forcibly changing the data written to the FM/DA108 to a specified value.
It has a DMA mode register to set the mode. There are three DMA modes; in the first mode, the page memories PMR102°PMG103. Data is transferred from the PMB 104 to the frame memory FM/DA 108. In the second mode, the data set in the data register of the register group 121 is transferred to the frame memory FM/DA1.
Write in 08.

In the third mode, the contents of the data ROM 122 are read and written to the frame memory FM/DA 108.

First mode First, page memories PMR102, PMG103. PM
B104 is a memory for one page, and except for the upper address allocated to each page memory, the lower addresses are mapped to the same address. The contents of the address register 211 are first selected by the selector 129,
It is latched (held) by latch 130.

This address is supplied to the address line via the multiplexer 128, and the data is read out from the page memory PMR102 and connected to the data latch 126.
is latched to the DLI of The control circuit 132 controls the page memories PMR102, PMG103. By replacing the upper address for PMB104, page memory PMG10
Data is read from DL2 of the data latch 126 and latched into the data latch DL2. Similarly, data is read from the page memory PMB104 and latched into DL3 of the data latch 126. The decoder 125 decodes the upper address generated by the control circuit 132 and the data latch 126
It generates latch enable signals for DLI to DL3.

By the way, DL4 of the data latch 126 operates in the same way as DLI, 2°3 only when the image signal is of 4 colors (for example, Y, M, C, Bk) and the page memory also exists for 4 colors. . Next, the data of the address register 212 is set in the address counter 124 in advance, and this address is selected by the multiplexer 128 and supplied to the address bus, and the contents of DL, 1-DL3 of the data latch 126 are transferred to the multiplexer 128. 27, frame memory FM/DA10
8 is written on. In this operation, the first pixel is stored in the frame memory FM/DA1 from the data in the three page memories.
Synthesized on 08. In the next pixel synthesis, latch 1
The value R of the reduction ratio register is added to the output of latch 130 by an adder 131, and this
This is relatched with latch 30 to be supplied to 30.

Further, the address counter 124 counts up by 1 and repeats the same operation as for the first pixel.

The same operation is repeated thereafter, but the data of the transfer number register has been set in the down counter 135 in advance.
Each time the processing for one pixel is completed, the power is turned down, and when the signal reaches O, it notifies the interrupter 136 that the processing for one line (horizontal) has ended. This ends the DMA operation.

The interrupter 136 requests the CPU board CPUB4O1 to set data to the address registers 211 and 212 for the next line. In this way, DMA transfer of, for example, a rectangular area can be performed by repeating the 1-line DMA.

Next, in mode 2, PMR102°PMG103. The image reading operation from the PMB 104 is skipped without being performed. Also multiplexer MPX12
In operation 7, the contents of the data register are selected and supplied to the data line without selecting DL1 to DL4 of the data latch 126.

This operation causes 1 in the width of the value set in the transfer number register.
Write a horizontal line with a constant image data value (data register value) using DMA (direct memory access). By repeating this for several consecutive lines in the vertical direction on the CPU board CPUBIOI, it is possible to fill, for example, a rectangular area with a certain value.

Using this function, the memory in the frame memory FM/DA 108 is cleared, and the image displayed on the monitor 110 can also be cleared.

In the third mode, the contents of the data ROM 122 prepared in advance are used as data, converted into R, G, and B colors by the look-up table LUT 123, and written to the frame memory FM/DA 108. The contents of the data ROM 122 are characters, character strings, and icons. Normally, the reduction ratio register must be set to R=1. Also, if R=0°5, the magnification ratio=1/R=2 and the size is doubled.

The read position of the data ROM 122 is set in the address register 211. Mode 3 differs from mode 2 in operation in that the multiplexer MPX 127 selects and outputs the data in the lookup table LUT 123, and the latch 1
30 outputs are provided.

The same clock as the address counter 140 is input to the latch 130, and the frame memory FM/DA 108
A clock is input every time one pixel of the board is accessed, and the data ROM is stored in the adjacent pixel (output of the address counter 124) of the frame memory FM/DA 108.
The adjacent pixels on 122 are converted by LUT 123 and are written. Further, the horizontal width of characters, character strings, and icons to be written to the frame memory FM/DA 108 is set in the transfer number register. When the DMA for one line is completed in this manner, the incrementer 136 issues an interrupt to the CPU board CPUBIOI to terminate the DMA. Then, the CPU on the CPU board CPUBIOI performs DMA settings for the next 1-pixel width line that constitutes the characters, character strings, icons, etc. In this way, by repeatedly making DMA requests for the number of vertical lines of characters, character strings, icons, etc. that the CPU wants to write using DMA, the frame memory FM/DA 108
It becomes possible to display characters, character strings, icons, etc. on the screen at high speed.

[Second Embodiment] FIG. 5 shows a second embodiment, in which DMA can be performed by specifying a rectangular area range for the corresponding DMA for each line in the first embodiment. . However, in order to perform DMA in a trapezoidal or diamond shape like line-compatible DMA, the CPU board CPUBI is used for each line as in the first embodiment.
OI must intervene in the process. However, in the second embodiment, during the DMA of the rectangular area, the CPU board
There is no need for IOI to intervene.

The different parts from the first embodiment will be explained below.

First, in the transfer number register of the register group 121, in addition to the number of horizontal pixels of the rectangular area to be written into the frame memory FM/DA 108, the number of pixels in the vertical direction is also set. This vertical pixel width number is determined by the down counter 141 at the beginning of the DMA.
is set to When the DMA for each line in the rectangular area is completed, the down counter 135 sends an LS indicating the end of one line.
A synchronization signal YNC is generated, and the down counter 141
Count down to 11. Address register 211 uses DMA to store page memories PMR102, PMG103.
The first address for reading the PMB 104 is set, and its vertical and horizontal components are set in the latch 144 through the selector 143 before the start of DMA, and the horizontal component is set in the latch 130 through the selector 129.

This horizontal component is reset many times in synchronization with LSYNC.

Further, LSYNC is supplied to the latch 144 as a synchronizing signal, and the value R of the reduction rate register is added to the vertical address by the adder 45 every time the DMA for one line is completed. (retained).

The output of the latch 130, which is the horizontal address, and the latch 144, which is the vertical address, are output from the multiplexer MP.
Through X128, page memory PMR102゜PMG
103. It is supplied to the PMB 104 or data ROM 122.

Also, it is supplied to the data ROM 122 and the frame memory FM/
When data such as a character string is DMAed to the DA 108, R=1 is normally set. Also, if R=0.5, the image will be enlarged twice. However, only the bits of the integer part of the outputs of the latches 130 and 140 are supplied to the data ROM 122.

〔Effect of the invention〕

As described above, according to the present invention, when printing out a read image, by processing the read image and displaying it, for example, you can check fine details by enlarging it, or check the overall balance by reducing it. It has a great effect on understanding image data because it can perform high-speed processing such as adding reference data through synthesis to aid understanding.

[Brief explanation of drawings]

Fig. 1 is an overall configuration diagram of one embodiment of the present invention, Fig. 2 is an overview diagram of a scanner/printer, Fig. 3 is a block diagram of a control section of the scanner/printer, and Fig. 4 is a first implementation of a DMA controller. FIG. 5 is a diagram showing a second embodiment of the DMA controller. 1......... Scanner 2.
......Printer 101...
・・・・・・・・・ ・・・CPU board 102.103
, 104 ... Page memory 127゜ ... Scanner/printer interface ... Direct memory access controller ... Frame memory communication circuit for monitor Scanner/printer Monitor system bus high-speed path register group data ROM look-up table address counter decoder data latch 128...Multiplexer selector latch adder control circuit

Claims (4)

[Claims] (1) An image processing system that reads image information and outputs the image onto a recording medium, comprising a reading means for reading the image information, a storage means for storing the image information read by the reading means, and a display means for displaying the image information. , a direct memory access means, a processing means for processing image information, and the image information stored in the storage means is accessed by the direct memory access means, processed by the processing means, and displayed on the display means. An image processing system comprising: a control means for controlling display. (2) The image processing system according to claim 1, further comprising a second control means for controlling the storage operation by the storage means and the access operation by the direct memory access means so that they can be performed in parallel. (3) The image processing system according to claim 1, wherein the processing means performs scaling processing on the size of the image information. (4) An image characterized in that it has a second storage means for storing text or image information, and the processing means combines or replaces the image information with the information stored in the second storage means. processing system.