JPH02288403A - Superconductive monolithic integrated circuit and manufacture thereof - Google Patents
Superconductive monolithic integrated circuit and manufacture thereofInfo
- Publication number
- JPH02288403A JPH02288403A JP1111545A JP11154589A JPH02288403A JP H02288403 A JPH02288403 A JP H02288403A JP 1111545 A JP1111545 A JP 1111545A JP 11154589 A JP11154589 A JP 11154589A JP H02288403 A JPH02288403 A JP H02288403A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- integrated circuit
- superconductor thin
- monolithic integrated
- superconducting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 239000002887 superconductor Substances 0.000 claims abstract description 35
- 239000010409 thin film Substances 0.000 claims abstract description 29
- 239000004020 conductor Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 239000012212 insulator Substances 0.000 claims abstract description 11
- 239000003990 capacitor Substances 0.000 claims description 21
- 239000010408 film Substances 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 claims description 8
- 150000001875 compounds Chemical class 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 6
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 7
- 229910021521 yttrium barium copper oxide Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 229920006254 polymer film Polymers 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- 235000004522 Pentaglottis sempervirens Nutrition 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- KOWWOODYPWDWOJ-LVBPXUMQSA-N elatine Chemical compound C([C@]12CN(C3[C@@]45OCO[C@]44[C@H]6[C@@H](OC)[C@@H]([C@H](C4)OC)C[C@H]6[C@@]3([C@@H]1[C@@H]5OC)[C@@H](OC)CC2)CC)OC(=O)C1=CC=CC=C1N1C(=O)CC(C)C1=O KOWWOODYPWDWOJ-LVBPXUMQSA-N 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- BKVIYDNLLOSFOA-UHFFFAOYSA-N thallium Chemical compound [Tl] BKVIYDNLLOSFOA-UHFFFAOYSA-N 0.000 description 1
- 229910052716 thallium Inorganic materials 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 229910052727 yttrium Inorganic materials 0.000 description 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
- Y02E40/60—Superconducting electric elements or equipment; Power systems integrating superconducting elements or equipment
Landscapes
- Superconductor Devices And Manufacturing Methods Thereof (AREA)
- Superconductors And Manufacturing Methods Therefor (AREA)
- Waveguides (AREA)
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明はマイクロ波ミリ波領域で用いるモノリシック集
積回路に関し、特に超伝導薄膜をマイクロストリップ導
体に用いたモノリシックマイクロ波回路およびその製造
方法に関するものである。[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a monolithic integrated circuit used in the microwave and millimeter wave region, and particularly to a monolithic microwave circuit using a superconducting thin film as a microstrip conductor and a method for manufacturing the same. It is.
（従来の技術）
近年の高温超伝導体の発見により、超伝導体の各種応用
に関する研究開発が活発化している。この中で、マイク
ロ波集積回路への超伝導体の応用分野では、一般に超伝
導材料の高電流密度化および超微細化は必ずしも必要で
なく、単に電気抵抗が小さいという点だけでも従来にな
い大きな効果が期待できる。例えばマイクロ波受信回路
における最人力段整合回路には微弱電流しか流れないが
、その損失を１ｄＢ改善できたとすれば受信機の雑音指
数を１ｄＢ改善したことを意味し、その効果は絶大であ
る。通常この種の整合回路にはマイクロストリップ線路
が用いられるが、ストリップ導体の幅は数ｐｍ〜数＋数
毎μｍ程度り、特に超微細加工が要求されているわけで
はない。このため特にマイクロ波集積回路の分野は高温
超伝導体の利用分野として十分に応用可能となっている
。(Prior Art) The recent discovery of high-temperature superconductors has stimulated research and development into various applications of superconductors. Among these, in the field of application of superconductors to microwave integrated circuits, it is generally not necessary to increase the current density and ultra-fine size of superconducting materials, and simply to have a low electrical resistance makes it possible to You can expect good results. For example, only a weak current flows through the most powerful stage matching circuit in a microwave receiving circuit, but if the loss can be improved by 1 dB, it means that the noise figure of the receiver has been improved by 1 dB, and the effect is enormous. Usually, a microstrip line is used in this type of matching circuit, but the width of the strip conductor is about several pm to several + several micrometers, and ultrafine processing is not particularly required. For this reason, the field of microwave integrated circuits in particular has become fully applicable as a field in which high-temperature superconductors can be used.
第５図は超伝導体を用いた従来のモノリシックマイクロ
波集積回路（ＭＭＩＣ）の構造を示す図である。FIG. 5 is a diagram showing the structure of a conventional monolithic microwave integrated circuit (MMIC) using a superconductor.
図において半絶縁性ＧａＡｓ基板１８上に、イオン注入
層１３をチャンネル層とし、ゲート電極１９、ソース電
極１５、ドレイン電極１４を備えたＧａＡｓ ＦＥＴが
構成され、バイアホール１７によって裏面電極２３に電
気的に接続された超伝導体薄膜１１の上に誘電体薄膜２
０が構成され、さらにその上に超伝導ストリップ導体１
２および超伝導キャパシタ上部電極２２が構成されてい
る。In the figure, a GaAs FET is constructed on a semi-insulating GaAs substrate 18, with an ion implantation layer 13 as a channel layer, a gate electrode 19, a source electrode 15, and a drain electrode 14. A dielectric thin film 2 is placed on top of a superconductor thin film 11 connected to
0 is constructed, and furthermore, a superconducting strip conductor 1 is placed on top of it.
2 and a superconducting capacitor upper electrode 22.
（発明が解決しようとする問題点）
マイクロストリップ線路の損失は（１）導体損（２）放
射損および（３）誘電体損からなる。常伝導マイクロス
トリップ線路では導体損が支配的であるが、超伝導マイ
クロストリップ線路の場合は導体損は極めて小さくなり
損失の大部分は誘電体損となる。(Problems to be Solved by the Invention) Loss in a microstrip line consists of (1) conductor loss, (2) radiation loss, and (3) dielectric loss. In a normal conductive microstrip line, conductor loss is dominant, but in a superconducting microstrip line, the conductor loss is extremely small and most of the loss is dielectric loss.
このため超伝導マイクロストリップ線路の損失をさらに
低くするためには誘電体損を削減することが必要である
。Therefore, in order to further reduce the loss of the superconducting microstrip line, it is necessary to reduce the dielectric loss.
一方平行平板キャパシタの損失の原因もマイクロストリ
ップ線路の場合と同様であり、電極を超伝導化すると導
体損は無視できるようになるがさらに損失を低くするに
は誘電体損を削減することが必要である。特にＭＭＩＣ
においては温度等誘電体成膜上の制約から低損失の誘電
体膜が実現できず大きな課題であった。On the other hand, the causes of loss in parallel plate capacitors are similar to those in microstrip lines; if the electrodes are made superconducting, conductor loss can be ignored, but to further reduce loss, it is necessary to reduce dielectric loss. It is. Especially MMIC
However, due to temperature and other constraints on dielectric film formation, it was not possible to realize a dielectric film with low loss, which was a major problem.
本発明の目的は誘電体損を大幅に削減した超伝導マイク
ロストリップ線路およびキャパシタを搭載したＭＭＩＣ
を提供することにある。The purpose of the present invention is to provide an MMIC equipped with a superconducting microstrip line and a capacitor that significantly reduces dielectric loss.
Our goal is to provide the following.
（問題点を解決するための手段）
上記目的を達成するために、本発明の超伝導モノリシッ
ク集積回路は、半絶縁性化合物半導体基板上に少なくと
も能動素子とマイクロストリップ線路型受動回路とを搭
載したモノリシック集積回路において、超伝導体薄膜か
ら成るマイクロストリップ線路の接地導体が前記基板表
面に設けられ、超伝導体薄膜からなるマイクロストリッ
プ導体が複数の絶縁体支柱により空中に支えられること
を特徴としている。(Means for Solving the Problems) In order to achieve the above object, the superconducting monolithic integrated circuit of the present invention has at least an active element and a microstrip line type passive circuit mounted on a semi-insulating compound semiconductor substrate. The monolithic integrated circuit is characterized in that a ground conductor of a microstrip line made of a superconductor thin film is provided on the surface of the substrate, and the microstrip conductor made of the superconductor thin film is supported in the air by a plurality of insulating supports. .
さらに、半絶縁性化合物半導体基板上に少なくとも能動
素子と平行平板型キャパシタとを搭載したモノリシック
集積回路において、超伝導体薄膜からなるキャパシタ下
部電極が前記基板表面に設けられ、超伝導体薄膜からな
るキャパシタ上部電極が複数の絶縁体支柱により空中に
支えられていることを特徴としている。Furthermore, in a monolithic integrated circuit in which at least an active element and a parallel plate capacitor are mounted on a semi-insulating compound semiconductor substrate, a capacitor lower electrode made of a superconductor thin film is provided on the surface of the substrate, and a capacitor lower electrode made of a superconductor thin film is provided on the surface of the substrate. It is characterized in that the capacitor upper electrode is supported in the air by a plurality of insulator columns.
さらに上記集積回路の製造方法は半絶縁性化合物半導体
基板上に第１の超伝導体薄膜を選択的に形成する工程と
支柱となる絶縁体を前記第１の超伝導体薄膜上に選択的
に形成する工程と、膜材を塗布し表面の凹凸を平坦化し
た後エッチバック法により前記絶縁体支柱の頭出しをす
る工程と、第２の超伝導体薄膜を前記支柱に接して選択
的に形成する工程と、前記膜材を除去する工程とを含む
ことを特徴としている。Furthermore, the method for manufacturing the integrated circuit includes a step of selectively forming a first superconductor thin film on a semi-insulating compound semiconductor substrate, and a step of selectively forming an insulator serving as a pillar on the first superconductor thin film. a step of applying a film material to flatten surface irregularities and then aligning the insulator pillars by an etch-back method; and selectively applying a second superconductor thin film in contact with the pillars. The method is characterized in that it includes a step of forming the film material, and a step of removing the film material.
（作用）
本発明においては超伝導マイクロストリップ導体は、支
柱部を除いて空中に浮いているためマイクロストリップ
線路にとっての誘電体は主として空気であり誘電体損を
極めて小さくできる。これと同様にキャパシタに関して
も超伝導体薄膜からなるキャパシタ上部電極は支柱部を
除いて空中に浮いているため、キャパシタにとっての誘
電体は主として空気であり誘電体損を極めて小さくでき
る。この結果マイクロストリップ線路およびキャパシタ
から導体膜および誘電体損を殆ど除去でき、例えば５０
Ωマイクロストリツプ線路に関しては伝送損失は１０Ｇ
Ｈｚで１ｃｍ当たり０．００１ｄＢ以下、キャパシタＱ
値も１０ＧＨｚで１０００以上が実現できる。(Function) In the present invention, since the superconducting microstrip conductor is floating in the air except for the support portion, the dielectric for the microstrip line is mainly air, and the dielectric loss can be extremely reduced. Similarly, with regard to capacitors, the upper electrode of the capacitor made of a superconductor thin film is floating in the air except for the pillars, so the dielectric material for the capacitor is mainly air, and dielectric loss can be extremely reduced. As a result, conductor film and dielectric loss can be almost completely removed from microstrip lines and capacitors.
The transmission loss for Ω microstrip line is 10G.
0.001 dB or less per cm at Hz, capacitor Q
A value of 1000 or more can be achieved at 10GHz.
このような超伝導モノリシック集積回路の製造方法にお
いては該支柱を形成した後レジスト膜や高分子膜等の膜
材による平坦化およびエッチバックによる支柱頭出しを
行い、その後マイクロストリップ導体又はキャパシタ上
部電極を構成し、最後に高分子膜を除去するための本発
明の構造が実現できる。In such a method for manufacturing a superconducting monolithic integrated circuit, after forming the pillars, the pillars are flattened with a film material such as a resist film or a polymer film, and the pillars are exposed by etching back, and then a microstrip conductor or capacitor upper electrode is formed. The structure of the present invention can be realized for constructing and finally removing the polymer film.
（実施例）
第１図（ａ）、（ｂ）は第１の本発明の実施例の超伝導
モノリシック集積回路の１部を示す図である。（ａ）は
平面図、（ｂ）は断面図を示す。同図において半絶縁性
ＧａＡｓ基板８上にＹＢａ２Ｃｕ３Ｏ７からなる超伝導
体薄膜２から構成されるマイクロストリップ接地導体が
設けられ、さらにこの上に５ｉ０２からなる絶縁体支柱
１に支えれらたＹＢａ２Ｃｕ３Ｏ７からなる超伝導マイ
クロストリップ導体３が構成されている。(Embodiment) FIGS. 1(a) and 1(b) are diagrams showing a part of a superconducting monolithic integrated circuit according to a first embodiment of the present invention. (a) shows a plan view, and (b) shows a cross-sectional view. In the same figure, a microstrip ground conductor made of a superconductor thin film 2 made of YBa2Cu3O7 is provided on a semi-insulating GaAs substrate 8, and a superconductor made of YBa2Cu3O7 supported by an insulator column 1 made of 5i02 is further placed on top of this. A conducting microstrip conductor 3 is constructed.
超伝導体マイクロストリップ導体３と超伝導体薄膜２の
間隔をＳ、超伝導ストリップ導体３の幅をＷ、３および
２の厚みをＴ、超伝導体のロンドンの侵入長をλとし、
絶縁体支柱１の誘電率の効果を無視すると、このマイク
ロストリップ線路の特性インピーダンス２゜は
と表される。（１）式においてｚｓｅｒｉｅｓは直列イ
ンピーダンスであり単位長当たりの表面インピーダンス
の２倍と、単位長当たりの幾何学的インダクタンスの和
で表わされ、Ｙｓｈｕｎｔ（＝ｊｗＣ）は単位長当たり
の容量Ｃ＝８゜ｅｒｗｌＳにより表わされる。（１）式
においてＴ／λ＞１、ｐｒ＝１を仮定すると
となる。（２）式においてｚｎは常伝導体マイクロスト
リップ線路の特性インピーダンスである。The distance between the superconducting microstrip conductor 3 and the superconducting thin film 2 is S, the width of the superconducting strip conductor 3 is W, the thickness of 3 and 2 is T, and the London penetration length of the superconductor is λ,
Ignoring the effect of the dielectric constant of the insulator pillar 1, the characteristic impedance 2° of this microstrip line is expressed as follows. In equation (1), zseries is the series impedance and is expressed as the sum of twice the surface impedance per unit length and the geometric inductance per unit length, and Yshunt (=jwC) is the capacitance per unit length C= It is represented by 8°erwlS. In equation (1), assuming T/λ>1 and pr=1. In equation (2), zn is the characteristic impedance of the normal conductor microstrip line.
Ｓ＝１ｐｍ、 Ｗ＝７ｐｍ、 ｅｒ＝１、λ＝ ０．１
５ｐｍとするとｚｎ：５０１ｚｏ牟５７Ωとなる。S=1pm, W=7pm, er=1, λ=0.1
When it is 5 pm, it becomes zn:501zo㉟57Ω.
第２図（ａ）、 （ｂ）は第２の本発明の実施例の超伝
導モノリシック集積回路の１部を示す図である。同図に
おいて（ａ）は上面図（ｂ）は断面図を示し、半絶縁性
ＧａＡｓ基板８上にＹＢａ２Ｃｕ３Ｏ７からなる超伝導
体薄膜２から構成されるキャパシタ下部電極上に５ｉ０
２からなる絶縁体支柱１に支えられたＹＢａ２Ｃｕ３Ｏ
７からなる超伝導体薄膜４から構成されるキャパシタ上
部電極が設けられている。FIGS. 2(a) and 2(b) are diagrams showing a part of a superconducting monolithic integrated circuit according to a second embodiment of the present invention. In the figure, (a) shows a top view, and (b) shows a cross-sectional view, in which 5i0
YBa2Cu3O supported by an insulator column 1 consisting of 2
A capacitor upper electrode consisting of a superconductor thin film 4 consisting of 7 is provided.
第３図（ａ）〜（ｆ）、第３の本発明の製造方法を示す
図であり、第３図（ａ）のようにまず半絶縁性ＧａＡｓ
基板８上に全面にスパッタ法によりＹＢａ２Ｃｕ３Ｏ７
からなる超伝導体薄膜を形成しその後ホトレジストをマ
スクとしたドライエツチングにより不用部の超伝導体薄
膜を除去し所望の超伝導薄膜２を形成する。次に第３図
（ｂ）に示すように熱ＣＶＤ法により５ｉ０２膜を成膜
しその後選択エツチングにより支柱１を形成する。さら
に第３図（Ｃ）に示すようにレジスト膜６などを塗布し
て表面を平坦化する。その後反応性イオンエツチングに
より垂直方向から異方性エツチングを行い、支柱１の頭
出しを行う（第３図（ｄ））。続いて第３図（ｅ）に示
すようにＹＢａ２Ｃｕ３Ｏ７をスパッタ法により全面形
成しその後ホトレジストをマスクとしたドライエツチン
グにより第２の超伝導薄膜３を形成する。最後に酸素プ
ラズマ中のアッシングによりレジスト膜６を除去する（
第３図（ｆ））。FIGS. 3(a) to 3(f) are diagrams showing the manufacturing method of the third invention, and as shown in FIG. 3(a), first, semi-insulating GaAs is
YBa2Cu3O7 is deposited on the entire surface of the substrate 8 by sputtering.
A superconductor thin film is formed, and then unnecessary portions of the superconductor thin film are removed by dry etching using a photoresist as a mask to form a desired superconductor thin film 2. Next, as shown in FIG. 3(b), a 5i02 film is formed by thermal CVD, and then pillars 1 are formed by selective etching. Furthermore, as shown in FIG. 3(C), a resist film 6 or the like is applied to flatten the surface. Thereafter, anisotropic etching is performed from the vertical direction using reactive ion etching to locate the top of the support 1 (FIG. 3(d)). Subsequently, as shown in FIG. 3(e), YBa2Cu3O7 is formed on the entire surface by sputtering, and then a second superconducting thin film 3 is formed by dry etching using a photoresist as a mask. Finally, the resist film 6 is removed by ashing in oxygen plasma (
Figure 3(f)).
第４図は本発明の超伝導モノリシック集積回路の実施例
の鳥観図である。同図において半絶縁性ＧａＡｓ基板１
８上にイオン注入層１３をチャンネル層としソース電極
１５ドレイン電極１４、ゲート電極１９を備えたＧａＡ
ｓ ＦＥＴが構成され、さらに該ＧａＡｓ基板上にマイ
クロストリップ線路の接地導体およびキャパシタの下部
電極となる超伝導体薄膜１１が設けられ、この上に５ｉ
０２からなる支柱４０に支えられた超伝導マイクロスト
リップ導体１２および超伝導キャパシタ上部電極２２が
構成されている。超伝導体薄膜１１はバイアホール１７
を通じて裏面電極２３に電気的に接続されている。FIG. 4 is a bird's eye view of an embodiment of the superconducting monolithic integrated circuit of the present invention. In the figure, a semi-insulating GaAs substrate 1
GaA having an ion-implanted layer 13 as a channel layer on 8, a source electrode 15, a drain electrode 14, and a gate electrode 19.
A superconductor thin film 11 is provided on the GaAs substrate to serve as the ground conductor of the microstrip line and the lower electrode of the capacitor.
A superconducting microstrip conductor 12 and a superconducting capacitor upper electrode 22 are supported by pillars 40 made of 02. The superconductor thin film 11 has a via hole 17
It is electrically connected to the back electrode 23 through.
（発明の効果）
本発明の超伝導モノリシック集積回路においては、マイ
クロストリップ線路およびキャパシタの誘電体を主とし
て空気により構成するので誘電体損を大幅に減らすこと
ができ、従来の超伝導モノリシック集積回路の欠点を除
去できる。これにより例えば５０Ωマイクロストリツプ
線路に関しては伝送損失は１０ＧＨｚで１ｃｍ当たり０
．００１ｄＢ以下、キャパシタのＱ値も１０ＧＨｚで１
０００以上が実現でき、マイクロ波ミリ波工学上意義は
大きい。(Effects of the Invention) In the superconducting monolithic integrated circuit of the present invention, since the dielectric of the microstrip line and the capacitor are mainly composed of air, dielectric loss can be significantly reduced, which is different from that of the conventional superconducting monolithic integrated circuit. Defects can be removed. For example, for a 50Ω microstrip line, the transmission loss is 0 per cm at 10GHz.
．． 001dB or less, and the Q value of the capacitor is also 1 at 10GHz.
000 or more, which is of great significance in microwave and millimeter wave engineering.
また本発明の製造方法においてはレジスト膜による平坦
化およびエラチンバックによる支柱頭出し工程を用いて
いるためサブミクロンオーダの支柱を有する超伝導モノ
リシック集積回路を実現できる。Furthermore, in the manufacturing method of the present invention, a superconducting monolithic integrated circuit having pillars on the order of submicrons can be realized because the process of flattening with a resist film and positioning the pillars with an elatin back is used.
なお本発明の実施例においては超伝導体薄膜に高Ｔｃ超
伝導体であるＹＢａ２Ｃｕ３Ｏ７を用いたが超伝導体イ
ツトリウム系に限らずタリウム系などでもよい。また超
伝導体は高Ｔｃ系の材料に限らず、Ｎｂ等の低温系の材
料でもよいことは云うまでもない。In the embodiment of the present invention, YBa2Cu3O7, which is a high Tc superconductor, is used for the superconductor thin film, but the superconductor is not limited to yttrium, but may be thallium or the like. It goes without saying that the superconductor is not limited to high Tc materials, but may also be low temperature materials such as Nb.
さらに能動素子もＧａＡｓ ＦＥＴに限らすＨＥＭＴ、
ＨＢＴあるいはＩｎＰＦＥＴなといずれでもよい。Furthermore, HEMTs whose active elements are limited to GaAs FETs,
Either HBT or InPFET may be used.
第１図（ａ）、 （ｂ）、第２図（ａ）、（ｂ）、第４
図は本発明の実施例の超伝導モノリシック集積回路を示
す図、第３図（ａ）〜（Ｏは本発明の実施例の超伝導モ
ノリシック集積回路の製造方法を示す図、第５図は従来
例の超伝導モノリシック集積回路を示す図である。これ
らの図においてFigure 1 (a), (b), Figure 2 (a), (b), Figure 4
The figure shows a superconducting monolithic integrated circuit according to an embodiment of the present invention, FIGS. Figures 1 and 2 illustrate example superconducting monolithic integrated circuits.
Claims (3)
子とマイクロストリップ線路型受動回路とを搭載したモ
ノリシック集積回路において、超伝導体薄膜から成るマ
イクロストリップ線路の接地導体が前記基板表面に設け
られ、前記接地導体上に超伝導体薄膜からなるマイクロ
ストリップ導体が複数の絶縁体支柱により空中に支持さ
れて設けられていることを特徴とする超伝導モノリシッ
ク集積回路。(1) In a monolithic integrated circuit in which at least an active element and a microstrip line type passive circuit are mounted on a semi-insulating compound semiconductor substrate, a ground conductor of a microstrip line made of a superconductor thin film is provided on the surface of the substrate, A superconducting monolithic integrated circuit characterized in that a microstrip conductor made of a superconductor thin film is provided on the ground conductor and is supported in the air by a plurality of insulating columns.
子と平行平板型キャパシタとを搭載したモノリシック集
積回路において、超伝導体薄膜からなるキャパシタ下部
電極が前記基板表面に設けられ、超伝導体薄膜からなる
キャパシタ上部電極が複数の絶縁体支柱により空中に支
持され設けられていることを特徴とする超伝導モノリシ
ック集積回路。(2) In a monolithic integrated circuit in which at least an active element and a parallel plate capacitor are mounted on a semi-insulating compound semiconductor substrate, a capacitor lower electrode made of a superconductor thin film is provided on the surface of the substrate, and A superconducting monolithic integrated circuit characterized in that a capacitor upper electrode is supported in the air by a plurality of insulator supports.
膜を形成する工程と支柱となる絶縁体を前記第１の超伝
導体薄膜上に形成する工程と、膜材を塗布し表面の凹凸
を平坦化した後エッチバック法により前記絶縁体支柱の
頭出しをする工程と第２の超伝導体薄膜が第１の超伝導
体薄膜とを前記支柱を介して接するように第２の超伝導
体薄膜を形成する工程と、前記膜材を除去する工程とを
含むことを特徴とする超伝導モノリシック集積回路の製
造方法。(3) A step of forming a first superconductor thin film on a semi-insulating compound semiconductor substrate, a step of forming an insulator to serve as a pillar on the first superconductor thin film, and a step of applying a film material to the surface. After flattening the unevenness of the insulator pillars, a step of locating the top of the insulator pillars by an etch-back method; A method for manufacturing a superconducting monolithic integrated circuit, comprising the steps of forming a superconductor thin film and removing the film material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1111545A JPH02288403A (en) | 1989-04-27 | 1989-04-27 | Superconductive monolithic integrated circuit and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1111545A JPH02288403A (en) | 1989-04-27 | 1989-04-27 | Superconductive monolithic integrated circuit and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02288403A true JPH02288403A (en) | 1990-11-28 |
Family
ID=14564094
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1111545A Pending JPH02288403A (en) | 1989-04-27 | 1989-04-27 | Superconductive monolithic integrated circuit and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02288403A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000209057A (en) * | 1999-01-14 | 2000-07-28 | Fuji Electric Co Ltd | Noise filter |
| JP2000312121A (en) * | 1999-04-27 | 2000-11-07 | Fuji Electric Co Ltd | Noise filter |
| EP1505685A1 (en) * | 2003-07-28 | 2005-02-09 | Infineon Technologies AG | Microstrip line and method for producing of a microstrip line |
| WO2023139779A1 (en) | 2022-01-24 | 2023-07-27 | 富士通株式会社 | Josephson element, superconducting circuit, quantum computation device, and method for manufacturing josephson element |
-
1989
- 1989-04-27 JP JP1111545A patent/JPH02288403A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000209057A (en) * | 1999-01-14 | 2000-07-28 | Fuji Electric Co Ltd | Noise filter |
| JP2000312121A (en) * | 1999-04-27 | 2000-11-07 | Fuji Electric Co Ltd | Noise filter |
| EP1505685A1 (en) * | 2003-07-28 | 2005-02-09 | Infineon Technologies AG | Microstrip line and method for producing of a microstrip line |
| WO2023139779A1 (en) | 2022-01-24 | 2023-07-27 | 富士通株式会社 | Josephson element, superconducting circuit, quantum computation device, and method for manufacturing josephson element |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5343071A (en) | Semiconductor structures having dual surface via holes | |
| US4466172A (en) | Method for fabricating MOS device with self-aligned contacts | |
| US4554567A (en) | Superconductive integrated circuit incorporating a magnetically controlled interferometer | |
| US5812364A (en) | Capacitor | |
| US4837536A (en) | Monolithic microwave integrated circuit device using high temperature superconductive material | |
| US4871687A (en) | Method of fabricating a MESFET transistor with gate spaced above source electrode by layer of air or the like | |
| US4460880A (en) | Circuit matching elements | |
| US6177716B1 (en) | Low loss capacitor structure | |
| JPS583381B2 (en) | How to make traces above and below the ground plane on one side of the support board | |
| CA1208960A (en) | Method of making improved tunnel barriers for superconducting josephson junction devices | |
| EP0545801B1 (en) | Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same | |
| US6051440A (en) | Method of fabricating a low-inductance in-line resistor for superconductor integrated circuits | |
| US5320570A (en) | Method for realizing high frequency/speed field emission devices and apparatus | |
| US4381341A (en) | Two stage etching process for through the substrate contacts | |
| JPH02288403A (en) | Superconductive monolithic integrated circuit and manufacture thereof | |
| EP0798790A1 (en) | Method for manufacturing a superconducting device having an extremely thin superconducting channel | |
| EP0419361B2 (en) | Method for forming an electrode for electrical connection to oxide superconductor | |
| CA2050731C (en) | Superconducting device having a reduced thickness of oxide superconducting layer and method for manufacturing the same | |
| JP2822953B2 (en) | Superconducting circuit manufacturing method | |
| JPH04368005A (en) | Microwave transmission line | |
| US5751201A (en) | Resonator with metal layers devoid of DC connection and semiconductor device in substrate | |
| JP2004303744A (en) | Monolithic microwave integrated circuit and its fabrication method | |
| JPS60124851A (en) | Microwave integrated circuit device | |
| JP2727773B2 (en) | Method of manufacturing Josephson integrated circuit | |
| US6387753B1 (en) | Low loss capacitor structure |