JPH02288225A - Method of forming contact hole/via hole - Google Patents

Abstract

PURPOSE: To improve the step coverage and reliability of a via-holes/contact hole by respectively forming a side-wall oxide spacer and a metallized layer for barrier on the vertical wall surface and bottom of the via hole/contact hole and depositing an isomorphic layer composed of a high-melting point material, such as a silicide, etc., on the structure. CONSTITUTION: A method for forming contact hole/via hole contains a method for connecting two conductor layers at different levels to each other. A silicon substrate of a first conductive layer forms a lower-level conductive material. The conductive material layer is coated with an inter-level oxide layer. An opening is formed through the oxide layer and an isomorphic high-melting point layer is deposited on the structure and covers the side wall of the opening with a uniform thickness. Consequently, two levels isolated by the inter-level oxide layer are electrically connected to each other. Then interconnection is established between the upper section of the high-melting point material layer and another structure at an upper level by sputtering a metallized layer on the upper surface.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention generally relates to contact holes and pier holes used in semiconductor processes, and more specifically to step coverage of contact holes and pier holes. Concerning improving the.

In prior art semiconductor processing, one of the most important process steps is the interconnection of two conductive layers at different levels separated by an insulating layer. This interconnection is particularly important when one conductive layer is the top metallization layer. Currently, the conductor layer extending below is coated with an interlevel oxide layer (interlevel dielectric layer), and connection holes, such as contact holes or pier holes, formed in this oxide layer extend below the conductor layer. Exposing selected areas of the layer. The top conductor layer is then patterned and interconnected with the conductor layer extending below through contact holes or pier holes. This conductor layer extending below includes a conductive layer of polycrystalline silicon, or metal, or even the silicon surface itself.

Achieving a conductive connection between two layers requires a low resistance interface of the contact with the underlying metal or silicon, and the properties of this underlying material, especially if this material is silicon. It is important to ensure that the characteristics do not change in the case of Furthermore, it is important that the resistance between the contact interface itself and the upper metallization layer be low.

SUMMARY OF THE INVENTION One drawback of conventional processes is "voids" in the upper metallization layer on the vertical surface of the contact opening or pier hole. This can occur due to a number of reasons. One common cause in industry is that the coating is not conformal when depositing metallization layers using sputtering or physical vapor deposition methods. here,
“Same shape” means “the coating state of the film is faithful to the base level difference, etc.”
This term is used to mean "formal". Since these methods are anisotropic processes, the vertical surfaces within the contact opening or pier hole only have a relatively thin layer of metallization formed on the surface of the vertical walls; A thick "bulge" is formed along the upper edge. Voids in the metallized layer generally occur along this vertical plane. This problem is solved by depositing the conductive material by CVD. However, usually the CVD method is
It is not suitable for the types of metals required in the upper levels, for example for aluminum metallization processes.

SUMMARY OF THE INVENTION The invention disclosed and claimed herein includes a method of making a connection between two conductive layers at different levels. A silicon substrate or a first conductive layer forms the lower level of conductive material. This layer of conductive material is covered by an interlevel oxide layer. an opening is formed in the interlevel oxide layer;
A conformal layer of refractory material is then deposited over the structure to cover the sidewalls of the opening to a uniform thickness. This results in conduction between the two levels separated by the interlevel oxide layer. A metallization layer is then sputtered onto the top surface to establish interconnections between the upper portion of the refractory material layer and other structures in the upper level.

According to another aspect of the invention, the high melting point material is deposited over the entire substrate and extends over the surface of the interlevel oxide layer and over the bottom surface of the opening near the lower level. A barrier metal is deposited between the conformal refractory material layer and the lower conductive level.

According to yet another aspect of the invention, a sidewall oxide layer is formed with a tapered profile on the sidewalls of the opening. The tapered profile extends from a narrow portion at the lower level to a wider portion at the upper level such that the opening is wider at the upper level. As a result, a step is obtained which is more gradual than in the past, and a layer of high melting point material having the same shape is formed thereon. Preferably, the high melting point material is tungsten disilicide.

To more fully understand the invention and its advantages,
The explanation will be given with reference to the attached drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1, an interlevel oxide 12 is shown formed over a semiconductor structure 10 .

Preferably, semiconductor structure 10 is silicon.

However, in explaining the present invention, the semiconductor structure 1
Assume that 0 represents the first level conductor.

This point will be explained in detail later.

Oxide layer 12 is typically referred to as an interlevel oxide or interlevel dielectric layer and is approximately 5,000 to 10,000 nm thick. After forming oxide layer 12, contact holes or peer holes 14 are formed in oxide layer 12.

In the following description, it will be referred to as pier hole 14. As can be seen from the cross-sectional view, the pier hole 14 has two vertical side walls 16.
and 18. The pier holes 14 are formed by patterning the surface of the oxide layer 12 using a photoresist operation and then subjecting the structure to anisotropic plasma etching to remove the oxide in the unmasked areas. As a result, vertical side walls 16 and 18 are formed.

After the formation of the pier hole 14, a conformal layer of insulating material 20 is deposited over the pier hole 14 and the oxide layer 12 so as to conformally cover the vertical sidewalls 16 and 18 as well as the bottom surface 19 of the contact hole/pier hole. Insulating material layer 20 preferably includes deposited silicon oxide or silicon nitride. This layer of insulating material 20 can be deposited by a conventional low temperature reaction process using CVD techniques. The layer of insulating material 20 can have a thickness of several 1,000 layers.

The preferred thickness is 2.00OA. As explained above, the layer of insulating material 20 conforms to the geometry of the pier hole 14 and adheres to the vertical sidewalls 16 and 18.

As shown in FIG. 3, the layer of insulating material 20 is removed anisotropically so that the sidewalls 16 and 18 are each covered with a relatively thick oxide layer 2.
Covered by 2 and 24. - for example, a layer of insulating material 20
is 2.000 A, the lateral thickness of the sidewall oxide layers 22 and 24 is about 2.00 A near the bottom surface 19.
000 A, and is slightly thinner near the top surface of the insulating material layer 20. Therefore, the sidewall oxide layer 22
and 24 have a tapered surface rather than a vertical surface. As will be explained later, this results in the formation of a conductive layer within the pier hole 14 with a "rounded" surface.

Insulating material layer 20 can be anisotropically removed in a variety of ways. Etching is preferred where the layer of insulating material 20 is etched only vertically, with no undercuts or lateral etching.

Forming sidewall oxides is widely used in industry for numerous purposes. One purpose is to coat the sidewalls of conductive structures, such as the gates of MOS transistors, or to be used as spacers from vertical walls during ion implantation. One process for forming sidewall oxides is
Horngusse on October 26, 1982” / 7-(
) Iorng-3en Fu) Tj I given to others
It is described in detail in U.S. Pat. No. 4,356,040. Reference is made herein to this United States patent.

After forming the sidewall oxide layer 22,24, a thin refractory metallization layer 26 is sputter deposited onto the substrate to a thickness of approximately 500 nm. Preferably, the high melting point metal used is titanium. Next, nitrogen or NH3 is added to titanium.
Rapid thermal annealing (RTA) is performed in a cloud atmosphere. As a result, the titanium silicide layer (TiSi□) 28 is formed on the silicon substrate 1.
0 and near the location of the bottom 19 of the pier hole 14, a titanium nitride (TiN) layer 30 is formed on the remaining portion of the pier hole 14, on the outer surface of the sidewall layer 22, 24, and an oxide layer thereon. formed on the upper surface of 12.

Note that some of the titanium layer 26 combines with silicon to form a titanium silicide layer 28. On the other hand, nitrogen reacts with titanium to form titanium nitride. titanium layer 26
of titanium reacts in a nitrogen cloud to form titanium silicide, two competing reactions occur on the silicon. The first reaction is the formation of titanium nitride, which grows downward from the gas phase. In connection with the second reaction, titanium silicide grows upward from the interface with silicon.

Since the activation energies of these two competing reactions are different, the TiN/TiSi□ thickness ratio varies sensitively with temperature. However, as a result, the titanium nitride layer 3
A predetermined amount of T+N is formed in the portion of the titanium nitride layer 30 over the silicon, which is thinner than the portion over the oxide layer, which is the remaining portion of the titanium nitride layer 30. Both the titanium silicide layer 28 and the titanium nitride layer 30 are highly conductive materials, and the portions of the titanium nitride layer 30 and the titanium silicide layer 28 near the bottom 190 of the pier hole 14 form a barrier metal. ing. The method of forming titanium silicide layer 28 and titanium nitride layer 30 is illustrated in FIG. If a lower level conductor is present at the bottom 19 of the pier hole 14 and this lower level conductor does not contain silicon, the titanium silicide layer 2
Note that 8 is not formed. Titanium nitride layer 3
The purpose of 0 is to provide a barrier to interaction between later formed layers and underlying materials such as silicon. However, if the underlying extending material is a metal such as aluminum, it is necessary to sputter deposit TiN directly onto the surface of the aluminum instead of PTAing T1. For example, when metals are deposited directly onto silicon, "spiking" and "tunneling" can occur, phenomena well known to those skilled in the art.

After the barrier titanium nitride layer 30 is formed on the bottom 19 of the pier hole 14, a conformal conductive layer 32 is deposited over the titanium nitride layer 30 to a thickness of approximately 2,000 nm. Generally, a CVD method is used to form a conformal layer. In this example, tungsten disilicide (WSi2) is deposited by CVD.

Currently, among the various silicides, 'vVsi2 is the only material convenient for CVD deposition of conformal layers.

In contrast, sputtered materials such as aluminum, which become conductive layers, must be deposited by physical vapor deposition. Generally, this is an anisotropic process and coverage of vertical or near-vertical surfaces is poor. Therefore, it is important in the present invention to use a method such that a highly conductive layer is formed on the sidewalls within the pier hole 14. As will be explained in more detail below, the conductivity-critical portions of the conformal conductive layer 32 are adjacent to, but separated from, the outer surfaces of the sidewall oxide layers 22 and 24 by the titanium nitride layer 30. It is a part. In this way a conductive step is obtained. It is important to note that the conformality of the conductive layer 32 and the step coverage by this conductive layer 32 is enhanced by the use of sidewall layers 22,24 that act as "tapered spacers".

Although direct deposition of WSi2 by CVD is preferred, a variety of methods can be used to deposit highly conductive layers. For example, polycrystalline silicon, which is suitable for CVD methods, can be used, but its sheet resistance is relatively high, thus reducing the conductivity of the conductor. Another possible method is shown in Figures 6a and 6b. In FIG. 6a, the titanium layer 34 is deposited in vacuum at a temperature of about 100%.
It is deposited to a thickness of approximately 800° C. on the substrate. Next, a layer of doped or undoped polycrystalline silicon 36 is deposited by CVD to a thickness of approximately 1.50 nm.

Next, RTA is performed on the substrate at about 950° C. for about 30 seconds to form titanium silicide 28. The titanium silicide region is approximately 2.000-3.000 mm thick. Although titanium silicide was used in this example, any silicide such as Mo5iz, WSi, TaSi, etc. can be used. After the reaction to form titanium silicide, conductive layer 32 is formed using titanium silicide rather than tungsten silicide. It should be understood that problems due to non-conformity of films deposited by physical vapor deposition apply particularly to thick films. This problem is solved to some extent by depositing a thin film (eg Ti) by physical vapor deposition and then growing a film (eg poly) thereon by CVD.

Referring to FIG. 7, it can be seen that after formation of conductive layer 32, a metallization layer 38 is sputter deposited onto conductive layer 32. The metallization layer 38 is preferably sputter deposited aluminum to a thickness of approximately 5,000 to 8,000 Å. It can be seen that the portion of the aluminum layer 38 overlying the oxide layer 12 has a substantially constant thickness. However, the thickness of the portion resting on the pier hole 14 varies. This thickness change is due to the anisotropy of the sputter. In the drawings, the pier hole 14 is covered continuously, but blank areas may appear. The potential for voids is somewhat reduced due to the presence of the sidewall insulating layer 22.24, which has a tapered surface, and the conformal conductive layer 32, which also has a somewhat tapered surface rather than a sharp edge. Become. However, it is not important whether sharp edges or steps are present in the aluminum layer 38. This is because the electrically conductive connection to the bottom 19 of the pier hole 14 is realized by a homogeneous titanium nitride layer 30 and a homogeneous WSi2 layer 32. As explained above, in order to interconnect the metallized layer 38 and the silicon surface, or the metallized layer 38 and a conductor extending below, in the case of a conductor extending below, this conductor must be The only part that provides the necessary conductive interconnection with the conformal layer 30.32 is the part that extends from the upper level to the lower level. Therefore, this extension only needs to be present for the interconnection between the metallization layer 38 and the bottom 190 of the pier hole 14 to be reliable.

The horizontal plane of the titanium nitride layer 30 of the same shape and the 1vVsi□ layer 32 of the same shape are the metallized layer 38 and the bottom 19 of the peer hole 14.
Although not the main part of the conductive connection between the two, the horizontal surfaces end up making the metal system more resistant to electromigration.

In summary, the present invention provides a method for improving step coverage and reliability of peer holes/contact holes. This method involves forming sidewall oxide spacers formed on the vertical walls of the peer hole/contact hole;
Next, a barrier metallized layer is formed on the bottom of the peer hole/contact hole. A conformal layer of high melting point material such as silicide is then deposited over the structure to conformally cover the surfaces of the pier/contact holes, including the surfaces of the sidewall spacers. The sidewall spacer has a tapered surface that extends at an angle to the bottom of the pier/contact hole.

A metallization layer is then sputter deposited over the conformal layer so that the conformal layer provides a conductive connection between the upper and lower levels, solving the sputter step coverage problem. .

Although the present invention has been described in detail with respect to one embodiment, various changes, substitutions, and modifications may be made to the present invention without departing from the spirit and scope of the present invention as defined in the claims. can be applied.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a case where an oxide layer is formed on a silicon substrate or a metallized layer, and a contact hole/pier hole is provided in this oxide layer. FIG. 2 shows the structure of FIG. 1 with a thinner oxide layer formed thereon. FIG. 3 is a diagram of the structure of FIG. 2 with the upper oxide layer etched away to form sidewall oxide in the contact/pier holes. FIG. 4 is a diagram of the structure of FIG. 3 with a thin refractory metal layer formed thereon. FIG. 5 is a cross-sectional view of the structure of FIG. 4 having a high melting point metal transformed into a barrier layer of a high melting point material. FIG. 6 is a cross-sectional view of a high melting point material layer formed on the barrier layer of the structure shown in FIG. 5 by CVD. Figures 6a and 6b show an alternative method of forming the refractory material layer of Figure 6 by CVD, in which case a refractory metal layer is first formed over the structure of Figure 5. and then
A polycrystalline silicon layer is formed to form a silicide layer. FIG. 7 is a cross-sectional view of the structure of FIG. 6 in which a metallized layer is formed above the substrate by sputtering or physical vapor deposition. (Main reference numbers) IO... Semiconductor structure (silicon substrate, 12... Oxide layer (interlevel oxide), 14... Pier hole, 1
6.18...Side wall, 20...Insulating material layer, 22.24...Side wall oxide layer, 26...High melting point metallization layer (titanium layer), 28...Titanium silicide layer, 30...Titanium nitride layer , 32... conductive layer, 34... titanium layer, 36... polycrystalline silicon layer,

Claims (29)

[Claims] (1) To form a conductive interconnect between an upper level and a lower level conductive structure when the upper level and lower level of the semiconductor structure are partially separated by an insulating layer, Forming an opening of a predetermined size in the insulating layer between the lower levels, with sidewalls such that a portion of the conductive structure of the lower level that is to be connected to the upper level is exposed at the bottom of this opening. forming a thin conformal layer of conductive material on the sidewall extending from the conductive structure at the lower level to at least an upper level coplanar with the top surface of the insulating layer and in contact with the top surface of the conformal layer above the insulating layer; forming a thick metallization layer to form an upper level conductive structure interconnected with a lower level conductive structure. (2) further comprising the step of forming a sidewall insulating layer on a surface of a sidewall of the opening, the sidewall insulating layer comprising: a lower surface of the insulating layer;
2. The method of claim 1, wherein the insulating layer is thinned near the top surface. (3) The above step of forming the sidewall insulating layer forms an isomorphic layer of insulating material on the insulating layer in which the opening is formed and on the sidewall of the opening, and the insulating material layer is anisotropically formed. etching away non-substantially vertical portions, the anisotropic etching operation making the upper edge of the sidewall insulating layer thinner than the lower portions of the sidewall insulating layer; 3. A method according to claim 2, characterized in that: (4) the lower level conductive structure comprises a semiconductor material, and the method further comprises forming a barrier layer over the exposed regions of the lower level prior to forming the conformal layer of conductive material. The method according to claim 1. (5) The step of forming the conformal layer of conductive material includes depositing a conformal high melting point metal silicide layer over both the insulating layer and the opening by CVD. The method described in Section 1. (6) The method of claim 5, wherein the high melting point metal silicide is tungsten silicide. (7) forming a conformal refractory metal silicide layer, depositing a refractory metal layer conforming to the geometry on both the insulating layer and the opening; 2. The method of claim 1, further comprising: depositing a conformal polycrystalline silicon layer thereon; and annealing the refractory metal and the overlying polycrystalline silicon to bring the refractory metal into a silicide form. the method of. (8) The method according to claim 7, wherein the high melting point metal includes titanium. (9) to form conductive interconnects between upper and lower level conductive structures when the upper and lower levels of the semiconductor structure are partially separated by an interlevel oxide layer; forming an opening of a predetermined size in the interlevel oxide layer between the upper level and the lower level such that a portion of the conductive structure of the lower level that is to be connected with the upper level is exposed at the bottom of the opening; forming a sidewall insulating layer on the surface of the sidewall of the opening in the interlevel oxide layer to a predetermined thickness in the upper part than in the lower part near the lower level; forming a barrier layer over the exposed portion of the lower level; forming a conformal refractory metal silicide layer over the structure including the interlevel oxide layer, the sidewall insulating layer, and the barrier layer; A method comprising forming a metallization layer above the oxide layer and in contact with a refractory metal silicide layer to form an upper level conductive structure. 10. The method of claim 9, wherein the step of forming a conformal refractory metal silicide layer comprises depositing the refractory metal silicide by CVD. (11) The method according to claim 10, wherein the high melting point metal silicide includes tungsten silicide. (12) to form conductive interconnects between upper and lower level conductive structures when the upper and lower levels of the semiconductor structure are partially separated by an interlevel oxide layer; Forming an opening of a predetermined size in the interlevel oxide layer between the upper level and the lower level, exposing at the bottom of this opening a portion of the conductive structure of the lower level that is to be connected to the upper level. forming a sidewall insulating layer on the surface of the sidewall of the opening with a tapered profile whose width increases from the upper level to the lower level; A barrier layer is formed over the exposed portion of the structure, and a conformal refractory material layer is formed on the surface of the semiconductor structure to form a barrier layer on the sidewall insulating layer, the top surface of the interlevel oxide layer, and the lower level within the opening. forming a metallized layer over the interlevel oxide layer and in contact with the conformal layer to form the upper level conductive structure. how to. (13) forming a sidewall insulating layer includes depositing a conformal oxide layer over both the interlevel oxide layer and the opening to cover the sidewalls of the opening and the exposed portions of the interlevel oxide layer; covering both exposed portions of the lower level conductive structure within the opening and anisotropically etching the isomorphic oxide to remove portions of the isomorphic oxide layer that are not in the vertical plane; 13. The method of claim 12, wherein the anisotropic etching causes the oxide layer on the surface of the vertical sidewalls of the opening to taper to be thicker near the lower level than near the upper level. (14) forming a barrier layer includes forming a titanium nitride layer conforming to an interlevel oxide layer, a surface of a sidewall insulating layer, and an exposed surface of a lower level conductive structure; 13. The method according to claim 12. 15. The lower level conductive structure comprises silicon, and the method includes forming a titanium silicide layer at the junction of the titanium nitride layer and the exposed silicon within the opening. 14. The method described in 14. 16. The method of claim 12, wherein the step of forming a conformal layer comprises depositing a conformal layer of high melting point material by CVD. (17) forming a conformal layer comprises forming a conformal layer of refractory material over the structure to form a conformal layer of refractory material on top of the interlevel oxide layer and exposed surfaces of the sidewall insulating layer; , covering the exposed surface of the barrier layer in a conformal manner, forming a conformal polycrystalline silicon layer on the high melting point material layer, and reacting the polycrystalline silicon layer and the high melting point material layer to form a high melting point silicided material. 13. The method of claim 12, comprising the steps of: 18. The method of claim 12, wherein the high melting point material of the conformal layer is tungsten silicide. 19. The method of claim 12, wherein the step of forming a metal layer includes sputtering onto a layer of aluminum. (20) at the first and second levels, respectively;
a contact structure interconnecting two conductive structures, the portions of which are disposed on either side of the layer of insulating material, the contact structure being formed in the layer of insulating material between the first and second levels; an opening having sidewalls of; a conformal layer of refractory material deposited on a surface of the sidewall of the opening and extending from the first level conductive structure to the second level conductive structure; A contact structure comprising a deposited layer of refractory material at the second level as well as a metallization layer making a conductive connection with the conductive structure at the second level. (21) the sidewall of the opening is tapered from the second level to the first level, the opening having a larger size at the second level than at the first level; 21. The contact structure of claim 20. (22) The conformal layer of high melting point material comprises a conformal tungsten silicide layer.
Contact structure described in . (23) The contact structure according to claim 20, wherein the metallized layer includes sputtered aluminum. (24) interconnecting the conductive structure of the upper layer with selected regions of the lower extending silicon structure when the upper layer is partially isolated from the lower extending silicon structure by a layer of insulating material; a contact structure formed in an insulating layer between an upper layer and a surface of a selected region of a silicon structure and having a predetermined sidewall, the sidewall having a size in the upper layer greater than a size at the silicon surface; an opening having an increasingly tapered profile; a conformal refractory material layer deposited on the sidewall surfaces of the opening and extending from the silicon surface to the upper layer; and a conformal refractory material layer deposited on the top surface of the insulating material layer. A contact structure comprising a layer of refractory material and a metallization layer interconnecting the conductive structure of the upper layer. 25. The contact structure of claim 24, wherein the high melting point material layer extends over an insulating layer below the metallized layer and over the silicon surface within the opening. 26. The contact structure of claim 25 further comprising a barrier layer deposited between the silicon surface and the conformal layer. (27) further comprising a barrier layer deposited between the conformal layer of high melting point material and both the insulating layer and the portion of the silicon surface exposed by the opening. 25. The contact structure according to 25. 28. The contact structure of claim 24, wherein the conformal layer of high melting point material comprises tungsten silicide. 29. The contact structure of claim 20, wherein the conformal layer of high melting point material comprises titanium silicide.