JP2856418B2 - Contact forming method and structure - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention generally relates to a contact hole or a via hole used in a semiconductor process, and more specifically, to a step coverage of a contact hole or a via hole (step coverage state). For improving.

2. Description of the Related Art In semiconductor processing, one of the most important process steps is the different levels of 2 separated by insulating layers.
Interconnecting the two conductive layers. This interconnection is particularly important when one conductive layer is a top metallization layer. At present, the conductor layer extending downward is covered with an interlevel oxide layer (interlayer insulating layer), and a conductor hole formed in the oxide layer such as a contact hole or a via hole extends downward. Exposing selected areas of the layer. Next, the top conductor layer is patterned and interconnected with the conductor layer extending downward through contact holes or via holes. This conductor layer extending downward includes polycrystalline silicon or metal,
Further, a conductive layer composed of the silicon surface itself is included.

To achieve a conductive connection between the two layers, the resistance of the interface of the contact with the underlying metal or silicon is low, and the properties of the underlying material, especially the material It is important that the characteristics do not change in the case of. Furthermore, it is important that the resistance between the contact interface itself and the upper metallization layer be small.

One disadvantage of the conventional process is the "void" of the upper metallization layer on the vertical surface of the contact opening or via hole. This can occur for a number of reasons. One industrially common cause is that the coating does not conform when depositing the metallized layer using sputtering or physical vapor deposition. Here, “same shape” is referred to as “the coating state of the film is faithful to the
nformal) ". Since these methods are anisotropic processes, the vertical surface in the contact opening or via hole only has a relatively thin metallized layer formed on the surface of the vertical wall surface, and the contact opening or via hole is not formed. A thick “bulge” is formed along the upper edge. Voids in the metallized layer generally occur along this vertical plane.
This problem is solved by depositing a conductive material by a CVD method. However, usually, the CVD method is not suitable for the type of metal required at the upper level,
For example, it is not suitable for aluminum metallization processes.

SUMMARY OF THE INVENTION The invention disclosed and claimed herein includes a method of connecting between two different levels of a conductive layer. A silicon substrate or first conductive layer forms a lower level of conductive material. This layer of conductive material is covered by an interlevel oxide layer. An opening is formed in the interlevel oxide layer, and then a conformal layer of refractory material is deposited over the structure to cover the sidewalls of the opening with a uniform thickness. As a result, the two levels separated by the interlevel oxide layer conduct. Next, a metallized layer is sputtered on top to establish an interconnect between the upper portion of the refractory material layer and the upper level of other structures.

According to another aspect of the invention, the refractory material is deposited on the entire substrate and extends over the surface of the interlevel oxide layer and over the bottom of the opening near the lower level. A barrier metal is deposited between the conformal refractory material layer and the lower conductive level.

According to yet another aspect of the invention, a sidewall oxide layer is formed with a tapered profile on sidewalls of the opening.
The tapered profile extends from the lower level narrow portion to the upper level wide portion such that the opening at the upper level is wider. As a result, a step that is slower than in the related art is obtained, and a refractory material layer having the same shape is formed thereon. Preferably, the high melting point material is tungsten disilicide.

For a more complete understanding of the present invention and its advantages, reference is made to the accompanying drawings.

EXAMPLE Referring to FIG. 1, an interlevel oxide 12 is formed over a semiconductor structure 10. Semiconductor structure 10
Is preferably silicon. However, in describing the present invention, it is assumed that semiconductor structure 10 represents a first level conductor. This will be described in detail later.

Oxide layer 12 is commonly referred to as an interlevel oxide or interlayer insulation layer and has a thickness of about 5,000-10,000 °. Oxide layer 1
After forming 2, contact holes or via holes 14
Is formed in the oxide layer 12. In the following description, the via hole 14 will be described. As you can see from the cross section, the via hole
14 has two vertical side walls 16 and 18. The via holes 14 are formed by patterning the surface of the oxide layer 12 by performing a photoresist operation, and then performing anisotropic plasma etching on the structure to remove oxide in unmasked regions, As a result, vertical side walls 16 and 18 are formed.

After the formation of the via hole 14, the via hole 14 and the oxide layer
Depositing a conformal layer of insulating material 20 on top of the vertical sidewalls 16
And 18 as well as the bottom surface 19 of the contact hole / via hole. The insulating material layer 20 preferably includes deposited silicon oxide or silicon nitride. This insulating material layer 20 can be deposited by a conventional low-temperature reaction process using a CVD method. The insulating material layer 20 can have a thickness of several thousand mm. The preferred thickness is 2,000 mm. As explained above, the insulating material layer 20 conforms to the geometry of the via hole 14 and adheres to the vertical sidewalls 16 and 18.

As shown in FIG. 3, the insulating material layer 20 is removed anisotropically, and the sidewalls 16 and 18 have relatively thick oxide layers 22 and 24, respectively.
Covered with. For example, when the thickness of the insulating material layer 20 is 2,
000 mm, the lateral thickness of the sidewall oxide layers 22 and 24 is about 2,000 mm near the bottom surface 19 and the insulating material layer 2
Near the top of 0, it is slightly thinner. Thus, sidewall oxide layers 22 and 24 have a tapered surface rather than a vertical surface. As will be explained later, this results in a conductive layer having a “rounded” surface in the via hole 14.

The insulating material layer 20 can be removed anisotropically in various ways. Preferably, the etching is performed so that the insulating material layer 20 is etched only in the vertical direction so that there is no undercut or lateral etching. Forming sidewall oxides is widely used in the industry for a number of purposes. One purpose is to cover the side walls of a conductive structure such as the gate of a MOS transistor, or to use it as a spacer from a vertical wall surface during ion implantation. One process for forming sidewall oxides is described in detail in US Pat. No. 4,356,040, issued to Horng-Sen Fu et al. On Oct. 26, 1982. Reference is made herein to this United States patent.

After forming the sidewall oxide layers 22, 24, a thin refractory metallization layer 26 is deposited on the substrate by sputtering to a thickness of about 500 °. The refractory metal used is preferably titanium. Next, rapid thermal annealing (RTA) is performed on the titanium in a nitrogen or NH ₃ atmosphere. As a result, a titanium silicide layer (TiSi ₂ ) 28 is formed on or below the surface of the silicon substrate 10 and near the position of the bottom 19 of the via hole 14,
A titanium nitride layer (TiN) 30 is formed over the remainder of the via hole 14, on the outer surfaces of the sidewall layers 22, 24, and on the upper surface of the oxide layer 12. Note that some of the titanium layer 26 combines with the silicon to form titanium silicide layer 28.
On the other hand, nitrogen reacts with titanium to form titanium nitride.
When the titanium of the titanium layer 26 reacts in a nitrogen atmosphere to form titanium disilicide, two competing reactions occur on the silicon. The first reaction is the formation of titanium nitride, which grows downward from the gas phase. In the context of the second reaction, titanium silicide grows upward from the interface with silicon. Since the activation energies of the two competing reactions are different, the thickness ratio of TiN / TiSi ₂ changes sensitively with temperature. However, as a result, a predetermined amount of TiN is formed in a portion of the titanium nitride layer 30 on silicon which is thinner than a portion of the titanium nitride layer 30 on the oxide layer. Both the titanium silicide layer 28 and the titanium nitride layer 30 are highly conductive materials, and the portion of the titanium nitride layer 30 and the titanium silicide layer 28 near the bottom 19 of the via hole 15 forms a barrier metal. doing. The method of forming the titanium silicide layer 28 and the titanium nitride layer 30 is the fifth.
It is shown in the figure. Note that if a lower level conductor is present at the bottom 19 of the via hole 14 and the lower level conductor does not contain silicon, the titanium silicide layer 28 will not be formed. The purpose of the titanium nitride layer 30 is to
The purpose is to provide a barrier to interaction between subsequently formed layers and underlying material such as silicon. However, when the material extending downward is a metal such as aluminum, it is necessary to deposit TiN directly on the surface of aluminum by sputtering instead of performing RTA treatment on Ti. For example, if metal is deposited directly on silicon, phenomena known as "spiking" and "tunneling" may occur.

After forming a barrier titanium nitride layer 30 at the bottom 19 of the via hole 14, a conductive layer 32 of the same shape is formed on the titanium nitride layer 30 to a thickness of about 30 nm.
Deposit to 2,000Å. In general, to form a conformal layer C
The VD method is used. In this embodiment, tungsten disilicide (WSi ₂ ) is deposited by a CVD method. At present, among various silicides, WSi ₂ has CV
It is the only material that is convenient for depositing by the D method. Conversely, a sputtered material such as aluminum, which will be the conductive layer, must be deposited by physical vapor deposition. In general,
This is an anisotropic process, with poor coverage on vertical or nearly vertical surfaces. Therefore, it is important in the present invention to use a method in which a highly conductive layer is formed on the side wall in the via hole 14. As will be described in more detail below, the portion of the conformal conductive layer 32 that is important for conductivity is adjacent to the outer surfaces of the sidewall oxide layers 32 and 24, but is isolated therefrom by the titanium nitride layer 30. Part. In this way, a conductive step is obtained. The isomorphism of the conductive layer 32 and the step coverage by the conductive layer 32 indicate that the side wall layers 22 and 24 function as “tapered spacers”.
It is important to note that the use of

Nevertheless be directly deposited WSi ₂ is preferably a CVD method, it is possible to deposit a large layer of highly conductive by using a variety of methods. For example, polycrystalline silicon suitable for the CVD method can be used, but its sheet resistance is relatively high, thus reducing the conductivity of the conductor. Another method available is shown in FIGS. 6a and 6b. In FIG. 6a, a titanium layer 34 is deposited in vacuum at a temperature of about 100 ° C. on the substrate to a thickness of about 800 °. Next, a doped or undoped polysilicon layer 36 is deposited by CVD to a thickness of about 1,500 °. Next, apply RTA to the substrate about 95
Perform for about 30 seconds at 0 ° C. to form titanium silicide 28. The titanium silicide region is about 2,000-3,000 mm thick. In this example, titanium silicide was used, but any silicide,
For example, MoSi ₂ , WSi ₂ , or TaSi ₂ can be used. After the reaction for forming titanium silicide, the conductive layer 32 is formed using titanium silicide instead of tungsten silicide. It should be understood that the problems arising from non-uniform films deposited by physical vapor deposition apply particularly to thick films. The problem is that thin films (eg Ti)
Is solved to some extent by depositing by physical vapor deposition, and then growing a film (eg, poly) by CVD on it.

Referring to FIG. 7, it can be seen that after the formation of the conductive layer 32, the metallized layer 38 is deposited on the conductive layer 32 by sputtering. The metallized layer 38 is sputtered to a thickness of about 5,000
Preferably, it is aluminum deposited between 0 and 8,000 °. It can be seen that the aluminum layer 38 has a substantially constant thickness at the portion on the oxide layer 12. But,
The thickness of the portion on the via hole 15 changes. This change in thickness is due to the anisotropy of the sputter. In the drawing, the via hole 14 is continuously covered, but a blank portion may appear. The potential for voids is somewhat smaller due to the presence of the sidewall insulating layers 22, 24 having a tapered surface and the same shaped conductive layer 32 also having a somewhat tapered surface rather than sharp edges. Become. However, it is not important whether sharp edges or steps are present in the aluminum layer 38. This is because the conductive connection to the bottom 19 of the via hole 14 is a titanium nitride layer
This is because it is realized by the WSi _double layer 32 having the same shape as 30. As explained above, the metallization layer 38 and the silicon surface,
Alternatively, to interconnect the metallized layer 38 and the downwardly extending conductor, consider the case of the downwardly extending conductor, which provides the necessary conductive interconnection with the conformal layers 30, 32. The only part is the part extending from the upper level to the lower level. Therefore, this extension only needs to be present in order for the interconnection between the metallization layer 38 and the bottom 19 of the via hole 14 to be reliable.

The horizontal plane of the conformal titanium nitride layer 30 and the conformal WSi ₂ layer 32 is not a major part of the conductive connection between the metallization layer 38 and the bottom 19 of the via hole 14, but in the end the horizontal plane has a better resistance to electromigration. It is a metal system with a characteristic.

In summary, the present invention provides a method for improving step coverage and reliability of via holes / contact holes. In this method, a sidewall oxide spacer formed on a vertical wall surface of a via hole / contact hole is formed, and then a barrier metallization layer is formed on the bottom surface of the via hole / contact hole. Next, a conformal layer of a refractory material, such as a silicide, is deposited over the structure to conformally cover the surface of the via hole / contact hole, including the surface of the sidewall spacer. The sidewall spacer has a tapered surface extending at a predetermined angle with respect to the bottom surface of the via hole / contact hole. Next, a metallization layer is sputter deposited over the conformal layer such that the conformal layer provides a conductive connection between the upper and lower levels, thereby solving the problem of sputter step coverage. .

Although the present invention has been described in detail with reference to one embodiment, various modifications to the present invention can be made without departing from the spirit and scope of the present invention as defined in the appended claims.
Substitutions and modifications can be made.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a case where an oxide layer is formed on a silicon substrate or a metallized layer, and a contact hole / via hole is formed in the oxide layer. FIG. 2 shows a state in which a thinner oxide layer is formed on the structure of FIG. FIG. 3 is a view showing a state in which an oxide layer above the structure of FIG. 2 has been removed by etching to form a sidewall oxide in a contact hole / via hole. FIG. 4 is a view showing a state in which a thin refractory metal layer is formed on the structure of FIG. FIG. 5 is a cross-sectional view showing a state where the structure of FIG. 4 having a high melting point metal is converted into a barrier layer made of a high melting point material. FIG. 6 is a sectional view showing a state in which a high melting point material layer is formed on the barrier layer having the structure of FIG. 5 by the CVD method. 6a and 6b illustrate another method of forming the refractory material layer of FIG. 6 by a CVD method, in which a refractory metal layer is first formed on the structure of FIG. A polycrystalline silicon layer is then formed to form a silicide layer. FIG. 7 is a cross-sectional view showing a state where a metallized layer is formed above the substrate by sputtering or physical vapor deposition in the structure of FIG. (Main reference numbers) 10: Semiconductor structure (silicon substrate), 12: Oxide layer (interlevel oxide), 14: Via hole, 16, 18: Side wall, 20: Insulating material layer, 22, 24: Side wall oxide layer, 26: High melting point metallized layer (titanium layer), 28: Titanium silicide layer, 30: Titanium nitride layer, 32: Conductive layer, 34: Titanium layer, 36 ... Polycrystalline silicon layer, 38 Metallized layer (aluminum layer)

──────────────────────────────────────────────────の Continued on the front page (72) Mohammed M. Inventor. Farahani United States Texas Carrollton Big Canyon Trail 1710 (72) Inventor Yu Pin Han United States Texas Dallas Scottia 7701 (56) References JP-A-63-176476 (JP, A) JP-A-59-222943 (JP, A) JP-A-63-250172 (JP, A) JP-A-63-132456 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 21/28-21/288 H01L 21 / 3205 H01L 21/3213 H01L 21/44-21/445 H01L 21/768 H01L 29/40-29/51

Claims (20)

(57) [Claims] 1. A method for forming a contact to a semiconductor integrated circuit device, comprising: an insulating layer (12) on a conductive silicon region (10). Forming an opening (14) in the insulating layer to expose a portion (19) of the conductive silicon region, wherein the opening has substantially vertical sidewalls (16, 18). Forming an insulating conformal layer (20) over the insulating layer and the opening; anisotropically etching the insulating conformal layer along the vertical sidewalls of the opening; Forming a sidewall spacer region (22, 24) and exposing the conductive silicon region, the sidewall spacer region being larger adjacent to the conductive silicon region than on the upper surface of the insulating layer. Thick having thickness Forming a refractory metal layer (26) on the insulating layer, the side wall spacer region, and the exposed conductive silicon region; and heating the device in a nitrogen atmosphere. Converting the melting point metal layer into a high melting point metal silicide (28) on the exposed conductive silicon region and converting the remainder into a high melting point metal nitride (30); Forming a conductive homogenous layer (32) containing a high melting point metal, and forming an aluminum layer (38) on the conductive homogenous layer. 2. The method according to claim 1, further comprising the step of: after forming the aluminum layer,
Patterning the aluminum layer to define an interconnect. 3. The method of claim 1, wherein the step of forming the conductive conformal layer includes the following steps.
Or the method according to (2): depositing tungsten silicide on the refractory metal nitride (30) using chemical vapor deposition. 4. The method according to claim 1, wherein the step of forming the conductive isomorphous layer comprises the following steps: Depositing a second refractory metal layer on the second refractory metal, depositing a polycrystalline silicon layer on the second refractory metal, and heating the apparatus in a nitrogen atmosphere. Converting the polycrystalline silicon and the second refractory metal layer to a refractory metal silicide layer (32). 5. The method according to claim 1, wherein the refractory metal layer is a titanium layer. 6. The method according to claim 4, wherein said second refractory metal layer comprises titanium. 7. The method according to claim 1, wherein said conductive conformal layer of said refractory metal has a substantially uniform thickness.
The method according to any one of (6). 8. The method according to claim 1, wherein said refractory metal silicide contains titanium silicide.
The method according to any one of (7). 9. The method according to claim 1, wherein said refractory metal nitride comprises titanium nitride. 10. An aluminum layer (38) rests on said conductive isomorphous layer (32) above said insulating layer, and a conductive connection is formed from said conductive silicon region (10) to said high melting point. A metal silicide layer (28), the refractory metal nitride layer (3
0) and the aluminum layer (3
The method according to any one of claims (1) to (9), characterized in that it is made to reach (8). 11. An integrated circuit, comprising: a first level silicon conductor (10) separated by an insulating layer (12);
An opening (14) having substantially vertical side walls (16, 18) and extending through said insulating layer, said structure being for connecting a level metal conductor (38); An opening (14) for exposing a part (19) of the first-level conductor to the opening, covering a side wall of the opening, and being adjacent to the first-level silicon conductor; Insulating sidewall spacer regions (22,2) having a greater thickness than on the top surface of the insulating layer
4) a refractory metal silicide layer (28) covering the exposed portion of the first level silicon conductor, the refractory metal silicide layer, the sidewall spacer region, and a part of the upper surface of the insulating layer. A refractory metal nitride layer (30) covering the second melting point, and a conductive isomorphous layer (32) covering the high melting point metal nitride layer (30) and containing the refractory metal. The structure, wherein the metal conductor includes an aluminum layer covering the conductive conformal layer. 12. The structure of claim 11, wherein said conductive conformal layer comprises a refractory metal silicide. 13. The structure of claim 12, wherein said conductive conformal layer comprises tungsten disilicide. 14. The structure of claim 12, wherein said conductive conformal layer (32) comprises titanium silicide. 15. The refractory metal silicide (28) comprises titanium silicide.
The structure according to any one of (14). 16. The structure according to claim 11, wherein said refractory metal nitride (30) comprises titanium nitride. 17. The second level conductor (38) rests on a conductive conformal layer (32) above the insulating layer (12) and the conductive connection is away from the one level conductor. The second level conductor (38) passing through the refractory metal silicide layer (28), the refractory metal nitride layer (30) and the conductive conformal layer;
Claim (1)
Structure according to 1). 18. The method according to claim 11, wherein said conductive conformal layer comprises a refractory metal silicide having a substantially uniform thickness. Structure described in. 19. A structure for connecting a first level silicon conductor and a second level metal conductor separated by an insulating layer in an integrated circuit, the structure having substantially vertical sidewalls, An opening extending through the layer, such that a portion of the first level conductor is exposed to the opening; and a key covering the exposed portion of the first level conductor. A titanium nitride layer, the titanium silicide layer, a titanium nitride layer covering the side wall of the opening and a part of the upper surface of the insulating layer, and a titanium nitride layer having a substantially uniform thickness and covering all the titanium nitride layer. Wherein the second level conductor rests on the conductive isomorphous layer above the insulating layer, and wherein the conductive connection is from the one level conductor; The titanium silicide layer, the titanium nitride Through the layer and the conformal layer, characterized in that it is made to reach to the second level of conductor structures. 20. In an integrated circuit, a structure for connecting a first level silicon conductor and a second level metal conductor separated by an insulating layer, the structure having tapered sidewalls, An opening extending through the layer, such that a portion of the first level conductor is exposed to the opening; and a key covering the exposed portion of the first level conductor. A titanium nitride layer, the titanium silicide layer, a titanium nitride layer covering the side wall of the opening and a part of the upper surface of the insulating layer, and a titanium nitride layer having a substantially uniform thickness and covering all the titanium nitride layer. Wherein the second level conductor rests on the conductive isomorphous layer above the insulating layer, and wherein the conductive connection is from the one level conductor; The titanium silicide layer, the nitriding Through the monolayer and the conductive isomorphic layer, characterized in that it is made to reach the second level of conductor structures.