JPH02287969A - Information signal reproducing device - Google Patents

Abstract

PURPOSE:To read out a compression sound signal even in case of erroneous detection of a flag by holding an address at the end of a compression signal written after stopping the output of count-down signal. CONSTITUTION:When a write to a memory 33 is normally performed until a sector 1, an address at the end of a compression sound signal of the sector 1 is outputted by a final address holding circuit 10 in detecting an end flag. Then, a start flag detecting signal (b) of a sector 2 is outputted to a write address counter control circuit 55 by a start flag detecting circuit 53. A count-up signal (d) to rise after a prescribed time lag from the input of the signal (b) is outputted by the circuit 55, and the sector 2 is written in the memory 33, while the signal (d) falls, and simultaneously the write to the memory 33 is stopped. The compression signal of sectors 0 and 1 can be reproduced by reading the first address of the write through the address to be outputted by the circuit 10, and even when an erroneous detection takes place, the read can securely be carried out until the final sector written in the memory 33 with accuracy.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an information signal reproducing apparatus for reproducing time-base compressed audio signals recorded on a magnetic disk such as a video floppy recorder.

Conventional technology In recent years, 2-inch floppy disks (hereinafter referred to as video floppies) have been used instead of cameras that use film.
A video floppy recorder that records still images has been commercialized, and it is expected that in the future, a function to record audio signals as well as still images for a predetermined period of time will be added, and a variety of products will be produced.

The information signal reproducing apparatus as described above will be described below with reference to the drawings.

FIG. 7 is a block diagram showing a video floppy audio recording device as an example of a device for recording and reproducing a time-base compressed audio signal, and FIG. 8 shows a recording format of the audio signal. Same figure (
5A is a diagram showing a track format, FIG. 3B is a diagram showing a sector format, and FIG. Further, FIG. 9 is a block diagram of the video floppy audio reproducing apparatus, and FIG. 10 is a waveform diagram showing waveforms of each part.

This will be explained below using FIG. 7.

As is well known, the video floppy 40 has 50 concentric tracks extending from the outer circumferential side to the inner circumferential side, and a video signal (still image) or an audio signal is recorded on each track. Also, the rotation speed of the video floppy 40 is 3 G OO
r pml In other words, since it rotates once every 1/GO seconds, a video signal is compressed into one field on each track, and an audio signal is compressed into 1/60 seconds on the time axis and recorded. Three modes are available for the time axis compression ratio of the audio signal: 320x, 0,640x - 1,280x, and each mode has approximately 5x compression per track.
It is possible to record audio signals of seconds, about 10 seconds, and about 20 seconds.

As shown in FIG. 7, the audio signal is filtered through a low-pass filter (L
After band-limiting by Pri') 30, the signal is input to the time axis conversion circuit 31.

The time axis conversion circuit 31 is well known, and includes, for example, an A/D converter 32 that converts an analog audio signal into a digital signal.
, a memory 33 for storing digital signals, and a D/A converter 34 for converting the digital signals into analog signals.

The signal input to the time axis compression circuit 31 is converted into a digital signal by the A/D converter 32. Thereafter, it is written into the memory 33 at the write clock frequency fw. After this writing is completed, it is read out at the read clock frequency fr, and converted into an analog signal by the D/A converter 34. The time axis conversion rate Kc of the time axis conversion circuit 31 is
It is expressed by the following formula.

Kc:fw/fr When Kc<1, the time axis conversion circuit 31 operates as a time axis compression circuit, and when Kc>1, the time axis conversion circuit 31 operates as a time axis expansion circuit.

During recording, the time axis conversion surface path 31 operates as a time axis compression circuit and outputs a compressed audio signal whose time axis has been compressed to 11 GO seconds. A control code and flags (start flag and end flag) are added to this compressed audio signal by an adder 35. Thereafter, the signal passes through a pre-emphasis circuit 3B, an FM modulation circuit 37, and a recording amplifier 38, and is recorded on a video floppy 40 by a magnetic head 39.

Next, the recording format of the audio signal will be explained using FIG. FIG. 5A is a diagram showing the track format. DSP stands for Data Start Point. The compressed audio signal is divided into four sectors and recorded with spaces inserted between each sector. Figure (b) and (
C) is a diagram showing a sector format. The start flag and end flag indicate the beginning and end of a sector, and serve as a time axis reference when reproducing a compressed audio signal. In addition, the control code is the information that the audio signal has (
For example, the track number where the corresponding video signal was recorded,
(time axis compression ratio, track number where the next compressed audio signal is recorded, etc.), and the same control code is recorded in each sector of the same track. The same compressed audio signal as the last part of the compressed audio signal of the previous sector is recorded in the overlap. Furthermore, although the start flag is a positive signal in FIG. 8(b), it becomes a negative signal when, for example, no compressed audio signal is recorded in this sector. Also, the end flag is a negative signal, for example,
When the recording of the compressed audio signal ends in this sector and does not continue to the next sector, it becomes a positive signal.

That is, the polarity of these two flags represents the sector type. There are four types of sectors: Type 1 follows the next sector on the same track, Type 2 follows sector O on the next track, Type 3 follows the last sector in the sequence, and Type 4 follows the next sector on the same track. Indicates an unused sector.

The reproduction operation of a compressed audio signal recorded in the above format will be explained with reference to FIGS. 9 and 10. In addition, the 9th
In the figure, circuits that operate in the same way as in FIG. 7 are given the same reference numerals.

In the figure, 40 is a video floppy, 50 is a magnetic head, 5
1 is a reproduction amplifier, and 52 is a demodulation circuit.

31 is the time axis conversion circuit mentioned earlier, which includes an A/D converter 32 that converts an analog signal into a digital signal, a memory 33 that stores the digital signal, and a D/A converter that converts the digital signal into an analog signal. 34, and operates as a time axis expansion circuit during playback. 33
a is a data input terminal, 33b is a write address terminal, 33
C is a read/write terminal, 33d is a continuous address terminal,
33e is a data output terminal. When a high level signal is input to the read/write terminal 33c, the memory 33 writes the data input to the data input terminal 33a to an address specified from the write address terminal 33b. Further, when a low level signal is input to the read 1 write terminal 33c, the data written to the address specified from the successive address terminal 33b is output to the data output terminal 33e.

53 is a start flag detection circuit, and 54 is a start flag detection circuit. In this format, since the edge of the flag is the time reference for the start and end of the compressed audio signal, the trailing edge of the flag is detected, and the start flag detection signal (Figure 10 (b)) and the end flag are detected. A detection signal (FIG. 10(C)) is output.

55 is a write address counter control circuit, which receives the start flag detection signal (b) and end flag detection signal (C) as input, and delays by a predetermined period (for example, T y + Ta) from the input of the start flag detection signal (b). It outputs a count-up signal (FIG. 10(d)) which rises with the input of the end flag detection signal (C) and falls with the input of the end flag detection signal (C).

While this count-up signal (d) is input to the read/write terminal 33c, the memory 33 performs a write operation. In addition, at the same time as the end flag detection signal (C) is input, a countdown signal with a pulse width T6 (Fig. 10(e)
)).

The write address counter 56 inputs the count up signal (d) and count down signal (e) which are the outputs of the write address counter control circuit 55, and outputs them to the write address terminal 33b, thereby writing data into the memory 33. It specifies an address.

58a is a count-up terminal, and 56b is a count-down terminal. While the count-up signal (d) is input to the count-up terminal 5θa, the write address is increased, and the count-down signal (e) is input to the count-down terminal 58b. The write address is decreased while the

57 is a successive address counter control circuit, and 58 is a successive address counter. Read address counter control circuit 5
7 inputs the output of the write address counter 56 and the output of the read address counter 58, and controls the successive address counter 58 so that the output of the read address counter 58 counts up until it reaches the address output by the write address counter 58. control. Read address counter 5
By inputting the output of 8 to the read address terminal 33d, one subsequent address is defined in the memory 33.

59 is a reproduction signal processing circuit which receives the output of the D/A converter as an input.

Next, the circuit operation of FIG. 9 is shown in the waveform diagram (a) of FIG. 10.
This will be explained with reference to (f).

During reproduction, the output of the magnetic head 50 passes through a reproduction amplifier 51 and is subjected to FM demodulation and de-emphasis by a demodulation circuit 52. First, the demodulated reproduced signal of sector 0 (a)
is input to the time axis conversion circuit 31, converted into a digital signal by the A/D converter 32, and output to the memory 33.

Further, this reproduction signal (a) is transmitted to the start flag detection circuit 5.
3. It is also input to the end flag detection circuit 64 at the same time.

The start flag detection circuit 53 detects the trailing edge of the start flag of sector 0 and outputs the start flag detection signal (
b) is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (for example, T t +
T Self) Count-up signal that rises with a delay (d)
Output. By outputting the count up signal (d),
The write address counter 56 starts counting up, and the memory 33 starts a write operation.

Then, the end flag detection surface path 54 detects the sector O.
When the trailing edge of the end flag is detected and the end flag detection signal (C) is input to the write address counter control circuit 56, the count up signal (d) falls, the write address counter 5θ stops, and memory 3
The write operation in step 3 also stops.

Since the count-up signal (d) is output to the last edge of the end flag, at the time of detecting the end flag,
The pedestal section and end flag after the compressed audio signal are written into the memory 33.

However, when the write address counter control circuit 55 receives the end flag detection signal (C), it outputs a countdown signal (e) with a pulse width of T. This countdown signal (e) causes the write address counter 56 to
Countdown for 6 seconds.

T6 is the period from the end of the compressed audio signal determined by the format to the rear edge of the end flag (see Figure 8 (C)), and by this countdown, the write address is set to the end of the compressed audio signal. Return to address. Furthermore, by writing the start end of the compressed audio signal of the sector from this address, the unnecessary pedestal portion and end flag written in the memory 33 are eventually removed.

Similarly, the compressed audio signals from sector O to sector 3 are continuously written into the memory 33 without duplication.
After completing writing from sector O to sector 3, write address counter 56 outputs address E.

Reading out the compressed audio signal written in the memory 33 is as follows:
The first address written (atto in Figure 10(f),
address A) to the address finally output from the write address counter 56 (address E in FIG. 10(f)) at the read clock frequency fr. Output.

The audio signal converted into analog by the D/A converter 34 is reproduced by a reproduction processing circuit 59 and outputted from an output terminal 60.

Problems to be Solved by the Invention However, in the conventional configuration described above, reading from the memory 33 is performed until the address finally output from the write address counter 56 is read. Therefore, if a count-up signal is output due to detection of a start flag, such as when an end flag is detected incorrectly, and the write address counter 56 is already operating, the output of the write address counter 56 will be This is different from the end address of the compressed audio signal of the sector written to the memory, and if an end flag detection error occurs, it is not known to which address the compressed audio signal has been written, that is, how far it can be read, and the memory The problem was that it was extremely difficult to read data from.

The present invention solves the above-mentioned conventional problems, and even if a flag is detected incorrectly, the compressed audio signal up to the sector that can be written to the memory without erroneously detecting the flag is accurately read out. The purpose of the present invention is to provide a signal reproducing device that can perform the following functions.

Means for Solving the Problems In order to solve the above problems, the information signal reproducing device of the present invention demodulates and demodulates an information signal recorded in a sector area, with a start flag added to the start end side and an end flag added to the end side. demodulation means for obtaining a signal; memory means for receiving the output of the demodulation means and temporarily storing only the information signal from the demodulated signals of the plurality of sector areas; and writing only the information signal in the memory means. write address control means for sequentially increasing or decreasing the write address of the memory means, and detecting and holding the end write address of the information signal to be written in the memory means by detecting the end flag; final address holding means for updating a held address by detecting a write address at the end of the information signal; The apparatus includes successive address control means for sequentially increasing the read address of the memory means so as to read from the memory means, and reproduction processing means for inputting the output of the memory means and performing reproduction processing.

Effect of the Invention With the above configuration, the present invention makes it possible to always hold the end write address of the compressed audio signal of the previous sector when writing to the memory. For this,
Even if the demodulated signal is disturbed due to noise, etc. and a flag is detected incorrectly, by reading up to the end write address of the compressed audio signal in the previous sector, compression can be performed up to the sector that was correctly written to the memory. It becomes possible to read the audio signal.

EXAMPLE A first example of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a video floppy audio reproducing apparatus according to a first embodiment. In FIG. 1, circuits that operate in the same way as in FIGS. 7 and 9 are designated by the same reference numerals.

31 is the time axis conversion circuit mentioned earlier, which includes an A/D converter 32 that converts an analog signal into a digital signal, a memory 33 that stores the digital signal, and a D/A converter that converts the digital signal into an analog signal. 34, and operates as a time axis expansion circuit during playback. 33a
is a data input terminal, 33b is a write address terminal, 33c
is a read/write terminal, 33d is a continuous address terminal, 3
3e is a data output terminal. The memory 33 has a read/write function.
When a high level signal is input to the write terminal 33c, the data input to the data input terminal 33a is written to the address of the write address terminal 33b. Furthermore, when a low level signal is input to the read/write terminal 33c, the data written to the address of the successive address terminal 33b is output to the data output terminal 33e.

53 is a start flag detection circuit, and 54 is a start flag detection circuit. In this format, the edge of the flag is the time reference for the start and end of the compressed audio signal, so the trailing edge of the flag is detected, and the start flag detection signal (Figure 2 (b)) and end flag are detected. Detection signal (
Figure 2 (C)) is output.

55 is a write address counter control circuit, which receives the start flag detection signal (b) and end flag detection signal (e) as input, and which receives the start flag detection signal (b) after a predetermined period of time (for example, T7↓T3) after the input of the start flag detection signal (b). It outputs a count-up signal (FIG. 2(d)) which rises and falls with the input of the end flag detection signal (C). Yo...
If the start flag detection signal (b) and end flag detection signal (g) are input accurately, the count up signal (d
) is output for a period of T4+T8. However, if a detection error occurs in the end flag, an amount greater than Ta+Ta will be output. Therefore, the count up signal (
d) maximum output period (e.g. maximum T 4 + T 2
+ T s ). This count up signal (
d) is input to the read/write terminal 33c, the memory 33 performs a write operation.

Further, the write address counter control circuit 55 outputs a countdown signal (FIG. 2(e)) having a pulse width T6 at the same time as the end flag detection signal (C) is input.

The write address counter 56 inputs the count up signal (d) and count down signal (e) which are the outputs of the write address counter control circuit 55, and outputs them to the write address terminal 33b, thereby writing to the memory 33. It specifies an address.

58a is a count-up terminal, and 56b is a count-down terminal. While the count-up signal (d) is input to the count-up terminal 58a, the write address is increased, and the count-down signal (e) is input to the count-down terminal 56b. The write address is decreased while the

10 is a final address holding circuit which is a feature of the present invention. The final address holding circuit 1o receives the outputs of the write address counter control circuit 55 and the write address counter 56 as input, and receives the output of the write address counter 56 after the output of the countdown signal (e) is stopped, that is, the written address. The end write address of the compressed signal is held and output to the read address counter control circuit 57. The output is held until the end write address of the compressed audio signal of the next sector is detected. Further, the initial value of the final address holding circuit 10 is assumed to be the address first written into the memory 33 (in this embodiment, address A in FIG. 2(g)).

57 is a read address counter control circuit, and 58 is a read address counter. Successive address counter control circuit 5
7 inputs the output of the successive address counter 58 and the output of the final address holding circuit 10, and controls the successive address counter 58 so that it counts up until the output of the read address counter 58 reaches the address output by the final address holding circuit 10. Control. Successive address counter 58
specifies a read address in the memory 33 by inputting it to the successive address terminal 33d.

590 is a reproduction signal processing circuit which receives the output of the D/A converter as an input.

Next, the circuit operation in FIG. 1 is explained by waveform diagrams (a) to (a) in FIG.
This will be explained with reference to (g).

During reproduction, the output of the magnetic head 50 passes through a reproduction amplifier 51 and is subjected to FMS modulation and de-emphasis by a demodulation circuit 52. First, demodulated sector 0 playback signal (a
) is input to the time axis conversion circuit 31, and the A/D converter 32
The signal is converted into a digital signal and output to the memory 33.

Further, this reproduction signal (a) is transmitted to the start flag detection circuit 5.
3. It is also input to the end flag detection circuit 54 at the same time.

The start flag detection circuit 53 detects the trailing edge of the start flag of sector 0 and outputs the start flag detection signal (
b) is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (for example, T?+) from the input of the start flag detection signal (b).
Ts) Count-up signal that rises with a delay (d)
Output. By outputting the count up signal (d),
The write address counter 56 starts counting up, and the memory 33 starts a write operation.

Then, the end flag detection circuit 54 detects the sector Q.
When the trailing edge of the end flag is detected and the end flag detection signal (C) is input to the write address counter control circuit 56, the count up signal (d) falls and the write address counter 56 stops. with memory 3
The write operation in step 3 also stops.

Since the count-up signal (d) is output to the last edge of the end flag, at the time of detecting the end flag,
After the compressed audio signal, the O pedestal section and end flag are written into the memory 33.

However, when the write address counter control circuit 55 receives the end flag detection signal (C), it outputs a countdown signal (e) with a pulse width T6. This countdown signal (e) causes the write address counter 56 to
Countdown for 6 seconds.

Due to this countdown, the write address returns to write address B at the end of the compressed audio signal.

Further, the final address holding circuit 10 holds the write address after countdown based on the detection of the end flag, that is, the end address B of the compressed audio signal. This address B is held until the next end flag of sector 1 is detected and counted down.

Furthermore, by writing the start end of the compressed audio signal in sector 1 from address B after countdown, the unnecessary pedestal portion and end flag written in the memory 33 are eventually removed.

Similarly, the compressed audio signals from sector 0 to sector 3 are written continuously into the memory 33 without duplication.
After completing writing from sector 0 to sector 3, the final address holding circuit 10 outputs the end address E of the compressed audio signal in sector 3.

Reading out the compressed audio signal written in the memory 33 is as follows:
From the first written address (address A in FIG. 2(g)) to the address finally output from the final address holding circuit 10 (address E in FIG. 2(g)),
This is performed by reading at the read clock frequency fr, and output to the D/A converter 34.

The audio signal converted into analog by the D/A converter 34 is reproduced by a reproduction processing circuit 59 and outputted from an output terminal 60.

Next, scratches on the video floppy 40, playback errors on the head,
The fact that reproduction is possible even when a flag detection error occurs due to noise or the like will be explained with reference to the waveform diagram in FIG. 3. FIG. 3 exemplifies a detection error of the end flag of sector 2. Assuming that the writing of this track into the memory 33 is performed normally up to sector 1, the final address holding circuit 10 outputs the end address C of the compressed audio signal of sector 1 upon detection of the end flag of sector 1. There is.

Next, the compressed audio signal for sector 2 is written.

First, the start flag detection circuit 53 detects the start flag of sector 2, and generates a start flag detection signal (b).
is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (e.g. 4; J' T
T 10T 3) Outputs a count-up signal (d) that rises with a delay, and thereby the compressed audio signal of sector 2 begins to be written to the memory 33 from address C. However, since the end flag of sector 2 cannot be detected, the count-up signal (d) has a specified length (for example, Ta
+T*+T a ), the count-up signal (d) falls, and writing to the memory 33 stops. At this time, since the end flag was not detected, the end write address of the compressed audio signal in sector 2 cannot be known.

However, even at this point, the final address holding circuit 10 is outputting the write address C at the end of the compressed audio signal in sector 1, and for reading, the final address holding circuit 10 outputs from address A, which is the first address of writing. By reading up to address C, it is possible to read and reproduce the normally written compressed audio signals in sector 0 and sector 1.

As mentioned above, even if flag detection errors occur due to scratches on the video floppy, playback errors in the head, noise, etc.
It is possible to reliably read up to sectors that have been accurately written to the memory 33.

Incidentally, in the above embodiment, an example was given in which the end flag was detected incorrectly, but even in the case where the start flag was incorrectly detected, it is possible to read accurately up to a sector that has been written to the memory 33 in the same way.

Next, a second embodiment of the present invention will be described.

The second embodiment not only solves the conventional problems, but also continues writing to memory even if a flag is detected incorrectly, and reproduces all compressed signals except for the sector in which the flag was incorrectly detected. The purpose of the present invention is to provide a signal reproducing device that can perform the following functions.

FIG. 4 is a block diagram of a video floppy audio reproducing apparatus according to the second embodiment. Note that in FIG. 4, circuits that operate in the same manner as in FIG. 1 are designated by the same reference numerals.

31 is the time axis conversion circuit mentioned earlier, which includes an A/D converter 32 that converts an analog signal into a digital signal, a memory 33 that stores the digital signal, and a D/A converter that converts the digital signal into an analog signal. 34, and operates as a time axis expansion circuit during playback. 33a
is a data input terminal, 33b is a write address terminal, 33c
is a read/write terminal, 33d is a read address terminal, 3
3e hatator output terminal. The memory 33 is
When a high level signal is input to the write terminal 33c, the data input to the data input terminal 33a is written to the address of the write address terminal 33b. Furthermore, when a low level signal is input to the read/write terminal 33c, the data written to the address of the successive address terminal 33b is output to the data output terminal 33e.

53 is a start flag detection circuit, and 54 is a start flag detection circuit. In this format, since the edge of the flag is the time reference for the start and end of the compressed audio signal, the trailing edge of the flag is detected, and the start flag detection signal (Fig. 5 (b)), End flag detection signal (
Figure 5(C)) is output.

55 is a write address counter control circuit, which receives the start flag detection signal (b) and end flag detection signal (e) as input, and performs a predetermined period of time (for example, T t + T s ) from the input of the start flag detection signal (b). It outputs a count-up signal (FIG. 5(d)) that rises with a delay and falls with the input of the end flag detection signal (C).

Therefore, if the start flag detection signal (b) and end flag detection signal (e) are accurately input, the count-up signal (d) is output for a period of T4+Ta. but,
If an end flag detection error occurs, T4,000 T6
It will be output for the above period. Therefore, the maximum output period of the count-up signal (d) (for example, the maximum T 4 +
T 2 + T s ).

While this count-up signal (d) is input to the 1 read/write terminal 33c, the memory 33 performs a write operation.

Further, the write address counter control circuit 55 outputs a countdown signal (FIG. 5(e)) having a pulse width T6 along with the input of the end flag detection signal (C).

The write address counter 56 inputs the count up signal (d) and count down signal (e) which are the outputs of the write address counter control circuit 55, and the output of the final address holding circuit 10, and outputs them to the write address terminal 33b. By doing so, a write address is specified in the memory 33. 56a is a count-up terminal, 56b is a count-down terminal, and 56c is a data input terminal. While the count-up signal (d) is input to the count-up terminal 56a, the write address is increased, and the count-down terminal 56b is input to the count-down terminal. While the signal (e) is being input, the write address is decreased. Further, when neither the count-up signal (d) nor the count-down signal (e) is input, the output of the final nutless holding circuit 10 input to 58c is set.

10 is a final address holding circuit which is a feature of the present invention. The final address holding circuit 10 receives the outputs of the write address counter side control circuit 55 and the write address counter 5B as input, and is the address of the write address counter 56 after the output of the countdown signal (e) is stopped, that is, the address of the write address counter 56 after the output of the countdown signal (e) is stopped. The end write address of the compressed signal is held and outputted to the write address counter 56 and subsequent address counter control circuit 57. The output is held until the end write address of the compressed signal of the next sector is detected. Further, the initial value of the final address holding circuit 10 is assumed to be the address first written in the memory 33 (in this embodiment, address A in FIG. 6(g)).

57 is a read address counter control circuit, and 58 is a successive address counter. Read address counter control circuit 5
7 controls the read address counter 58 which receives the output of the successive address counter 58 and the output of the final address holding circuit 10 and counts up until the output of the read address counter 58 reaches the address output by the final address holding circuit 10. do. The successive address counter 58 is
The successive address is specified in the memory 33 by outputting to the successive address terminal 33d.

60 is a reproduction signal processing circuit which receives the output of the D/A converter as an input.

Next, the circuit operation of FIG. 4 is explained by the waveform diagram (a) of FIG. 5.
This will be explained with reference to (g).

During reproduction, the output of the magnetic head 50 passes through a reproduction amplifier 51 and is subjected to FM demodulation and de-emphasis by a demodulation circuit 52. First, demodulated sector 0 playback signal (a
) is input to the time axis conversion circuit 31, and the A/D converter 32
The signal is converted into a digital signal and output to the memory 33.

Further, this reproduction signal (a) is transmitted to the start flag detection circuit 5.
3. It is also input to the end flag detection circuit 54 at the same time.

The start flag detection circuit 53 detects the trailing edge of the start flag of sector 0 and outputs the start flag detection signal (
b) is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (for example, T t +
Ts) Count-up signal that rises with a delay (d)
Output. By outputting the count up signal (d),
The write address counter 56 starts counting up, and the memory 33 starts a write operation.

Then, the end flag detection path 54 detects sector 0.
When the trailing edge of the end flag is detected and the end flag detection signal (C) is input to the write address counter control circuit 56, the count up signal (d) falls, the write address counter 56 stops, and memory 3
The write operation in step 3 also stops.

Since the count-up signal (d) is output to the rear edge of the end flag, the pedestal portion after the compressed audio signal and the end flag are written in the memory 33 at the time of detecting the end flag.

However, when the write address counter control circuit 55 receives the end flag detection signal (C), it outputs a countdown signal (e) with a pulse width T6. By this countdown signal (e), the write address counter 56 is set to T6.
Count down for a while.

Due to this countdown, the write address returns to write address B at the end of the compressed audio signal.

The final address holding circuit 10 holds the write address after countdown by detecting this end flag, that is, the end address B of the compressed audio signal. This address B is held until the next end flag of sector 1 is detected and counted down.

Furthermore, after the TI countdown signal (e) falls, the final address holding circuit 10 input to 56C
The output address B of sector 1 is set, and the start end of the compressed audio signal of sector 1 is written from address B. This results in
As a result, the unnecessary pedestal portion and end flag written in the memory 33 are removed.

Similarly, the compressed audio signals from sector 0 to sector 3 are written continuously into the memory 33 without duplication.
After completing writing from sector 0 to sector 3, the final address holding circuit 10 outputs the end address E of the compressed audio signal in sector 3.

Reading out the compressed audio signal written in the memory 33 is as follows:
From the first address written (address A in FIG. 5(g)) to the address finally output from the final address holding circuit 10 (address E in FIG. 5(g)),
This is performed by reading at the read clock frequency fr, and output to the D/A converter 34.

The audio signal converted into analog by the D/A converter 34 is subjected to 11 raw processing by the reproduction processing circuit 59 and outputted from the output terminal 60.

Next, scratches on the video floppy 40, playback errors on the head,
The fact that reproduction is possible even when a flag detection error occurs due to noise or the like will be explained with reference to the waveform diagram of FIG. 6.

FIG. 6 exemplifies a detection error of the end flag of sector 2. Writing this track to the memory 33 is as follows:
Assuming that the process up to sector 1 is normal, the detection of the end flag of sector 1 causes the final address holding circuit to
0 outputs the end address C of the compressed audio signal of sector 1.

Next, the compressed audio signal for sector 2 is written.

First, the start flag detection circuit 53 detects the start flag of sector 2, and the start flag detection signal (
b) is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (for example, T y +
T s ) Count-up signal (d
), and as a result, the compressed audio signal of sector 2 begins to be written to the memory 33 from address C. However, since the end flag of sector 2 cannot be detected, the count-up signal (d) has a specified length (for example, T a
* + T s ) and the count-up signal (d
) falls, and writing to the memory 33 stops. Since the end flag was not detected at this time, the end write address of the compressed audio signal in sector 2 cannot be known.

However, even at this point, the final address holding circuit 10 is outputting the write address C at the end of the compressed audio signal of sector 1, and when the count-up signal (d) falls, it becomes the output of the final address holding circuit 10. Address C is set. Therefore, it is possible to continue writing the compressed audio signal for the next sector 3.

The start flag detection circuit 53 detects the start flag of sector 3, and outputs the start flag detection signal (
b) is output to the write address counter control circuit 55.

The write address counter control circuit 55 operates for a predetermined period (for example, f T v
+Ts) outputs a count-up signal (d) that rises with a delay, and thereby the compressed audio signal of sector 3 begins to be written to the memory 33 from address C.

Then, the end flag detection circuit 54 detects the sector 3.
The end flag of is detected, and the end flag detection signal (C
) is input to the write address counter control circuit 56, the count up signal (d) falls, the write address counter 56 stops, and the write operation of the memory 33 also stops.

Further, when the end flag detection signal (C) is input, the write address counter control circuit 55 outputs a countdown signal (e) having a pulse width To. This countdown signal (e) causes the write address counter 56 to count down for a period of T6, and the write address returns to write address D at the end of the compressed audio signal.

When the end flag of sector 3 is detected, writing of this track is completed, and finally the final address holding circuit 10 outputs the write address D of the end of the compressed audio signal of sector 3.

As is clear from FIG. 6(g), the compressed audio signals of sectors O, 1, and 3 are written in addresses A to D of the memory 33, except for sector 2 where the flag detection error occurred. To read the compressed audio signal of this track, the compressed audio signal excluding sector 2 is reproduced by reading from address A, which is the first address of writing, to address D output by the final address holding circuit 10. .

As described above, even if a flag detection error occurs due to a scratch on the video floppy, a playback error in the head, noise, etc., it is possible to reproduce all compressed audio signals except for the sector in which the flag was incorrectly detected. be.

Incidentally, in the above-mentioned embodiment, a case where an end flag is detected incorrectly is taken as an example, but a similar reproduction is also possible in the case where a start flag is incorrectly detected.

Effects of the Invention As is clear from the first embodiment, the present invention allows compressed audio signals to be accurately written into memory even when flag detection errors occur due to scratches on the video floppy, playback errors in the head, noise, etc. It is possible to read out and play back up to the sectors that were previously recorded.

Furthermore, in the second embodiment, even if a flag detection error occurs, it is possible to continue writing the compressed audio signal of the next sector into the memory. This makes it possible to read out and reproduce all the compressed audio signals except for sectors in which flags have been detected incorrectly, which is highly effective.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a video floppy audio signal reproducing device according to a first embodiment of the present invention, FIGS. 2 and 3 are operational waveform diagrams of various parts of the same embodiment, and FIG. 2
5 and 6 are operational waveform diagrams of various parts of the same embodiment. FIG. 10 is a block diagram showing an example of the audio signal reproduction device for the video floppy in the embodiment. is a waveform diagram of the operation. 10...Final address holding circuit, 40...Video floppy 50...Magnetic head, 51...
・Reproduction amplifier, 52... Demodulation circuit, 31...
・Time axis conversion circuit, 32...A/D converter,
33...Memory, 34...D/A converter, 53
...Start flag detection circuit, 54...End flag detection circuit, 55...Write address counter control circuit, 56...Write address counter, 57
. . . successive address counter control circuit, 58 . . . successive address counter, 59 . . . reproduction processing circuit.

Claims (2)

[Claims] (1) demodulating means for obtaining a demodulated signal by demodulating an information signal recorded in a sector area, with a start flag added to the starting end side and an end flag added to the terminating side; memory means for temporarily storing only the information signal from the demodulated signal of the area; and write address control means for sequentially increasing or decreasing the write address of the memory means so as to write only the information signal in the memory means. , a final address for detecting and holding the end write address of the information signal written in the memory means by detecting the end flag, and updating the held address by detecting the next end write address of the information signal; holding means; and read address control means for sequentially increasing the read address of the memory means so as to read from the memory means from the first address where the plurality of information signals are written to the address held in the final address holding means. An information signal reproducing apparatus comprising: a reproduction processing means for inputting and reproducing the output of the memory means. (2) The information signal reproducing apparatus according to claim 1, wherein the write address control means increases the write address from the end of the last written information signal held by the last address holding means.