JPH02287271A - Delay trouble inspection apparatus - Google Patents

Abstract

PURPOSE:To test that each path is possible to operate at specification frequency by activating the logic of the path from a register to a register when the trouble simulation of a scanning system is performed. CONSTITUTION:A pattern forming part 91 calculates an input pattern I activat ing the path of a combination circuit part from the output of the register of an LSI 18 to the input of the next register and further strikes one clock to calculate an input pattern II setting the input pattern I to the register of the LSI. At the time of testing, a tester part 93 is used to scan in the input pattern II at first and two clocks are struck at the frequency of the operating specifica tion of the LSI and a result is scanned out to be compared with an expectation value 92. That is, the logic of the path from the output of the register of a synchronous circuit to the input of the next register is activated and it is con firmed that each path is operable at specification frequency.

Description

[Detailed Description of the Invention] [Summary] The present invention relates to a delay fault inspection method for testing whether a logic circuit can operate at a specified frequency. The purpose is to activate the logic of the path from the logic circuit to the register, and to test that each path can operate at the specified frequency, from the register output of the logic circuit to the next register input. Input pattern generation means for obtaining an input pattern I that activates a specific test path of the combinational circuit; An input pattern for obtaining a human cover turn II that is set in a register in the input section ■ After scanning in the generating means and the input pattern II, a clock is struck twice at the operating specification frequency of the logic circuit, and the first clock is generated. sets the input pattern in which the inspection path is established in accordance with the change from the input pattern (2) to the input pattern (2) in the register, forms the inspection path by the logic of the human cover turn I, and then A change in state is outputted from the output of the combinational circuit, the result is set in the register at the second clock, and the test means scans out the result and compares it with an expected value. The system is configured to test for delay faults that exist on the test path.

[Industrial application field]

The present invention relates to a fault simulation method, and more particularly to a delay fault inspection method for testing whether a logic circuit can operate at a specified frequency.

Logic circuits used in digital computers, etc. are realized as integrated circuits, and with the development of large-scale integration technology, many functions are integrated into LSI (large scale integration).
It has come to be realized as Before starting the LSI manufacturing process, it is important to test whether the logic circuit of the LSI is operating normally.In particular, it is important to test whether the logic circuit of the LSI is operating normally. It is important to test whether the functionality is correct. Logic simulation is a simulation method in which a logic signal is input to the input of a logic circuit, and it is checked whether the output of the logic circuit obtained is an expected pattern. In addition, fault simulation is a method in which a stuck-at fault is assumed for the output of each gate, a logic simulation is performed under that assumption, and the stuck-at fault is found when the pattern at that time is output in the actual circuit. be. Note that a stuck-at fault refers to a situation in which the collector of a transistor becomes an oven and the collector output does not change even if the collector current attempts to flow.

These test simulation methods are extremely important technologies. As LSI speeds have increased in recent years, in addition to detecting static faults such as stuck-at faults, there is a demand for delay fault inspection to confirm that the LSI can operate at the specified frequency. In this case, in particular, the logic of the path from the output of a register in the synchronous circuit to the input of another register is activated from O to 1 or from 1 to O, and the signal propagation on that path is verified to be able to operate at the specified frequency. A method is required to obtain a test sequence that can be confirmed.

[Conventional technology]

FIG. 11 is a conceptual diagram of a fault simulation method based on the conventional scan path method. In the figure, 1 is a register section inside the target logic circuit, and 2 is a combinational circuit section that receives a signal output from register 1 and a signal input from an external input, and outputs logic within a clock cycle. A part of the output is set in the register section 1. 3 is a scan-in which is a shift input when register section 1 is made into a shift register;
4 is a shift-out scan out.

It is assumed that a clock 5 is input to the register unit 1, and the logic of the path 6 of the combinational circuit 2 is executed during the clock cycle period from the rising edge of the clock to the next rising edge. Some of the outputs of the combinational circuit section are output to external output bins. In fault simulation based on this scanning method, all register sections included in a logic circuit are connected as a shift register in such a way that a shift signal is propagated. Then, during testing, the scanned-in data is set in the register section, this information is given to the input of the combinational circuit section 2, and its output is set in the register section 1 at the next rising edge of the clock. Content is scanned out and compared to expected patterns. The advantage of the scan method is that any input pattern can be set to the register section inside the integrated circuit chip, and therefore any input pattern can be input to the combinational circuit connected to this register. It is possible. Another advantage is that the output of any combinational circuit section is also set in the register section, and testing can be easily performed by scanning it out.

For example, if the four stages of Nant gates shown in the combinational circuit section 2 of FIG. 11 are on one path, and it is possible to set one terminal of all the Nant gates to 1, then
When a specific bit output from register part I is activated from O to 1, this activated logic change is propagated through the path on the Nantes gate, and the logic corresponding to the change is changed to the next clock. It is set in register section 1 at the rising edge.

[Problems to be Solved by the Invention] In the conventional method, the conditions for forming a path such that a change in input propagates to a change in output, that is, for example,
An input pattern is formed that creates a condition in which one terminal of each NAND in the NAND circuit shown in Fig. 11 is set to 1, and the input points on the path are activated from 0 to 1 or from 1 to 0. It was not possible to propagate logical changes on that path. That is, conventionally, when a designer verified a logic design using a simulator, the input series used was tested at the operating frequency to check whether it was as expected. In particular, since the register section is a shift register, it is not possible to change the pattern that satisfies the input conditions such as propagation of activated logic on the path by scan-in operation alone.

Therefore, in the conventional method, the input series is only used to check the correctness of the logic; it activates the logic of the path from the register output to the register input, and checks whether each path can operate at the specified frequency. There was a problem that delayed failure inspection was not possible.

That is, there is a problem in that the ratio of tested paths is low and it is not possible to form a high-performance tester that tests LSIs that operate at high speed at that frequency.

The present invention makes it possible to activate the logic of paths from register to register and test whether each path can operate at the specified frequency even when performing scan-based fault simulation. do.

[Means to solve the problem]

FIG. 1 is a system configuration diagram of the present invention.

In FIG. 1, 7 is an external storage section for storing circuit data and path data, 8 is a target LSI, and 9 is a system of the present invention, which is internally comprised of a pattern generation section 91 and a test section 93. The pattern generation section 91 obtains an input pattern I that activates the path of the combinational circuit section from the register output of the LSI 8 to the input of the next register, and then generates the input pattern of the LSI by striking one clock. Find the input pattern II that will be set in the register. Then, during the test, the test section 9
3, first scan in pattern II, then
The clock is struck twice at the frequency of the LSI's operating specifications, the result is scanned out, and compared with the expected value (92).In other words, in the present invention, the logic of the path from the register output to the register input of the synchronous circuit is activated. This test method confirms that each path can operate at the specified frequency.

[Operation] The present invention obtains an input pattern 1 that activates the path of the combinational circuit section from the register output of the LSI 8 to the input of the next register, and furthermore, the input pattern clocks the register. Find an input pattern II that will cause the person's cover turn ■ to be sent to the register by one hit.

During testing, after scanning in the pattern II, one clock is applied to input the input pattern ■ that activates the path to the input of the combinational circuit, and then the next clock is used to scan in the combinational circuit for the input pattern I. The output pattern is set in a register and scanned out to compare it with the expected value.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2(a) is a processing outline diagram of the system of the present invention.

That is, the present invention provides 31
In steps 32 and 32, pattern I and pattern II are generated, pattern II is scanned in in step S3, and the expected value output by pattern I is tested.

FIG. 2(b) is a block diagram of the pattern generation section. In the figure, 12 is an input search section, 13 is a simulation section for a target combinational circuit, and 14 is an output inspection section. The pattern generation unit 91 searches for test sequences for generating patterns T and II. As a result of the search, pattern I may not be found, and even if pattern I is found, pattern II may not be found.

Therefore, the input search unit 12 executes an algorithm for searching for patterns in order to generate pattern (2) and pattern (II). Then, when the results obtained by executing the algorithm are inspected and the desired pattern is found, it is judged as "success", and if it is not found, it is determined that there is no solution or it is aborted and " Impossible.” Alternatively, if you are unable to proceed any further while exploring, but there is something you have left unfinished, packtrack the exploration as a "failure". If it is not “success” or “impossible” or “failure”, then “
treated as "unknown". Success and failure like this.

By obtaining unknown, impossible, or reset information from the output inspection unit 14, this information is taught to the input search unit 12,
Control behavior. This is the operation of the pattern generation section of the present invention.

The test section 93 in FIG. 1 receives the input pattern I, the input pattern ■, and the expected value generated by the pattern generation section 91. FIG. 2(C) is a functional block diagram of the processing of the test section. In S4, the test section 93 scans in the second input pattern II, which forms the input pattern I for activating the path by inputting a clock. Scan data needs to be input using a scan clock. When the test section 93 scans this input pattern II into the LSI, the input pattern II is set in the register section inside the LSI. Then, in S5, the clock is turned on twice at the specified frequency. If the frequency of this system clock is f, then the period is 1/'', which is the time width from the rising edge of the clock to the rising edge of the next clock.The input pattern scanned in by the rising edge of the first clock ■ changes to input pattern ■. This input pattern I determines other inputs in advance so that the change in logic propagates on the path of the currently focused logic path of the LSI. This input pattern I When applied to the circuit, the register section of the LSI
The input pattern (2) changes to the input pattern I at the second clock, and the result of the input pattern I is outputted via the combinational circuit at the second clock, and is stored in the register section.

Then, in S6, it is scanned out to confirm that the data is equal to the expected value. That is, it can be checked whether the logic change due to the change from input pattern (2) to input pattern (I) operates normally within the specified frequency f by scanning out the result of the register section and comparing it with the expected value. That is, it is possible to check whether the total propagation delay time on the logical path that is about to be established is within the period 1/I. If it fits, the correct expected value pattern will be scanned out on the second clock, but if the delay of the logic path is not within the reciprocal of the specified frequency, that is, the period of the system clock, even if the logic is correct. However, a delay failure occurs and the scanned out data is incorrect.

Therefore, when the scanned-out data is compared with the expected value, it does not match, and a delay failure is confirmed.

FIG. 2(d) is a conceptual diagram of the operation of the pattern generation section that obtains the input pattern (2). For the human cover turn given by the input search unit 12, the signal value at the start point 18 of the path is set from 0 to 1,
Or if you change it from 1 to 0, the change is path 1
It is necessary to check whether the change in the signal propagates on the signal 9 towards its end point 20. In order to obtain the input pattern (2), its operation is simulated in the combinational circuit simulation section. The output inspection unit 14 checks whether a signal change has been transmitted to the end point 20 of the path. If the algorithm is transmitted, it is marked as "success"; if there is no solution or there is a give-up, it is marked as "impossible", and if the algorithm cannot proceed and has no choice but to return to the original state, it is marked as "failure J". The search is backtracked.The state in which neither of these is known is unknown.Success J,
The output inspection unit 14 determines whether it is "impossible,""failed," or "unknown." After making these determinations, the input search unit 1
The output inspection unit 14 instructs the next operation after step 2.

If this is not possible, this path will not be activated.

In other words, it is determined that it cannot be tested. Furthermore, at the start of the search, the pattern generation section is initialized with a reset signal. Therefore, as shown in FIG. 2(d), the input pattern I
When calculating, the inputs given from the input search section 12 are all inputs, and the output given to the output inspection section 14 is one output.

FIG. 2(e) is a conceptual diagram of a pattern generation section for determining input pattern II. Input pattern (2) is an input in which the value stored in the register section becomes input pattern I as a result of clocking.

The final output of the combinational circuit is simulated based on the pattern given by the input search unit 12. If the output inspection unit 14 determines that the output of the combinational circuit 13 is the input pattern I, it gives "success", and if there is no solution or gives up, it gives "impossible" and moves on to the algorithm. I can't, but
Backtracking is when you return to the original location and then search for a different path. In this case, the search is a "failure" so you backtrack. If one of these is unknown, it is "unknown." In this way, "success", "impossible", "failure", and "unknown" are determined and the next operation of the input search unit 12 is instructed. If the search turns out to be "impossible", it is requested to generate another pattern (2). Note that the reset signal sets search conditions. Therefore, as shown in FIG. 2(e), when finding the input pattern II, the input given from the input search unit 12 to the combinational circuit 13 is given as a pattern for all inputs,
The output of the combinational circuit 13 given to the output inspection section 14 is also the full output.

FIG. 3(a) shows pattern I and pattern I according to the present invention.
FIG. 3 is a circuit diagram of an embodiment used to determine I. FIG. In the figure, DFFI, DFF2. Each DFF3 is a D-type flip-flop, and when a clock is input to the clk terminal, data at the input terminal is set by the rising edge of the clock and is output from the Q output. Each flip-flop also has a shift-in input st and a shift-out output SO to form a shift register, and a DFF
Scan-in (SCAN-IN) data is input to si of l, SO is input to sl of DFF2, and
sO is input to si of DFF3, and SO of DFF3 is output as scan out.

Ql is an input of B3, Q2 is an input of gl, and Q3 is an input of B2. Q2 is also connected to B2. The output of gl is connected to the other input of B3, and the output of B2 and B3
The output of becomes the input of B4, and the output of B4 becomes the DFF
It is connected to the input DI of I. The output of B4 is data out.

In addition, the input D2 of DFF2 is externally input *ENA
BLE, and the input D3 of the DFF3 is the DATA-IN signal. That is, in FIG. 3(a), DFFI, D
FF2. DFF3 corresponds to the register section, gl, B2 .
B3. B4 corresponds to the combinational circuit section. And D
ATA-IN signal and *ENABLE signal are external inputs, D
ATA-OUT becomes external output. In the combinational circuit, the path to be activated is Q2. gl, B3. B4. Di
Consider the path of Now, the change from 1 to O is F (Fal
1), the rise from 0 to 1 is expressed as R(Ri
se). The above-mentioned path will be referred to as the "inspection path" hereinafter. Ql must be 1 to activate the inspection path.
Therefore, the output of B2 must also be set to l. Under such conditions, when Q2 is F or R, that F or R is propagated to the output of gl, the output of B3, and the output of B4 in the test path. For example, when Q2 is F, the output of gl is R, the output of B3 is F, and the output of B4 is R.

FIG. 3(c) is an example diagram of the search order showing the procedure for generating pattern I and pattern II. In the figure, X is a don't care and is in an undetermined state of 1 or 0. F
represents a symbol that represents a change from 1 to O, and R represents a symbol that represents a change from O to 1. Bl and BO are symbols that mean failure when the signal value becomes 1, and failure when the signal value becomes 0, respectively. Y is a symbol of unknown meaning.

First, we will explain the tree search method for finding pattern I, that is, the input pattern that is the condition for activating the path. Items 1 to 8 are pattern generation when Q2 changes from 1 to 0, that is, F. In the procedure, items 9 to 16 are
This is the procedure when Q2 changes from 0 to 1, that is, R. In item number l, the circuit is in a state where it has been initialized by a reset command. At the time of reset, the signal line corresponding to Q2 of the input search section is fixed to F as the starting point of the path.

Further, the output inspection unit monitors whether the signal value of R or F is propagated to Dl as the end point of the path.

When Q2 is F, the output of gl is R, and the other signals are now X. This is the starting state. Item No. 2.3.4 is a tree search procedure for generating pattern I. In addition to Q2, inputs include Ql, Q3.
DI (DATA-IN)*E (*ENABLE) has the degree of freedom to take 0 or 1, and therefore, pattern I is generated from 2 to the 4th power=16 combinations.

Therefore, first, all inputs are initialized to the state of X, which is undefined as O or 1. In item number 2, the leftmost Ql among these is bound to 0 with 0 priority. Then, when Q2 is F, gl is defined as its inverse R, and B2 becomes 1 according to the truth value described later.If the output of 0g2 is 1, F of Q2 becomes R at gl and passes through B3. However, since Ql is 0, it does not propagate to the output of B3, and B3 becomes 1 due to the O of Ql. Therefore, since B3 fails with a 1, the outputs of B1 and B4 fail with an O, so they become BO. Therefore, the control will fail. So this time, change Ql to 1. This is item number 3. At this time, the output of B2 is X, and since Ql of B3 is 1, the output state of gl is propagated and becomes F. Since B3 is F and B2 is X, the output of Dl is unknown and becomes Y. The control is therefore "unknown". If it is unknown, set the other inputs to X and proceed with the algorithm.

That is, Q3 is set to 0. This is item number 4.

Ql and Q2 are the same as item number 3, and are 1 and F.

At this time, g1 is R, B2 is 1 because Q3 is 0,
F of B3 will be propagated through B4, and the output of B4 will be R. Therefore, activation has been transmitted, resulting in "success".

Ql, Q2. When Q3 changes from 110 to 100, that is, when Q2 changes from 1 to O under the constraint that Ql is l5Q3 is O, the change passes through the inspection path to D
The input pattern ■ is to appear in ``l'', and this was generated. Therefore, item numbers 5 and 6 are means for generating pattern II. In item number 5, constraint conditions are set by resetting. Before hitting the clock is Ql, Q2. Q
3 is 110, and the pattern ■ must be 100 after being hit, that is, Q2 must be F, so the input search unit calculates Q1=1. Q2=1 and Q3=0 are constrained, and only Dl and E among the inputs have a degree of freedom of change. Furthermore, since the output inspection section must receive the clock to obtain pattern I, it is set to detect the output conditions of D1 being 1, B2 being O, and D3=O. If item number 5 is input to the input of the combinational circuit under such constraint conditions, Ql will be 1
Therefore, the lower side of B3 becomes 1. Since Q2 is 1, gl
The output of is O, B3 is 1, and the output of B2 is Q3
Since is O, it is 1. Therefore, since B2 and B3 are both 1, the output of B4 is 0 and becomes item number 6, but item number 5
This is contrary to D1=1.

Therefore, it is a failure. There is nothing to backtrack, so failure is equivalent to impossible.

Therefore, using item numbers 7 and 8, another pattern (■) is searched. In item number 7, Q3 is set to 1 as a continuation of item number 4. Ql,Q
2. Q3 is 1. F, 1, then gl is R,
Since Q3 is 1, B2 propagates F of Q2 and becomes R,
Since Ql is 1, B3 propagates R of gl and becomes F.

The output of B4 is D due to the F of B3 and the R of B2 and the F of B3.
l fails with 1. Therefore, the control becomes a "failure". In item No. 8, other possibilities are considered, but since it can be seen that all cases have been exhausted, it becomes clear that generation of pattern (2) is impossible. That is, in 8, Ql and Q3 return to X, and the state becomes the same as in item number 1.

This means it is not possible. In other words, the tree search for items 1 to 8 is a pattern l such that Q2 is F.
This means that although it is possible to obtain pattern II, it is not possible to obtain pattern II.

Therefore, pattern I for the case where Q2 is R in item numbers 9 to 12 is generated using the same procedure. For item number 9, Q2 is R
In this case, gl is reset to F, and the others are reset to X. In item No. 10, if QlmeX is changed to O, B3 will be forced to 1, resulting in a failure due to 1. Therefore, the output of B4 also becomes 0 and fails, B3 becomes B1, Dl becomes BO, and the control becomes "failure". Therefore, in item number 11, Ql is changed from 0 to 1. Due to this l, the output of B3 becomes R. However, since Q3 is X in the output of B2,
X, so the output of B4 is Y and becomes "unknown." If it is unknown, the algorithm is further advanced and the other Xs are changed to 0. In this case, Q3 is changed from X to 0.

As a result, the output of B2 becomes 1 and B4 propagates the other input, propagating the output R of B3,
Set the output to F. In other words, Dl becomes F, resulting in "success". Item numbers 13 to 16 generate pattern II. In item number 13, since Q2 is R in item number 12, 0, which is the state before rising, is assigned to Q2, and when the clock is input to this, it becomes 1, so B2 is set to 1. Therefore, the constraints are Ql, Q2. Q3 is 100, DI, B2. B
3 becomes 110. This is the reset state.

As we proceed with the algorithm under these conditions, gl
The output of B2 is 1 because it is the inversion of Q2, the output of B2 is 1 because it is the inversion of Q3, the output of B3 is 0 because Ql is 1 and gl is 1, and B1 is the inversion of the output of B3, so it is l. becomes. However, the fact that B2 and B3 should be 10 is X,
It is X. This is not required by pattern ■ and results in a failure. Therefore, proceeding with the algorithm further, change the leftmost X, that is, Dl in item number 15, to O. At this time, since D3 is O, it becomes unknown. Next, when *E is changed from X to 0, the 02 input becomes O. There is no state X, but this is an unknown state. If D2 is set to 1, that is, *E is set to 1, Di
, D2. D3 becomes 110 and it is successful. That is, when a clock is applied, Q2 is changed from 1 to 0, and the R can be propagated through the test path.

FIG. 3(C) is a processing flow of a test section that performs a test using patterns ① and II obtained by the pattern generation section.

When pattern I and pattern II regarding the circuit of the circuit of FIG. 3(a) are determined based on the embodiment of FIG. Do it with That is, the input value shown in item number 17 in FIG. 3(b), that is, QI=1. Q
2=0. Q3=O, DI=O.

*E=1. Of this pattern, what is scanned in is the register value, so it is Ql, Q2°Q3. D[ and *E are set to 0°l in external input. Then move on to Sll. Here clock pulse 2
The current external input to the register with the specified frequency f is D1.
=0. *E=1, and the contents of the register are Q1=1
．． Q2-0°Q3=0. In this state, when one full clock pulse is input, the register input becomes as shown in Figure 3(b).
As shown in item number 17, D1=2. D2=1. D3
Since =O, the contents of the register change to ■, 1°0. External input does not change. QL=1°Q2=1. Q
3=0 and the external input DI=O, *E-1, the output g4 of the combinational circuit is 0, so the input of the flip-flop DFFI becomes 0. Also, due to external input, the input of DFF2 is LD, and the input of DFF3 is O. Therefore, when the second clock pulse is applied, the QI
Q2. Q3 is 0, 1, respectively. Changes to O. This is S
It is in the state of ll. The process moves to S12 to scan out and compare it with the expected value. That is, Q1=0. Q2=1. Q
Check whether 3=0 was set correctly. If the specified frequency f is set in the register, this expected value will be scanned out and the test result will be correct.

The above test operation will be explained using the circuit diagram shown in FIG. 3(d). In the scan-in state of input pattern II, Q1=1. Q2=0. Q3=O.

When one clock pulse is input at the specified frequency f, Ql=
1. Q2=1. Q3=O. At this time, the output of g4 changes from l to 0 as shown in the figure. Jutte, D1=
In the state O, D2=O, D3=0 (7), the second clock pulse is input at the specified frequency f. Then Ql is g4
The output of 0 is set. D3 is data in 0
is set. Therefore, Q1=O, Q2=1. Q3=0
becomes. Scan this out.

Furthermore, the above operation will be explained using a time chart using FIG. 3(e). The numbers in the figure correspond to the temporal devices, and each number corresponds to the legend of the number below. (1) is the state when scanned in.

QI=1. Q2=0. Q3=O, DI=0. *E=
It is 1. At this time, since the output Q2 of gl is 0, it is 1. The output of g2 is 1 since Q3 is 0. The output of g3 is 0. Therefore, g4 is ■. This corresponds to DI. D2 is 1 and D3 is
It is 0. In this state, the first clock is input at time (2). The register inputs at this time are Di, D2.
Since D3, correspondingly, as shown in (3), Ql-Dl, Q2=D2. Q3=03. Q2
changes from O to 1. The change in Q2 is propagated to the combinational circuit in (4), (5), and (6). (4
), due to the change in Q2, gl changes from 1 to 0, and (
In 5), g3 changes from 0 to 1 due to gl change. Then, in (6), Dl changes from 1 to 0 due to the change of 83. Then, in (7), the second clock is input. Then, in (8), DFF 1 takes in D1=O, and Ql changes from 1 to O. The state when scanning out in (9) is Q1=O, Q2=1. Q3=0.

FIG. 4 is a truth table for arithmetic logic when determining the input pattern (2). As shown in the figure, the 4-input gate is
Since it can be expanded to a 2-input gate and given as a 2-input truth table, it can be applied repeatedly to create a 4-input truth table. Also,
NAND/NOR inverts ANDloR.

For example, among the two-input ant gates, the two-input ant gate on the path is operated using the truth table (1) of Path-Primitive. In the table, the horizontal direction corresponds to input terminals on the path, and the vertical direction corresponds to input terminals not on the path. The signal symbol O is a logical low level, 1 is a high level,
R is a change from O to 1, F is a change from 1 to 0, X is O or 1
is indeterminate, BO means 0 and the search has failed, and B1 means 1 and the search has failed. It is unclear whether Y is 0, 1, R, or F. The shaded area indicates a search failure and the logical value is X, but in order to limit the number of signal values to 8 and express it with 3 bits, it is forced to be B1.
This way, there will be no contradiction in calculations. E represents an impossible case. By using this truth table, it is possible to simulate whether R or F propagates from the input to the output of the gate. For example, if the input side that is not an input terminal on the path is O, even if the input terminals on the path are R or F, it will fail with 0. 1 input terminal not on the path
In this case, the input terminals R and F on the path propagate as R and F in the case of an AND gate. The input terminal on the path is X,
If it is BO, Bl, Y, the output is also the same. If the input terminal not on the path is R, if the input terminal on the path is R, it will be R, but for example, if the input terminal on the path is F, the input terminal of the AND gate will be 0. Fail. A truth table for such a two-input AND gate is given in the form of a Path-primitive, that is, a symbolic representation of whether an activation state propagates through the AND gate.

For two-input ant gates that are not on the path, Non-
A path-primitive truth table (2) is given.

That is, with AND, if either input terminal is 0, the output is 0. If one input terminal is 1, if R and F are input to the other input, the output will be R and F. If one input is 1, the output will be X if the other input is X.

Figure 4 (3) is the Path-primity of 2-input OR.
ve truth table. In the case of a two-input OR, if the input terminal other than the input terminal on the path is O, R and F of the input terminals on the path are propagated to the output. If the input terminal other than the input terminal on the path is 1, it will not be activated and will fail at 1 even if the input terminal on the path is RIF. If the input terminal that is not on the path is R, it is R when the input terminal on the path is R, but if the input terminal is not on the path, it is R, but if
or B1, it fails with 1. The explanation will be similarly omitted below.

Figure 4 (4) is a 2-input OR Non-path-pri
mitve, that is, the truth table of the OR gate that is not on the path. In this case, when either one is O, the other R and F propagate. When either input is 1, the output is often 1. The explanation will be omitted below. Note that if the AND gate has four inputs, it is possible to replace it with a tree structure of two input ANDs, as shown in the figure. Of course, the truth table for the 4-input AND may be constructed directly. FIG. 4 (5) is a truth table for an inversion circuit, that is, an inverter. An inverter is a gate that outputs 0 when a 1 arrives, but the truth table for finding a Path-Primitive, that is, a pattern I, is F when R is input, R, X when F is input. When it is , it is X, when it is BO, it is B1, when it is B1, it is Y when it is BOSY, and when it is 0.1, it is an error. Non-path-Primi
tive, that is, O when generating pattern II.
When 1.1 is O, when R is F, when F is R, when X is X, when BO is 1, when B1 is 0, and when Y is X.

FIG. 5(a) is a principle diagram of the mechanism of the present invention, and FIG. 5(b) is a block diagram of its processing flow. Figure (a), (
In b), the input search units I and It inject patterns that are candidates for pattern E and pattern II, the combinational circuit unit 13 simulates the operation of the circuit for the candidate patterns, and the output inspection unit 14 injects candidate patterns for pattern E and pattern II. This is to confirm that the pattern satisfies the conditions of patterns I and II. The output inspection unit 14 notifies the input search unit 12 of success, failure, unknown, impossible, etc. in the signal mode as to whether pattern I or pattern II is being generated, and the combinational circuit 1
Controls the generation mode of 3. When generating the pattern I, the combinational circuit unit 13 converts the operation logic of the gates on the path and the operation logic of the gates not on the path into the third test path.
By distinguishing according to the truth table shown in the figure, it is possible to simulate how a signal change is transmitted from the start point to the end point of the path. When pattern II is generated, all gate operation logics are those of gates that are not on the path, and the circuit operation for pattern II is simulated. The input search section 12 injects the pattern generated by the input search section 1 into the combinational circuit section 3 when generating the pattern I. Therefore, the signal from the input search unit I is selected for the input terminal via the selection circuit 21. Further, the input searcher II operates to generate the pattern II, and injects pattern candidates into the combinational circuit unit 13. As shown by item number 5 in FIG. 3(a), when pattern 1 is generated in item number 4, item number 5 is determined based on it and becomes a constraint condition. Therefore, the fixed condition ■ receives information from the input searcher ■, and the pattern! It is determined by the conditions generated from. There are also constraints on the pattern generated from the input searcher (2); for example, the input value that is the starting point of the path is fixed to F or R. This is a fixed condition and is given to the input searcher I. Pattern I is Pattern II
It determines all of the constraint conditions, which is the fixed condition II.
and inspection conditions ■.

In the previous example, item number 5 is the constraint condition, that is, the fixed condition (■), but when this is determined, the gate output is determined in the combinational circuit section 13, and as shown in item number 6, gl,
g2. The output of g3 becomes 011. Therefore, the inspection condition I
Item number 6 is given as I, which is determined by the input searcher I. Each input searcher searches to generate a solution in the input vector space, and determines whether the search is successful or not.
The output searcher will notify you if it has failed, is unknown, or is impossible. Backtrack when you fail in your search. When the search returns to the state at the start of the search by backtracking, it is found that it is impossible, and this is notified to the output inspection section. If it is unclear, proceed with the search. Pattern II
When an impossibility is notified during generation, the mode enters a mode for searching for other patterns ■. For example, in FIG. 3(b), it is found that it is impossible to generate pattern II in item number 6, so in item number 7, pattern ■ is changed to another one. If it becomes impossible when searching for pattern I, it is proven that no test pattern exists to test that inspection path. For example, item number 8
Now for the pattern! It turns out that it is impossible to generate.

In other words, Q2 is the pattern for F's change from 1 to O ■
It turns out that it is impossible to generate. Output inspection section 1
4, in the generation mode of pattern I, test condition (2) is tested by tester (2). This watches over the propagation of F through R to the output signal line at the end of the path.

For example, in item number 4 of FIG. 3 (b), Ql, Q2. Q3 is l.

Under the test conditions of F and O, the tester 2 shows that R is generated at DI and activation logic is propagated at the end of the path. In the pattern II generation mode, the inspection condition II is inspected by the inspection device (■).

Test condition (2) monitors whether a pattern of the input searcher I whose value is determined appears on the corresponding output line. However, for F it is 0. For H, monitor 1. For example, in FIG. 3(b), in item numbers 1 and 2, pattern I
is obtained, and R of Q2 is successfully propagated as F to the D2 terminal. Item numbers 13 to 17 are changed in order to obtain an input pattern II that will generate this pattern I when the clock is turned on. Since Q2 is R, it must be set to 0 as its previous value, and it must be set to 1 after the clock is input, so item No. 13 is given as a constraint: D2 must be set to 1. And the checker ■ is the input searcher I
Monitor that a pattern with a fixed value appears on the corresponding output line.

In this way, pattern II is generated by proceeding through item numbers 14, 15, 16, and 17. This pattern becomes pattern ■ when one clock is inserted.

And in Q2, it changes from 0 to 1.

Since the change satisfies the conditions of pattern I, it is propagated to the output. In this way, in the present invention, when the conditions are met in any generation mode, success, failure, unknown,
Sends an impossible or reset control signal to the input search section. However, impossibility is detected when the search returns to the original state after one round, and is recognized by transmitting what the input search section 12 detects to the output inspection section 14. A reset is issued when a pattern is generated, but only at the beginning when a pattern I is generated.

FIG. 6 is a circuit diagram of an input pattern generation circuit when the principle diagram of FIG. 5 is applied to the embodiment of FIG. 3(a). g
l, B2. B3. B4 is the combinational circuit shown in FIG. 3(a). Two sets of input search sections corresponding to the number of inputs of the combinational circuit, that is, the number of external inputs of several tens of registers, are formed, and input searchers (2) and input searchers (II) are respectively applied to the combinational circuit via the selection circuit 21. In this embodiment, the outputs of the registers are Ql, Q2 . Since the external inputs in Q3 are DI and *E, the outputs of input searchers ■ and ■ are 5 each.
It is one. The output of the input searcher I is connected to the input searcher ■. The outputs of the input searchers (1) and (2) are input to the combinational circuit via a selection circuit 21 selected depending on the mode.

The combinational circuit includes Ql, Q2. Q3 is input and DI
and *E bypass the combinational circuit.

B4, which is the output of the combinational circuit, and the bypassed DI
, *E are input to the tester ■ and tester ■ of the output test section, and the output signals selected for the respective modes are fed back to the input searchers ■ and ■. These signals are success, failure, unknown, impossible and reset notifications.

The operation of the input pattern generation circuit shown in FIG. 6 will be explained in order with reference to FIG. FIG. 7(a) shows the state of item number 1 in the generation of patterns ① and II in FIG. 3(b).

Since the pattern I is generated, the selection circuit 21 is connected to the input searcher I side, and the output searcher 14 also selects the output of the searcher ■. Fix Q2 to F as shown in item number 1. When Q2 is set to F, Q2 becomes F and is inputted at one input of B2 and the input of gl of the combinational circuit 13. Other outputs Q1 of input searcher I. Q3. D.I.
, *E is X, so the other input Q3 of B2 is X, B3
One input of is Ql, and the output of gl is the inverse of F
is input. Therefore, the output of B2 is 1, and the output of B3 is Y, which is unknown since one input of B3 is X. Therefore, the output of B4 is also Y.

Since the output of B4 is Dl, it is input to the tester I as D I =Y. The searcher I senses this Y and notifies the searcher I of the unknown result. The input searcher I receives the notification from the checker I that it is unknown, and performs item number 2.
In other words, 0 is put in the state of Ql. Then, Figure 3 (b
), it is B1 and fails. Therefore, the input searcher I changes the state of item number 3, ie, Ql, from 0 to 1.

Then, the searcher I sends a message to Dl indicating Y, that is, an unknown state, and notifies the input searcher ■.

In the state of item number 4, Q3 is further set to 0. Then D
l becomes R and becomes a success. Then, the process shifts to pattern II generation mode. In other words, the selection circuit 21 is replaced by the input searcher II.
state, the mode of the selection circuit is switched so that the output of the searcher II is fed back to the input searcher. In item No. 5, Ql, Q2゜Q3 are respectively 1, 1. When set to O, the output g4 of the combinational circuit 13 becomes 0, which violates D1=1 in item number 5, resulting in a failure. This means that the pattern I that allows the propagation of F in Q2 is generated, but the pattern I
This means that I is not generated. Therefore, the mode for generating pattern I is entered once again.

That is, input searcher I and searcher II are used.

FIG. 7(b) shows the state of item number 4. That is, Ql is 1
, Q2 is F and Q3 is O. At this time, the output of the combinational circuit 13 becomes R, and the tester I notifies that the searcher I is successful.

FIG. 7(C) shows the state of item number 6. In other words, item number 6
is the second half of the generation of pattern II, and Q3. is the output of input searcher II. Q2. Ql is each fixed at 0.1.1, but Dl and *E are in the X state. Since the mode is pattern II, the result of input searcher II is input to combinational circuit 13. Since Q2 is 1, the output of gl is 0, and since Q3 is O, the output of g2 is 1.
, g3 becomes 1 since gl is 0. Therefore,
l is input to g4, and Di becomes O. When this O is entered into the searcher ■, the searcher ■ has the constraint conditions DI, D2. Since it is stored in advance that D3 is 1.0.0, a check is performed on DI among them.

In this case, the output of g4 is 0, so the stored D
It is contradictory to I=1. Therefore, the input searcher side is notified of impossibility, which means failure. Note that the output of the input searcher (■) is Ql, Q2, . The value of Q3 is 1, F, O and DI,
*The state of X and X of E is still being output.

FIG. 7(d) shows the state of item number 7. Item No. 7 is a state for finding pattern I again, and input searcher I and searcher I are used. Item number 7 is Ql is 1, Q2 is F, Q3
is 1. DI and *E are X. These outputs of the input searcher (2) are applied to the combinational circuit 13 via the selection circuit 21.

Since Q2 is F, the output of gl is R. The output of g2 is R because Q3 is 1 and Q2 is F. g3
Since Ql is 1, the output of is F, which is a propagation of R of the input of g3. Therefore, since R and F are input to g4, 8
1, that is, 1 and fails. To form item No. 8, the input searcher ■ selects Ql, Q2 . Q3. Di, *E
is X, F.

X, X, X becomes the same as the starting state, that is, the state of item number 1, and becomes impossible. At this time, there is no condition to propagate F of Q2. In other words, since it turns out that this is not possible, the pattern I is controlled to propagate R of Q2, resulting in item number 9.

FIG. 7(e) shows the state of item number 9. Q2 is fixed at R. At this time, in the combinational circuit 13, the output of gl becomes F, but since Ql is X, the output of g3 becomes an unknown Y, the output of g2 becomes X, and the output of g4 becomes Y, which is an unknown state. It is. Therefore, to proceed, Ql is O
Make it. As shown in FIG. 4(a), in this case, D
Since I becomes 0 and the process fails, go to item No. 11 and change Ql to 1.

At this time, since DI is Y and unknown, X in Q3 is changed to 0 in order to further advance the tree search. At this time, Dl becomes F and is successful.

The state of item number 12 is shown in Figure 7). Input searcher I
The output of Ql is 1, Q2 is R, Q3 is O and Dl is X,
*E is X. At this time, using the signal input to the combinational circuit 13, the output of gl is F since Q2 is R.
becomes. The output of g2 is 1 since Q3 is O. g
The output of 3 is R because Ql is 1 and the output of gl is F. Therefore, the output of g4 becomes F, and the activation state propagates, resulting in success. In other words, pattern I has been found. The checker ■ notifies this to the input searcher as a success.

Move on to item number 13. FIG. 7(2) shows the state of item number 13 in which the input searcher ■ and the searcher II are connected. From the logic found in item No. 12, the input searcher 2 outputs the constraints that Ql is 1, Q2 is 0, and Q3 is 0, and in the searcher H, DI, D2°D3 are 1 and 1.0, respectively.
Remember that. Then, pattern II is generated. From the state of item number 13, gl, g2. Since g3 is 1 and 1°0, the output of g4 is 1, that is, Dl is 1. However, since D2 is in the state of ・X, it ends in failure. Therefore, move on to item number 15. That is, D
Change l from X to 0. Even if this is changed, D2 remains X, so it is unknown. Therefore, we advance the tree search and *E
further change to O. If E is 0, it becomes unknown because D2 is O.

FIG. 7(c) shows the state of item number 17. The outputs of the input searcher 2 are Ql, Q2 . Q3. Di, *E is 1°0, O,0
, 1. At this time, the output of gl is 1 because Q2 is 0, the output of g2 is 1 because both g2 and g3 are 0, and the output of g3 is O because the output of gl is 1 and the output of Ql is 1. Therefore, the output of g4 becomes 1. Therefore,
DI becomes 1. Furthermore, since DI is O1*E is 1, D2. D3 becomes 1 and 0, respectively. This is a state of success. In other words, this means that pattern ■ has also been found.

FIG. 8 is a hardware configuration diagram of the input searcher. (
(a) is a block diagram of the input searcher, (b) is a schematic diagram of its operation, and (C) is an internal configuration diagram of the first cell Isi of the input searcher.

The input searcher replaces patterns in synchronization with the clock. In the initial state, the output of all Is is X.

The l5(7) output, which is active due to MD, 1 = 1, is active due to MD, 1 = 0, as shown in Figure 8(C).
When , the output of Is which is 1nactive is O, R, F
, 1. X→■→ko v-+X
and changes. For (2), 0 or 1 is designated by MD, 0.

Regarding Btrk coming from the output tester, Btrk=OO
The input searcher does not work when . When Btrk=01, the input searcher is reset (all Is outputs are set to X), and when Btrk=10, the input searcher advances.

When Btrk=11, the input searcher backtracks or banks tracks. The carry (CR, CL) is I S (MD, 2
=O) status is transmitted. CR becomes 1 when all the outputs of the TSs to the left of itself are not X. CL becomes 1 when there is an IS outputting ■ to the right of itself. The leftmost l5 (ISa) CR input value is 1, and the rightmost one is ■5.
The CL input value of (Isn,,) is 0.

For example, when the input searcher is in the state shown in FIG. 8(b) (all MDz=000), when moving forward, X is the output value of the rightmost IS that is outputting ■. That is, the output of IS9, which is inputting CR=1 and outputting X, is set to 0.

When moving backward, the output value of the rightmost S which outputs ■ is set to =VC inversion), and the output of Is located to the right is set to X. In other words, CL=O is input, and O
The output of IS6 which outputs 1 is assumed to be 1, and the output of IS'l and IS8 which input CL=O and output 1 is assumed to be X.

FIGS. 8C and 8D show the internal structure of each cell of the input searcher and the truth table of each block, respectively. The CRi block receives and receives 1 bit of information from CR1-+, and
It receives 3 bits of information from Dt and outputs CRt. As shown in the truth table, the initial value is O, and CR1-+
When is a, and when MDi=1**, CRi is a. Regardless of the state of CRt-+, CR1 is 1 when PCI is 0 or 1 and when MD is -0**
becomes. P.C.

When is X, CRt becomes O. Its output is 3
It's bit.

When determining the PCI output, when the current PGt is a and the back track signal Btrk is OO, the next PGJ will be a. When the mode signal MD is lO,
If the back track signal Btrk is not 00, PGt becomes 0.

When the mode signal M D t is 111, and also B
If trk is not OO, it becomes 1. MDt is 110
, Bt rk is not OO, becomes F.

MDz = 101-v PG when Btrk is not OO
i becomes R. When M Di is Q** and Btrk is 01, then X, MDz is O*a, Pet = X, and CCi =
1'+Btrk-10, it is X. And M.D.
When the upper bit of i is 0, pc is a, and Btrk is 10, PGi is a. With MDi=0*0, P
C is 0, B t , 7 k is 1°1,
Furthermore, when PCI is 0 and the lower bit of CCs is O, P
G( is 1, PGi is O, 0 when the lower bit of CC1 is 1, PGt is 1, X when the lower bit of CCt is 00,
1 when PCI is 1 and the lower bit of CC1 is 1
, when PGi is X and CCi is **, it becomes X. Further, when MDI is O*1 and Btrk is 11, PGt is 1. 0 when the lower bit of CCi is O. PCI is 1. 1 when the lower bit of CCt is 1, xSp when PGl is 0 and the lower bit of CC4 is 0
When the lower bit of,c,is 1 in O,CC,,o,pc,
When is X and CCi is **, it becomes X.

FIG. 9 is a mode pattern diagram of a cell that generates fixed conditions for each item number in FIG. 3, etc.). For items 1 to 8, Q2 is F.
M D 1 of ISl is set to 110 in order to fix it to . In addition, in items 5 to 6, in order to set Ql and Q2 to 1, I
MD of So and IS is set to 111, and MD is set to 100 to set Q3 to 0.

In items 9 to 16, Q2 is set to R, so IS.

Set M D i to 101, and in items 13 to 16, Q
To set l to 1, set MDi of TSo to 111, and to set Q2 and Q3 to 0, set M D t of IS+ and ISz to 1.
It is set to 00.

FIG. 10(a) is a functional block diagram for processing of the present invention. A path is set in S21. That is, the constraint conditions for pattern I are set, and pattern I is set in S22.
is generated. If pattern (2) cannot be generated, that is, if it is impossible, it is determined that it is impossible to test. If pattern I has been generated and is “successful”, the process moves to S23;
After setting the constraint conditions for pattern II, proceed to step S24.
Pattern II is generated. If pattern (2) cannot be generated, that is, if it is impossible, the process returns to S22 and pattern I is generated again. Pattern I at S24
If the generation of I is successful, i.e. a solution is found. Pattern I, pattern ■, and expected values for pattern I are stored.

FIG. 10 (1)) is a processing flow in path setting. Based on a given path, the operation logic of gates not on the path and gates on the path are set separately. For gates on the path, it also recognizes which input bins are on the path and sets them to correspond to the operation logic (32
5). Also, set the starting point of the path to R or F.

FIG. 10(C) is a functional block diagram for the process of generating pattern I. At step 326, one input is selected from among the inputs that have a degree of freedom in value, that is, X, and the value is set to 0 to 1.

Moving on to 327, based on the truth table of the combinational logic part,
Perform a simulation. In this case, a primitive truth table is used. At step 328, the output checking unit checks whether F or R is detected at the end of the path. If yes, signal the discovery of pattern I (
S29). If no, check at 830 if it is possible, and if it is yes, go back and toss the degree of freedom to 0 or 1. If there is no possibility, the process moves to S31. Most recently, the value of the input is changed from X to 0 (or 1), and the value of the input that has not been replaced with 1 (or O) is replaced with 1 (or 0).

Furthermore, since the value of the input changed from X to 0 (or 1) has already been changed, the value is returned to X. Then, the process moves to S32. Here, only the path starting point is R or F.
Then, check whether all others have returned to X (332). If the answer is YES, the situation is impossible, so it is notified that there is no solution (S33). If not, return to 327 to continue the simulation.

FIG. 10(d) is a processing flow for setting constraints for pattern II. In S41, for an input having a value determined in pattern I, that input is fixed to the determined value in the search for pattern II.

However, if the starting point value of the path is R, it is fixed to O, and if it is F, it is fixed to 1. Then, proceeding to S42, the combinational circuit section 1
If there is a relationship between the input and output of 3, that is, when a clock is applied, the value of a certain output is transmitted as the value of a certain input, that is, if there is a relationship between the input and output of a register,
Using pattern ■, fix the output value corresponding to the input whose value has been determined to the input value. However, if the input value is R, 1
, F is fixed to 0.

FIG. 10(e) is a functional block diagram of the process of generating pattern II. In step 343, first, one input is selected from among the inputs that have a degree of freedom in value, that is, the input that is X, and the value is set from 0 to 1. Then, in S44, a simulation is performed based on the truth table of the combinational logic section. In this case, a non-primitive truth table is used.

In S45, it is checked whether the output value matches the fixed output condition (546), and if yes, pattern II is discovered. If no, see if there is a mismatch. If there is no mismatch, the process returns to step 343, and if YES, the process goes to step S47.

Here, the value of the input whose value was most recently changed from χ to 0 (or 1) and whose value has not been replaced with 1 (or 0) is replaced with 1 (or 0). Further, for subsequent inputs that are changed from X to 0 (or 1), the value is returned to X because the value is always replaced. Then, the process moves to 348, where it is observed whether all input values other than the fixed conditions have returned to X (348). If it has returned, the result is 549) without an answer, but if it has not returned, the result is NO and the process returns to 344 of the simulation.

〔Effect of the invention〕

As described above in detail, according to the present invention, it becomes possible to test for delay failures in LSI, which has been difficult in the past. Furthermore, the tester required for this purpose can be easily configured by adding a circuit that generates two high-speed lock pulses to a conventional static fault inspection tester for scan testing.

[Brief explanation of drawings]

FIG. 1 is a system configuration diagram of the present invention, FIG. 2(a) is a processing overview diagram of the system of the present invention, FIG.
) is a diagram showing the processing flow of the test section, FIG. 2(d) is a conceptual diagram of the operation of the pattern generation section for obtaining the human cover turn ■, and FIG. 2(e) is a conceptual diagram of the operation of the pattern generation section for obtaining the input pattern II. , FIG. 3(a) shows pattern 1 of the present invention. Circuit diagram used in the example used to determine pattern II, FIG. 3 (
b) is an example diagram of the search order showing the generation procedure of patterns I and II; FIG. 3 (C3 is the processing flow of the test section; FIG. Figure (e) is a time chart showing an explanation of the operation of the present invention, Figure 4 is a diagram showing a simulation for human cover turn I, Figure 5 (a) is a diagram of the mechanism principle of the present invention, Figure 5 (5) is a schematic diagram of the operation of the pattern generation circuit, FIG. 6 is a diagram of the input pattern generation circuit of the present invention, and FIG. 7 is a diagram of the operation of the pattern generation circuit (
It is a diagram showing the state of item numbers in the generation of B I and II in b), (a) the state of item number 1, (b) the state of item number 4, (
C) is the state of item number 6, (d) is the state of item number 7, (e) is the state of item number 9, (f) is the state of item number 12, ((to) is the state of item number 13, (5) is the state of item number 17, Figure 8 (a)
is a block diagram with an input searcher, and FIG. 8(b) is a block diagram with an input searcher.
), FIG. 8(C) is an internal configuration diagram of the i@th cell Isl of the input searcher, FIG. 8(d) is the truth table of each block of the input searcher, and FIG. 9 is the mode pattern of the cell that generates the fixed conditions for each item number in FIG. 3(b), FIG. 10(a) is a functional block diagram for the processing of the present invention, and FIG. Processing flow 1st
0 (C) is a functional block diagram for the generation process of pattern I of the present invention, and FIG. 10 (d) is a processing flow for setting constraints for pattern II of the present invention. Functional block diagram for pattern II generation processing of the invention. FIG. 11 is a block diagram showing a conventional scan path method. 91... Input pattern generation means 92... Expected value 93... Testing means... Path setting means S22... Pattern r generation means S24...
- Pattern ■ generation means 327.344...Simulation means 828...Detection means S31. S32. S47. S48...Tree search means selection means S45° inspection means

Claims (8)

[Claims] (1) Input pattern I generation means (
91), and an input pattern II generating means for obtaining an input pattern II such that the input pattern I is set in a register at the input section of the combinational circuit by hitting one clock that causes the input pattern I to be set in the register in the logic circuit. (91
) After scanning in the input pattern II, the clock is struck twice at the operating specification frequency of the logic circuit, and the inspection pass is confirmed as the input pattern II changes to the input pattern I at the first clock. The input pattern to be converted is set in the register, the test path is formed by the logic of the input pattern I, the change in the logic state is output from the output of the combinational circuit, and the result is stored in the register. After setting with the second clock, scan out the result and find the expected value (92)
1. A delay fault testing method characterized by having a test means (93) for comparing the delay faults present on a test path of a logic circuit. (2) path setting means (S21) for providing constraint conditions for determining an input pattern I that activates a specific test path of a combinational circuit from a register output of a logic circuit to the next register input; and the input pattern. means for generating pattern I (S22); and if the pattern I generation means cannot generate the pattern I, it is determined that the test is not possible, and when the pattern I is generated, the input pattern I is A pattern to obtain an input pattern II that is set in the register at the input part of the combinational circuit by hitting one clock that is set in the register.
In the setting means (S23) for setting the constraint conditions of II, the means (S24) for generating the pattern II, and the generating means for the pattern II, if there is no solution, the
A delay fault inspection method characterized in that the I generation is performed again, and if the pattern II is generated, the pattern I, the pattern II, and the expected value are output. (3) Based on the given path, the path setting means distinguishes the operation logic of gates on the path and gates not on the path, and creates a truth table for gates on the path using a path-sensitive truth table ( Express the input-output relationship using Figure 4 (1)), and for gates that are not on the path, express the input-output relationship of the gate according to the non-path-sensitive truth table (Figure 4 (2)). Claim 2 characterized in that
Delayed failure inspection method described. (4) The pattern I generation means (S22) selects one input from among the inputs whose values have a degree of freedom, sets the value to 0 (or 1), and sets the value to 0 (or 1). a simulation means (S27) that executes a simulation of a combinational logic unit according to a primitive truth table; a detection means (S28) that detects whether a change in logic is detected at a path end point; If no change is detected,
First, check whether there is still a possibility, and if so, return to the selection means, and if there is no possibility, change the value from the most recent state of don't care (X) to 0.
(or 1), and the value of the input that has not been replaced with 1 (or 0) is replaced with 1 (or 0), and after that, the input that is changed from X to 0 (or 1) For , a search is performed to return the value to
3. The delay fault testing method according to claim 2, further comprising tree search means (S31, S32) for searching whether the state has returned to the state of (S31, S32). (5) The means for setting the constraint conditions for the pattern II is:
For an input with a value determined in Pattern I, the input is fixed at that determined value in the search for Pattern II, and if there is a relationship between the input and output of the combinational circuit section, the value is determined in Pattern I. means for setting the value of the output corresponding to the input to be fixed at the value of the input (S41, 4
3. The delayed fault inspection method according to claim 2, further comprising: 2). (6) The pattern II generation means selects one input from among the inputs that have a degree of freedom in value, and sets the value to 0 (or 1).
); a simulation means (S44) that performs a simulation based on a non-path primitive truth table of the combinational logic unit; Inspection means to be inspected (S45, S46
) and the inspection means, the most recent value of the input that has been changed from X to 0 (or 1) and has not been replaced with 1 (or 0) is set to 1.
(or 0), and after that, for inputs that have been changed from don't care X to 0 (or 1), perform a search to return the value A tree search method that continues until it returns to X (S
47, S48). 3. The delayed fault inspection method according to claim 2, further comprising: (7) An input pattern I that activates a specific path of a combinational circuit from a register output of a logic circuit to the next register input, and that input pattern I causes one clock to be set in the register of the logic circuit. As a result, the input searcher for finding the input pattern II that is set in the register at the input part of the combinational circuit will move forward in the search by selecting the rightmost input pattern that outputs X in the don't care state. If you want to move backward by setting the output value of the cell on the left (left) to 0 to 1, invert the output value of the rightmost (left) cell that outputs a value of 1 to 0, and 2. The delay fault testing method according to claim 1, wherein hardware for tree search is used in which the output of the cell on the left side is set as a don't care X. (8) When determining the input pattern I, the signal states of the input terminals on the test path for the 2-input gate and the output signals for the input terminals not on the test path are calculated using a path primitive truth table, and 0 is a logic value. Low level of value, 1 is high level, R is change from 0 to 1, F is change from 1 to 0, X is undefined whether it is 0 or 1, B0 is search failure with 0, B1
2. The delay fault testing method according to claim 1, wherein the search is performed using expressions such as 1 indicates failure, and Y indicates an unknown state.