JPH02285704A - Variable gain differential amplifier circuit - Google Patents

Variable gain differential amplifier circuit

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Publication number
JPH02285704A
JPH02285704A JP10687889A JP10687889A JPH02285704A JP H02285704 A JPH02285704 A JP H02285704A JP 10687889 A JP10687889 A JP 10687889A JP 10687889 A JP10687889 A JP 10687889A JP H02285704 A JPH02285704 A JP H02285704A
Authority
JP
Japan
Prior art keywords
circuit
resistors
amplifier circuit
differential amplifier
trs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10687889A
Other languages
Japanese (ja)
Inventor
Masahiro Goto
真宏 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Cable Ltd
Original Assignee
Hitachi Cable Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Cable Ltd filed Critical Hitachi Cable Ltd
Priority to JP10687889A priority Critical patent/JPH02285704A/en
Publication of JPH02285704A publication Critical patent/JPH02285704A/en
Pending legal-status Critical Current

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  • Control Of Amplification And Gain Control (AREA)

Abstract

PURPOSE:To operate the circuit with a low power supply voltage by constituting an emitter constant current bias source for a 1st and a 2nd differential amplifier circuit with a common emitter circuit and driving each base with a 3rd differential amplifier circuit whose input terminal receives a gain control voltage. CONSTITUTION:With a control voltage applied between terminals 5, 6, a ratio of collector currents of transistors(TRs) 21, 22 is changed. TRs 16, 18, resistors 37, 41 and TRs 16, 17, resistors 38, 40 constitute respectively a current mirror circuit, and a collector power supply comprising the TRs 21, 26 and TRs 22, 15 has a prescribed ratio depending on the ratio of the resistors 38, 40 and the resistors 37, 41 respectively. Thus, the resistance of the resistors 37, 38 and the resistors 40, 41 is selected respectively the same to make the sum of collector currents of the TRs 15, 16 to be a constant value having a prescribed ratio to the current of the constant current source 9. Collectors of the TRs 15, 16 are connected to two sets of differential TRs 11, 12 and 13, 14 connecting to same load resistors 31, 32 via emitter resistors 33-36, the control voltages 5, 6 are varied to vary the gain of the amplifier circuit comprising the TRs 11-14 and the resistors 31-36.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は利得制御の可能な増幅回路に係り、特に集積回
路に好適で、低電圧動作が可能な可変利得差動増幅回路
に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an amplifier circuit capable of gain control, and particularly to a variable gain differential amplifier circuit suitable for integrated circuits and capable of low voltage operation.

[従来の技術] 第5図は従来の電流和n型差動増幅回路の一例である。[Conventional technology] FIG. 5 shows an example of a conventional current summation n-type differential amplifier circuit.

第5図において、入力端子5と6に印加された利得制御
信号によりトランジスタ15と16で構成された差動増
幅回路の各コレクタ電流が制御される。トランジスタ1
9は上記差動増幅回路に用いる定電流回路として動作す
る。1−ランリスタ15と16のコレクタ電流は夫々抵
抗33〜36を介し、二つの差動回路を構成するトラン
ジスタ11と12、及び13と14のエミッタに入力さ
れる。上記トランジスタ11と14、及び12と13の
ベースは互に共通に接続され、その間に入力信号電圧が
印加される。又、トランジスタ11と13、及び12と
14のコレクタも互いに共通に接続され、抵抗31、又
は32端の信号電圧が端子3、又は4より出力電圧が取
り出される。この出力電圧の大きさは上記の制御電圧に
よって制御することができるので本回路はり変利得の差
動増幅回路として動作する。
In FIG. 5, each collector current of a differential amplifier circuit composed of transistors 15 and 16 is controlled by gain control signals applied to input terminals 5 and 6. transistor 1
9 operates as a constant current circuit used in the differential amplifier circuit. The collector currents of the 1-run listers 15 and 16 are input to the emitters of transistors 11 and 12 and 13 and 14, which constitute two differential circuits, through resistors 33 to 36, respectively. The bases of the transistors 11 and 14 and 12 and 13 are commonly connected to each other, and an input signal voltage is applied between them. Further, the collectors of the transistors 11 and 13, and the collectors of the transistors 12 and 14 are also connected in common, and the signal voltage at the end of the resistor 31 or 32 is taken out as an output voltage from the terminal 3 or 4. Since the magnitude of this output voltage can be controlled by the above-mentioned control voltage, this circuit operates as a differential amplifier circuit with variable gain.

[発明が解決しようとする課題] 第5図を用いて説明した従来回路では、電源端子8と接
地電位間に二つの差動回路と夫々のエミッタ抵抗、及び
コレクタ抵抗等を直列に接続する必要上、少なくとも3
■以上の電源電圧を必要とし、更に、比較的高い電源電
圧を用いる割に得られる最大の出力電圧が低いという問
題があった。
[Problems to be Solved by the Invention] In the conventional circuit explained using FIG. 5, it is necessary to connect two differential circuits, their respective emitter resistors, collector resistors, etc. in series between the power supply terminal 8 and the ground potential. top, at least 3
(2) It requires a power supply voltage higher than 1, and furthermore, there is a problem that the maximum output voltage that can be obtained is low even though a relatively high power supply voltage is used.

特に、昨今の集積回路においては微細化が進み、その耐
圧が低下しつつあり、低い電源電圧で大きな出力電圧が
得られ、同時に高利得が得られる回路構成が要求されて
いるので、上記従来回路は不都合である。
In particular, recent integrated circuits are becoming increasingly finer and their withstand voltages are decreasing, and there is a demand for circuit configurations that can obtain a large output voltage with a low power supply voltage and high gain at the same time. is inconvenient.

本発明の目的は、上記従来回路の欠点を解消し、低い電
源電圧で大きな出力電圧と高利得が得られる可変利得差
動増幅回路を提供することにある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a variable gain differential amplifier circuit that eliminates the drawbacks of the conventional circuit and provides a large output voltage and high gain with a low power supply voltage.

[課題を解決するための手段] 本発明は上記の目的を達成するために、第一の差動増幅
回路の一対のベース入力端子と第二の差動増幅回路の一
対のベース入力端子の夫々を共通に接続して入力信号を
印加し、上記第一の差動増幅回路の入力信号と同相の出
力信号を出力するコレクタと上記第二の差動増幅回路の
逆相の出力信号を出力するコレクタを共通に接続し、同
様に上記第一の差動増幅回路の逆相の出力信号を出力す
るコレクタと上記第二の差動増幅回路の同相の出力信号
を出力するコレクタを共通に接続した電流加算型差動増
幅回路において、上記第一と第二の差動増幅回路のエミ
ッタ定電流バイアス源の夫々をエミッタの接地回路で構
成し、該二つのエミッタ接地回路の夫々のベースを、ダ
イオード抵抗素子の直列接続回路をコレクタ負荷とし、
その入力端子に利得制御電圧を印加した第三の差動増幅
回路により駆動するようにする。
[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for each of a pair of base input terminals of a first differential amplifier circuit and a pair of base input terminals of a second differential amplifier circuit. are connected in common and an input signal is applied to the collector, which outputs an output signal in phase with the input signal of the first differential amplifier circuit, and an output signal of the opposite phase of the second differential amplifier circuit. The collectors are connected in common, and similarly, the collector that outputs the opposite phase output signal of the first differential amplifier circuit and the collector that outputs the in-phase output signal of the second differential amplifier circuit are connected in common. In the current addition type differential amplifier circuit, each of the emitter constant current bias sources of the first and second differential amplifier circuits is configured with an emitter grounded circuit, and the base of each of the two emitter grounded circuits is connected to a diode. A series connection circuit of resistive elements is used as a collector load,
It is driven by a third differential amplifier circuit to which a gain control voltage is applied to its input terminal.

[作  用] 以上のように構成した可変利得差動増幅回路は電源と接
地電位間に挿入されていたトランジスタの数を一つ減ら
すことができるので、従来回路より低い電源電圧で動作
する。
[Operation] The variable gain differential amplifier circuit configured as described above can reduce the number of transistors inserted between the power supply and the ground potential by one, and therefore operates at a lower power supply voltage than the conventional circuit.

[実 施 例] 以下、本発明の実施例の構成を第1図〜第4図を用いて
説明する。第1図において、定電流源9により動作する
PNPトランジスタ対21.22のコレクタに、ダイオ
ード接続されたトランジスタ17.18と抵抗39.4
0の直列接続回路が夫々負荷として接続されている。端
子5.6間に制m+rFi圧を印加することにより、ト
ランジスタ21.22の]レクタ電流値の比を変化させ
ることができる。トランジスタ15.18、抵抗37゜
41とトランジスタ16.17、抵抗38.40は夫々
カレント・ミラー回路を構成しており、トランジスタ2
1とトランジスタ16、トランジスタ22とトランジス
タ15のコレクタ電流は夫々抵抗38と抵抗40、抵抗
37と抵抗41の比により決まる一定の比を有している
。従って、抵抗37.38、及び抵抗40.41の抵抗
値を夫々同じにすることにより、トランジスタ15.1
6のコレクタ電流の和を定電流源9の電流値と一定の比
を持った一定値とすることができる。そこで、トランジ
スタ15.16のコレクタを夫々のコレクタが同一の負
荷抵抗31.32に接続された、二組の差動トランジス
タ対11.12と13゜14へ夫々のエミッタ抵抗33
〜36を介して接続し、制御11m圧5.6を変化させ
れば、これら二組のトランジスタ対の差動電流の総和を
一定に保ったまま抵抗31と32に流れる′Fi流比を
変化させることができる。その結果、トランジスタ11
〜14、抵抗31〜36により構成する増幅回路の利得
を可変とすることができる。
[Example] Hereinafter, the configuration of an example of the present invention will be described using FIGS. 1 to 4. In FIG. 1, a diode-connected transistor 17.18 and a resistor 39.4 are connected to the collectors of a PNP transistor pair 21.22 operated by a constant current source 9.
0 series connected circuits are each connected as a load. By applying a control m+rFi pressure across terminals 5.6, the ratio of the rector current values of transistor 21.22 can be varied. Transistor 15.18, resistor 37°41, transistor 16.17, and resistor 38.40 constitute a current mirror circuit, and transistor 2
The collector currents of transistor 1 and transistor 16 and transistor 22 and transistor 15 have a constant ratio determined by the ratio of resistor 38 to resistor 40 and resistor 37 to resistor 41, respectively. Therefore, by making the resistance values of the resistors 37.38 and 40.41 the same, the transistor 15.1
The sum of the collector currents 6 and 6 can be set to a constant value having a constant ratio to the current value of the constant current source 9. The collectors of the transistors 15.16 are then connected to the respective emitter resistors 33 to two differential transistor pairs 11.12 and 13.14, the respective collectors of which are connected to the same load resistor 31.32.
~36, and by changing the control 11m pressure 5.6, the 'Fi current ratio flowing through the resistors 31 and 32 can be changed while keeping the sum of the differential currents of these two transistor pairs constant. can be done. As a result, transistor 11
14, the gain of the amplifier circuit constituted by the resistors 31 to 36 can be made variable.

第1図に示した本発明の実施例回路と第5図に示した従
来回路を比較すると、電源端子8と接地点間に、第5図
の場合は、トランジスタが3ヶ直列に挿入され、一方、
第1図の場合は2ヶ直列に挿入されていることがわかる
。゛従って、本発明には上記トランジスタ数が少ない分
だけ電源電圧を低く設定できるという利点が得られるの
である。
Comparing the circuit according to the embodiment of the present invention shown in FIG. 1 and the conventional circuit shown in FIG. 5, in the case of FIG. 5 three transistors are inserted in series between the power supply terminal 8 and the ground point. on the other hand,
In the case of Fig. 1, it can be seen that two pieces are inserted in series. Therefore, the present invention has the advantage that the power supply voltage can be set low because the number of transistors is small.

上記の利点は以下に第2〜4図を用いて説明する本発明
の他の実施例においても同様に11られる。
The above-mentioned advantages can be similarly applied to other embodiments of the present invention described below with reference to FIGS. 2 to 4.

第2図はトランジスタ23〜25、抵抗42〜44、電
流設定電圧7により構成した本発明の他の実施例である
。トランジスタ23が上記定電流源の電流を供給し、ト
ランジスタ24.25と抵抗42と44等の直列回路は
、トランジスタ23のベースに与えるバイアス電圧を発
生する。
FIG. 2 shows another embodiment of the present invention constructed by transistors 23 to 25, resistors 42 to 44, and current setting voltage 7. Transistor 23 supplies the current of the constant current source, and a series circuit including transistors 24 and 25 and resistors 42 and 44 generates a bias voltage to be applied to the base of transistor 23.

第3図は、第1図のトランジスタ11〜14のペース端
子対を分離し夫々に独立の入力信号を印加した本発明の
他の実施例である。入力端子1と2.51と52を夫々
を対として、二つの信号を入力することにより、2信号
の切替、アナログの加減演算等に利用することができる
。この時、差動トランジスタ対のエミッタ抵抗33〜3
6はすべて同じ値としてもよい。
FIG. 3 shows another embodiment of the present invention in which the pair of pace terminals of transistors 11 to 14 of FIG. 1 are separated and independent input signals are applied to each pair. By inputting two signals to the input terminals 1, 2, 51 and 52 as a pair, it can be used for switching between two signals, analog addition/subtraction calculations, etc. At this time, the emitter resistances 33 to 3 of the differential transistor pair
6 may all have the same value.

第4図は第1〜3図において、トランジスタ15〜18
、抵抗37.38.40.41等により構成されるカレ
ント・ミラー回路部分にトランジスタ26.27を追加
し、夫々を3トランジスタ型のカレント・ミラー回路と
してミラー係数を上げた本発明の他の実施例回路である
。トランジスタ15〜18の電流増幅率hFEが比較的
小さい場合や、複数の電流源回路を制御する場合等に特
に有効である。
Figure 4 shows transistors 15 to 18 in Figures 1 to 3.
Another embodiment of the present invention in which transistors 26, 27 are added to the current mirror circuit portion constituted by resistors 37, 38, 40, 41, etc., and each of them is made into a 3-transistor type current mirror circuit to increase the mirror coefficient. This is an example circuit. This is particularly effective when the current amplification factor hFE of the transistors 15 to 18 is relatively small or when controlling a plurality of current source circuits.

[発明の効果1 以上詳述したように本発明を適用すると、従来の電流加
算型可変利得差動・増幅回路において電源と接地電位間
に挿入されていたトランジスタの数を一つ減らすことが
できるので、電源電圧を1V程度低くした電流加算型可
変利得差動増幅回路を提供することができる。
[Effect of the invention 1 As detailed above, when the present invention is applied, the number of transistors inserted between the power supply and the ground potential in the conventional current addition type variable gain differential amplifier circuit can be reduced by one. Therefore, it is possible to provide a current addition type variable gain differential amplifier circuit in which the power supply voltage is lowered by about 1V.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の電流加算型可変利得差動増幅
回路の構成を示す図、第2図は本発明の実施例の具体的
な構成例を示す図、第3図、第4図は本発明の他の実施
例の構成を示す図、第5図は従来のTi電流加算型可変
利得差動増幅回路構成例を示す図である。 1、 2. 51. 52 3.4 5.6 11〜18.25〜27 21〜24 31〜38 :差動信号入力端子、 :差動信号出力端子、 :利得制御信号入力端子、 :定電流源用基準電圧 入力端子、 正Ti源端子、 定電流源回路、 NPNトランジスタ、 PNPトランジスタ、 抵抗。 児 国 第 聞 光 帛 目
FIG. 1 is a diagram showing the configuration of a current addition type variable gain differential amplifier circuit according to an embodiment of the present invention, FIG. 2 is a diagram showing a specific configuration example of the embodiment of the present invention, FIGS. This figure shows the configuration of another embodiment of the present invention, and FIG. 5 is a diagram showing an example of the configuration of a conventional Ti current addition type variable gain differential amplifier circuit. 1, 2. 51. 52 3.4 5.6 11~18.25~27 21~24 31~38: Differential signal input terminal, : Differential signal output terminal, : Gain control signal input terminal, : Reference voltage input terminal for constant current source , positive Ti source terminal, constant current source circuit, NPN transistor, PNP transistor, resistor. Children's country light shield

Claims (1)

【特許請求の範囲】[Claims] 1、第一の差動増幅回路の一対のベース入力端子と第二
の差動増幅回路の一対のベース入力端子の夫々を共通に
接続して入力信号を印加し、上記第一の差動増幅回路の
入力信号と同相の出力信号を出力するコレクタと上記第
二の差動増幅回路の逆相の出力信号を出力するコレクタ
を共通に接続し、同様に上記第一の差動増幅回路の逆相
の出力信号を出力するコレクタと上記第二の差動増幅回
路の同相の出力信号を出力するコレクタを共通に接続し
た電流加算型差動増幅回路において、上記第一と第二の
差動増幅回路のエミッタ定電流バイアス源の夫々をエミ
ッタの接地回路で構成し、該二つのエミッタ接地回路の
夫々のベースを駆動するためのダイオード抵抗素子の直
列接続回路をコレクタ負荷とし、その入力端子に利得制
御電圧を印加する第三の差動増幅回路を備えたことを特
徴とする可変利得増幅回路。
1. A pair of base input terminals of the first differential amplifier circuit and a pair of base input terminals of the second differential amplifier circuit are each connected in common and an input signal is applied to the first differential amplifier. A collector that outputs an output signal in phase with the input signal of the circuit and a collector that outputs an output signal of the opposite phase of the second differential amplifier circuit are connected in common, and similarly, a collector that outputs an output signal in phase with the input signal of the circuit is connected in common, In the current addition type differential amplifier circuit in which a collector that outputs a phase output signal and a collector that outputs an in-phase output signal of the second differential amplifier circuit are connected in common, the first and second differential amplifiers Each of the emitter constant current bias sources of the circuit is configured with a grounded emitter circuit, a series-connected circuit of diode resistance elements for driving the bases of each of the two grounded emitter circuits is used as the collector load, and a gain is connected to the input terminal of the circuit. A variable gain amplifier circuit comprising a third differential amplifier circuit that applies a control voltage.
JP10687889A 1989-04-26 1989-04-26 Variable gain differential amplifier circuit Pending JPH02285704A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10687889A JPH02285704A (en) 1989-04-26 1989-04-26 Variable gain differential amplifier circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10687889A JPH02285704A (en) 1989-04-26 1989-04-26 Variable gain differential amplifier circuit

Publications (1)

Publication Number Publication Date
JPH02285704A true JPH02285704A (en) 1990-11-26

Family

ID=14444778

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10687889A Pending JPH02285704A (en) 1989-04-26 1989-04-26 Variable gain differential amplifier circuit

Country Status (1)

Country Link
JP (1) JPH02285704A (en)

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