JPH02284536A - Acoustic reproduction device - Google Patents

Abstract

PURPOSE:To prevent beat interruption by means of the clock pulse signal of DSP by changing the frequency of a clock pulse supplied to the digital signal processing means (DSP) which signal-processes a digital audio signal in accordance with the reception frequency of a tuner. CONSTITUTION:A change over switch 5 supplies an audio signal from one of the tuner 1, a tape deck 2 and a CD player 3 to an A/D converter 6. The digital audio signal outputted from the A/D converter 6 is sound filed-controlled in accordance with a command in DSP 7 and outputted from a microcomputer 8. The digital audio signal outputted from DSP 7 turns into the audio signal outputs of two channels in right and left through a digital filter 10 and a D/A converter 11. A clock pulse generator 12 generates the clock pulse for the arithmetic operation of DSP 7, and two oscillators 13 and 14 with different frequencies are externally added through a change over switch 15 so that it can change the frequency of the clock pulse, whereby the frequency of the clock pulse is changed in accordance with the reception frequency of the tuner 1.

Description

TECHNICAL FIELD The present invention relates to a sound reproduction device having multiple audio signal sources including a tuner.

BACKGROUND ART There is a sound reproduction device that can perform sound field control to create reverberant sound and a sense of presence in an acoustic space such as a concert hall or a theater at home or in a car. Such a sound reproduction device is provided with a DSP (digital signal processor) that performs sound field control by digitally processing an audio signal output from an audio signal source such as a tuner. A DSP can perform calculation processing such as product-sum calculations at high speed, and therefore the frequency of the clock pulse of the DSP is set higher than that of a normal microcomputer. However, in tuners, harmonic signals of such clock pulses may mix into the receiving signal line and cause beat interference at the receiving frequency, especially when the oscillation frequency is high such as the clock pulse of a DSP. The problem was that it was large.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an audio reproduction device that prevents beat interference caused by a DSP clock pulse signal.

The sound reproduction device of the present invention includes a plurality of audio signal sources including a tuner, a first conversion means for converting an audio signal from any one of the plurality of audio signal sources into a digital signal, and a clock generator for generating clock pulses. digital non-digital signal processing means for processing the digital signal from the first conversion means in accordance with the clock pulse;
and second conversion means for converting the digital signal processed by the processing means into an analog signal, and the clock generation means changes the frequency of the clock pulse according to the receiving frequency of the tuner. It is said that

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

In the sound reproducing apparatus according to the embodiment of the present invention shown in FIG. 1, audio signals from a tuner as an audio signal source, a tape deck 2, and a CD player 3 are supplied to a function changeover switch 5. Changeover switch 5
supplies an audio signal from any one of the tuner 1, tape deck 2, and CD player 3 to the A/D converter 6.

The digital audio signal output from the A/D converter 6 is supplied to a DSP 7 as a digital signal processing means. The DSP 7 is composed of a one-chip integrated circuit including an adder, a multiplier, an accumulator, a RAM, a ROM, etc., and performs sound field control on the input digital audio signal according to instructions from the microcomputer 8 and outputs it. do.

Further, an external memory 9 is connected to the DSP 7 in order to obtain various desired delay times and create reflected sounds. DSP
A digital audio signal output from 7 is supplied to a D/A converter 11 via a digital filter 10. The output of the D/A converter 11 becomes the left and right two-channel audio signal output. Note that in reality, two channels of audio signals are output from the tuner], tape deck 2, and CD player 3, and these signals are selectively supplied to the A/D converter 6 by the changeover switch 5, but in the figure, shows only one channel for clarity.

The clock pulse generator 12 generates tarok pulses for the arithmetic operations of the DSP 7, and has two different frequency oscillators 13.1 to change the frequency of the clock pulses.
4 is externally attached via a changeover switch 15. The clock pulse generator 12 also has a clock pulse generation stop control terminal, and is adapted to stop generating clock pulses when this control terminal is set to a high level, for example. The switching of the changeover switch 15 and the stopping of generation of clock pulses are controlled by the microcomputer 8.

microcomputer 8 is microprocessor 2], R
It is equipped with AM22, ROM23, input/output ink faces 24 to 26, and a clock pulse generator (not shown), and includes a microprocessor 21, RAM22, and ROM2.
3 and interface 2425 are connected to each other by a bus. The interface 24 includes a DSP7,
The above clock pulse generation stop control terminal and changeover switch 15 are connected. Further, a tuner, tape deck 2, CD player 3, and changeover switch 5 are connected to the interfinice 25, and these are controlled by the microcomputer 8.

Further, connected to the interface 26 are a keyboard 17 for generating various commands in response to operations, and a drive circuit for a display 18.

In the tuner, as shown in Fig. 2, the antenna 3
The desired station is selected from the FM broadcast waves received by the front end 32 and converted to an intermediate frequency (■F).
The signal is supplied to an FM detector 34 via an IF amplifier 33.

The front end 32 converts the local oscillator signal to the mixer 32b into a PLL circuit using a PLL circuit 32a including a programmable frequency divider.
It is obtained by one type of LL synthesizer, and the channel selection operation is performed by controlling the frequency division ratio of the programmable frequency divider by the frequency control circuit 39. F
The detection output of the M detector 34 is supplied to an MPX (multiplex) demodulation circuit 35, where it is separated into L (left) and R (right) channel audio signals in the case of stereo broadcasting.
It becomes the playback audio output through the buffer amplifier 36,
The signal is supplied to the changeover switch 5.

Also, ■ a level detection circuit 37 that detects the received signal level (field strength) based on the IF signal level in the F amplifier 33; and ■ a so-called S
A station detection circuit 38 is provided, which outputs a station detection signal indicating that a broadcast wave has been received when the detection output of the curve characteristic is within a predetermined level range. The station detection signal output from the circuit 38 is supplied to a control circuit 39. The control circuit 39 includes, for example, a microcomputer.

In this configuration, programs and various data are written in the ROM 23 in advance. The data includes data indicating the relationship between the reception frequency of the tuner 1 and the clock pulse frequency of the clock pulse generator 12. That is, the reception frequency fI+ that causes beat disturbance due to the clock pulse frequency fa generated by the oscillator 13
f2...fn (n is an integer greater than 1) are written in advance. Note that the clock pulse frequency fa generated by the oscillator 13 is higher than the clock pulse frequency fb generated by the oscillator 14, and the reception frequency f1゜f2...
...When the clock pulse frequency fb from the oscillator 14 is used in fn, no beat disturbance occurs.

At predetermined intervals, the microprocessor 21 first determines whether or not the tuner 1 is in the tuning operation, as shown in FIG. 3 (step 51). If the channel selection operation is not in progress, a clock pulse generation command is generated (step 52). In response to this generation command, a low level signal is supplied from the interface 24 to the oscillation stop control terminal of the clock pulse generator 12, so that the clock pulse generator 12 generates clock pulses. Next, it is determined whether or not the function changeover switch 5 has just been switched to tuner selection (step 53). If it is not immediately after switching the changeover switch 5 to tuner selection, it is determined whether or not it is immediately after finishing the channel selection operation (step 54).

Immediately after switching the selector switch 5 to tuner selection, or immediately after finishing the channel selection operation, it is determined whether the current reception frequency fO belongs to any of fllf2...fo. (Step 55). If the reception frequency f does not belong to any of fl+f2...fn, a first frequency selection command is generated to select the clock pulse frequency fa (step 56). The changeover switch 15 electrically connects the oscillator 13 to the clock pulse generator 12 in response to a drive signal output from the interface 24 in response to the first frequency selection command.

Therefore, the frequency of the clock pulse of the clock pulse generator 12 becomes the frequency fa.

On the other hand, if the reception frequency fO belongs to one of fl+f2...fn, a second frequency selection command is generated to select the clock pulse frequency fb (step 5).
7). The changeover switch 15 is activated by a drive signal output from the interface 24 in response to this second frequency selection command.
electrically connects the oscillator 14 to the clock pulse generator 12. Therefore, the frequency of the clock pulse of the clock pulse generator 12 becomes the frequency fb.

If it is determined in step 51 that the channel selection operation is in progress, a clock pulse generation stop command is generated (step 58). Interface 2 responds to this generation stop command.
4 is supplied to the oscillation stop control terminal of the clock pulse generator 12, so that the clock pulse generator 12 stops generating clock pulses. Note that the microprocessor 21 sends a control signal to D in order to stop the calculation operation of the DSP 7 prior to generation of the pulse generation stop command.
A control signal is supplied to the SP7 to temporarily hold data during calculation, and a control signal is supplied to the DSP 7 in order to restart the calculation operation of the DSP 7 when a pulse generation command is issued.

In the tuner 1, for example, when starting a seek mode operation as a tuning operation, the control circuit 39 first sets the tuning operation determination flag F1 to 1 as shown in FIG. 4 (step 61), and the PLL circuit 32a. The frequency division ratio of the programmable frequency divider is changed by a predetermined value (step 62
), it is determined whether a predetermined time has elapsed since the frequency division ratio was changed (step 63). This predetermined time is slightly longer than the time from when the frequency division ratio is changed until the receiving frequency actually changes and stabilizes. If a predetermined period of time has elapsed, it is determined whether a station detection signal has been supplied from the station detection circuit 38 (step 64). By changing the frequency division ratio of the programmable frequency divider by a predetermined value, the receiving frequency increases by, for example, 100 Kllz, and at that time, the IF signal level, which is the received electric field strength, is equal to or higher than the predetermined level and the S curve in the FM detector 34 is increased. When the characteristic detection output is within a predetermined level range, a station detection signal indicating that a broadcast wave has been received is transmitted from the station detection circuit 38 to the control circuit 39.
is supplied to If this station detection signal is supplied, reset the channel selection operation determination flag F1 to 0 in step 6.
5), step 62 if no station detection signal is provided;
to move to. Note that the channel selection operation determination flag F1 is 0 and 1.
is supplied to the control circuit 3 as a signal indicating either one of the two.

Therefore, in step 51 described above, if the channel selection operation determination flag F1 is equal to 1, it is determined that the channel selection operation is in progress,
If the channel selection operation determination flag F1 is equal to O, it is determined that the channel selection operation is not in progress. Further, in step 54, the time immediately after the channel selection operation determination flag F1 changes from 1 to 0 is determined to be immediately after the end of the channel selection operation.

Further, when the microprocessor 21 operates in response to the operation on the keyboard 17 and switches the function selector switch 5 to select tuner 1, it sets the switching flag F2 to 1, and when the function is switched to another function, the switch is set to 1. The flag F2 is reset to 0, and in step 53, the time immediately after the switching flag F2 changes from O to 1 is regarded as the time immediately after the function changeover switch 5 is switched to select the tuner 1.

In the above-mentioned embodiment, a seek mode is shown as the channel selection operation, but the mode is not limited to this, and for example, a manual channel selection mode in which the reception frequency is changed by key operation, or a predetermined number of broadcast waves with a large electric field strength. It can also be applied to a BSM (Best Stations Memory) mode that detects and presets it in a preset memory.

Furthermore, in the case of a CD player 3, a DAT (digital audio tape recorder), or a satellite broadcast reception tuner that can directly generate digital audio signals, the output signal is supplied to the DSP 7 without going through the A/D converter 6. You can also.

Effects of the Invention As described above, in the sound reproduction device according to the present invention, the frequency of the clock pulse supplied to the digital signal processing means for processing the digital audio signal is changed according to the reception frequency of the tuner, so that the frequency of the clock pulse is changed according to the reception frequency of the tuner. Even when the frequency is high and its harmonic signals are included within the reception band, broadcast waves can be received satisfactorily without beat interference.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a diagram showing the configuration of a tuner in the device shown in FIG. 1, and FIG.
FIG. 4 is a flowchart showing the operation of the microprocessor in the device shown in the figure, and FIG. 4 is a flowchart showing the operation of the tuner control circuit. Explanation of symbols of main parts 1...Tuner 2...Tape deck 3...CD player 7...DSP 8...Microcomputer 12...Clock pulse generator

Claims (2)

[Claims] (1) a plurality of audio signal sources including a tuner; a first conversion means for converting an audio signal from any one of the plurality of audio signal sources into a digital signal; and a clock generation means for generating clock pulses; An acoustic device comprising: digital signal processing means for processing a digital signal from the first conversion means in accordance with a clock pulse; and second conversion means for converting the digital signal processed by the digital signal processing means into an analog signal. 1. A sound reproducing apparatus, wherein the clock generating means changes the frequency of the clock pulse according to the reception frequency of the tuner. (2) The sound reproducing device according to claim 1, wherein the clock generating means stops generating the clock pulse during a tuning operation of the tuner.