JPH02281167A - Automatic correcting circuit for vlsi tester - Google Patents

Abstract

PURPOSE: To eliminate the need for a manual adjustment delay device and a computer control time zone reflectance measuring method by obtaining modification factor with a calibration star connection circuit. CONSTITUTION: A pin electronic circuit to which a driver 46 and a receiver 48 are connected is, by closing a switch 66 in an automatic calibration mode, connected to a calibration star connection circuit. At that time, an incident wave 90, etc., are simultaneously generated at individual circuit of the driver 48, etc., and then through a calibration read 68, etc., made incident on a common node 74. There, one synthetic reflection wave 92 is formed, and returned to each circuit. A time delay between the reflection waves 92 such as the incident wave 90, etc., is measured, and compared to a pre-recorded delay information, and a modification factor about the incident wave of each pin electronic circuit is obtained. The incident wave modified with the factor reaches, in a test mode which closed a switch 62 through a test read 54, etc., each pin of a to-be-tested device 44 at the same time, so that waves of a system and a logic tester are modified and adjusted.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to logic testers, and more particularly to:
This invention relates to an automatic calibration circuit used for calibrating logic testers.

As the complexity of prior art VLSI has increased, so has the complexity of testing these devices in a manufacturing environment.

Testers have advanced to provide sub-nanosecond precision in generating and distributing high speed waveform edges to the tester bin board at 256'2, and the waveform edges all arrive at the bin at exactly the same time. However, there are still some inaccuracies due to multiple error sources inherent in the tester.

One of the more subtle specifications of the tester is the timing system. Some systems now offer a resolution of 60 ps, a maximum driver-to-driver and comparator-to-comparator skew of 1 and a maximum edge position error of 700 ps. Overall timing accuracy is ±1
．． It is within 5 ns. Actual testing, including these inherent errors, may result in even larger measurement errors. Especially when the number of bins increases to more than 256 bins, VL
SI tester design is made even more difficult by the need to maintain timing accuracy across all tester pins.

Through calibration, all voltage transitions that are timed to be delivered to the bins of the device under test (DUT), and all voltage transitions that occur whenever the expected data and the device data output are compared to a predetermined standard. You need to ensure that it is accurate. This degree of accuracy may determine the accuracy of the entire system. Signals traveling on the channel/L path to the DUT must pass through multiplexers, formatters, cables and drivers or detectors. Timing variations are inherent to these circuits and the associated cable lengths from channel to channel. These voltage transitions at the human pins and data detection at the output bins occur at different times even though we would expect them to match if programmed with similar delays. These timing changes are called "skew." Calibration is basically determining or measuring the skew in each system channel and compensating for this skew by variable delays in each system input and output channel. Hardware, software, or a combination of the two can be used to control the compensation delay.

Prior art techniques in hardware calibration involve manual delay adjustment or the use of pre-measured cables. When using pre-measured cables, measurements are taken for the first time and then the appropriate length of cable is placed in each channel path to equalize all delays. These manual methods are time consuming and do not account for errors due to environmental, electrical, and time-induced circuit drift while performing online testing.

The automatic calibration scheme is pre-configured to use a switch matrix that can be incorporated into the instrument interface port to connect each system human driver channel to a reference detector. The delay of each driver is adjusted to this reference detector. Each channel detector is then driven by an associated driver and calibrated to the system strobe. This method has two problems. First, the switch matrix must be manually replaced, and second, high quality 1-to-N matrices can become very large, since switching stubs that disrupt the characteristic impedance of the cable interconnection scheme are difficult to remove. , and is expensive due to its configuration.

Another prior art automatic calibration technique is the time-domain reflectometry method (
TDK). The TDR device is built into a logic tester. Such equipment is used by companies such as Teradyne, which offers automatic edge locking techniques that measure channel delay using TDII. This method offers the following drawbacks.

1) It is complicated and expensive. 2) Humpeter control TDR,
Requires. 3) Requires a 1-to-N switch matrix and bypass switch for each pin electronic driver.

A binary matrix driving 256 pins requires a relay tree 8 levels deep to separate the individual pin electronics paths.

It would be desirable to provide an automatic calibration system for a semiconductor device tester that obviates the need for expensive prior art techniques incorporating TDRs and associated switch matrices.

OBJECTS OF THE INVENTION It is an object of the present invention to provide an automatic calibration circuit for a logic tester that does not require a manually adjustable delay device or a computer controlled TDR.

Another object of the present invention is to provide an automatic calibration circuit for determined pin electronics delay errors and hardware delay errors associated with each pin or terminal of a device under test.

Another object of the invention is to provide a new calibration star connection circuit that simulates a central node or connection point for all pins or terminals of the device under test.

Another object of the invention is to provide a calibration circuit that forms a virtual node representing the center point of the device under test and that can automatically calibrate and compensate for delay errors between individual pin electronics. .

A general object of the present invention is to provide an automatic calibration system for logic testers that eliminates time skew between pins or terminals of a device under test.

Arrangements of the Invention In accordance with these and other objects of the present invention, an automatic calibration system for a logic tester includes pin electronics for each pin or terminal of the device to be tested. Individual pin electronics are connectable to individual pins or terminals of the device to be tested via a first predetermined time delay path when the tester is operated in a test moto. Additionally, the individual pin electronics can be connected to the new calibration star connection circuit via a second predetermined time delay path in auto-calibration mode. In the calibration mode, the incident waves are generated simultaneously by the respective individual pin electronics, and the incident waves form one composite reflected wave in the star-connected circuit, which is returned to the respective pin electronics. The time delay between the individual pin electronics incident waves and one combined reflected wave is:
The delay information is measured and then compared to prerecorded delay information for a second predetermined time delay path.

The deviation or change between the prerecorded second predetermined time delay and the difference between the incident wave and the resultant reflected wave represents a skew, change or drift of each individual pin electronics relative to each other. There is.

A second predetermined time delay is subtracted from the delay between the incident wave and the resultant reflected wave to provide a correction factor for the incident wave of the individual pin electronics. When a correction factor is added to the incident wave, the modified incident wave arrives simultaneously at each pin or terminal of the device under test, and all waves present in automatic calibration systems and logic testers are corrected and adjusted. .

Example Embodiments of the present invention will be described in detail below with reference to the drawings.

Referring to FIG. 1, a schematic block diagram of a prior art tester using a switch matrix for automatic calibration characteristics is shown. The system includes a mask driver 10 and a master detector 12, each connected to a
Human power is being applied to N matrix 14. matrix 14
has an input terminal leading to switch 20 via cable 18. Switch 20 is operable to select bypass path 22 or channel driver 25 .

The output terminals of both bypass path 22 and channel driver 25 are connected to a second switch 24 whose output terminal is connected to the input terminal of cable 26 . A cable 26 connects the output terminal of the switch 24 to the contact point 28. Contact point 28 is the point to be measured by the system of FIG.

The switch 24 is also connected to the input terminal of a high impedance buffer 30, and the output terminal of this buffer is
It is connected via cable 32 to a channel detector (not shown). A period generator 34 is provided to generate clock edges that are supplied to variable delay 36 and variable delay 38.

The output of the variable delay 36 is input to the mask driver IOK. The output of variable delay 38 is input to mask detector 12 . D/A converter 40 is operable to control variable delay 36 and D/A converter 42 is operable to control variable delay 38.

The system in Figure 1 is a time domain reflectometer (TDR).
The technique is shown and is used to measure the channel delay up to the open circuit contact point 28.

During calibration, waveform edges from mask driver 10 are sent to contact point 28 where they are reflected to mask detector 12. Switch 20 and switch 24 are both adapted to pass the signal to bypass path 22 . The 1/N matrix 14 connects the master drivers 10 to each test system channel Vc one at a time. Channel driver 25 is bypassed while measuring delay.

Referring to FIG. 2, there is shown a schematic block diagram of an automatic calibration circuit according to the present invention showing only the portion of the tester at device ffL (DUT) 44t that is tested by drivers and receivers 46-52. The tester circuit (not shown) is a conventional circuit. The circuit according to the invention is concerned with performing calibration between the respective pin electronics and DUT0.

DUT 44 (shown in dashed outline) provides the signal 2
A driver/receiver pair is shown in FIG. The first set of driver/receivers 46,48 and the second set of driver/receivers 50, 52 are conventional pin electronics driver/receivers. Driver 46 is connected to the input terminal of cable 54 via a series resistor 56 and a series switch 62. Driver 46 and series resistor 56 provide a termination impedance that matches the characteristic impedance of cable 54. Driver 50 is connected in series to a cable 580 input terminal via a resistor 60 and a series switch 64. The input terminal of receiver 48 is connected to switch 62 at a junction with resistor 56 or node 63, and similarly the input terminal of receiver 52 is connected to a junction between switch 64 and resistor 60 or node 65. has been done.

The output terminal of cable 54 is connected to a pin or terminal of DUT 44. The output terminal of the cable 58 is connected to the DUT.
44 separate pins or terminals. DUT44
The pins or terminals of are connected to the internal microcircuit to be tested. System timing is calibrated so that the pin electronics test waveforms arrive at the pins or terminals of DU'I' at the same time.

To perform this calibration, common node 74 will be described and used below. The O length connection point 63 of resistor 56, switch 62 and receiver 48 is connected to series switch 66. The other terminal of switch 66 is connected to cable 68. Resistor 60 , switch 64 and O-length connection point 65 of receiver 52 are connected to switch 70 . The other terminal of switch 70 is connected to cape/l/72. The other terminals of cables 68 and 72 are connected to a common node 74. cable or path 6
8 and 72 both have a characteristic impedance equal to the pin electronics and have predetermined length measurements and stored values. In an advantageous embodiment, the cables or paths are of equal length. Similarly, another tester driver/register is connected to cables 76, 78, 80, 182, 84 and 86.
switch 66 to connect to common node 74 as in
are connected via a switch similar to that and a cable similar to cable 68. An associated cable is provided for each test pin in the system, each cable having a known impedance equal to the source impedance including driver 46 and resistor 56.

During autocalibration, node 74 and associated cables 68, etc. are part of the autocalibration circuit. To maintain the device skew within specification while actually testing the device online, we tested the system to determine if there were any time delay changes in the system that caused time skew between the device pins. It is necessary to calibrate periodically. This time skew may occur as a result of temperature changes, aging, or other factors that may cause various delays between the DUT 44 and a timing generator (not shown) in the system. Time skew is DUT44
It is desirable to calibrate at the actual pin connections to the However, it is quite difficult to locate the calibration point on the probe tip, and therefore depending on whether the DUT is still a wafer-shaped chip or a packaged semiconductor device, the actual driver A short length of cable or wire path is placed between the electronic circuit and the actual probe point. This means that cable 5 in Figure 2
4 and 58.

In operation, the autocalibration operation is performed in two steps.

Time skew is calibrated on the input terminals of switches 62 and 64 and at their associated nodes 63.65, with autocalibration switches 66 and 70 closed and test switches 62 and 64 open. Thereby the common node 74 and associated cables 68-86
etc. can be connected to the individual pin electronics shown in FIG.

According to the method described below, an automatic calibration operation is performed,
And appropriate modifications are stored in the system to maintain the time skew at the output terminals of drivers 46 and 50 within predetermined specifications. But node 63.65 and DUT44
It is still necessary to take into account the delays between.

This can be done in two ways. First, although only two pins are shown in FIG. 2, a table can be constructed that takes into account the specific delays in each cable 54, 58, etc. associated with each pin in the test circuit. These delay or correction factors are then considered to determine the appropriate time skew. The actual delay can be measured by placing a calibration circuit or shunt common mate DUT at the location of DUT 44, such as associated with common node 74. Thereby, a calibration operation can be performed at a common node at a location of the DUT 44 that represents the actual center of the DUT 44 used with the test circuit. This means that the output terminals of the driver/receiver and
It takes into account various delays or errors associated with portions of the test circuit between the actual or physical center of the UT 44.

This actually provides a real node similar to virtual node 74. The error coefficients are then stored and D from the corrections to be made at the input terminals of switches 62 and 64.
It is used in determining the actual time skew at the actual input terminals of the UT44.

During automatic calibration, DUT and short test leads 54.58
etc. are removed from the system by opening switches 62, 64 and similar switches on all other test pins. Node 74 is connected to node 63.65 by switch 66.70 and cable 68.72 and similar switches and cables on all other test pins.
etc. are connected to. At this point all drivers within the test system are connected to a common node 74.

During calibration, the clock pulse edge is routed through driver 46 to receiver 48 by switch 66 and cable 68.
and is transmitted to the common node 74.

If only one driver in the system is turned on, common node 74 appears to the driver as a "short circuit." Therefore, after a period equal to two time delays, the resistor 56 at the input terminal of the receiver 48
A voltage drop occurs over the Each time delay is
This is the time required for the clock edge to propagate through cable 68. Preferably, this time delay is equal for all drivers in the system.

Until the first time a clock pulse edge reflected from common node 74 returns to the input terminal of receiver 48,
8 has a high level of manpower, and when they return, their manpower will be at a low level. This is only the case for systems where all other drivers 50 etc. are turned off. When calibrating the system according to the invention, all drivers 46.
50, etc. simultaneously generate pulses to provide an accumulated or composite waveform to a common node 74. This cumulative waveform is reflected and sent to all receivers 48 in the system at about the same time.
．． It will arrive at 52nd mag. Receiver 48 therefore receives the first clock edge that goes high, i.e. driver 46
and then measure the reflected clock edge of driver 46 plus the cumulative transmission from all remaining drivers in the system. As will be explained in more detail below, by comparing the received signal to the expected signal, errors can be calculated and adjustments made. This adjustment is made manually for each driver 46, 50, etc. in the system by varying the time programmed into the delay generator shown in FIG. If all drivers are calibrated, exactly the same graphics will appear on the receivers of all driver/receiver sets associated with all test points. The present invention provides the advantage that the system is relatively simple since only short paths or lengths of coaxial cable and one switch per test point are required. In addition, relatively simple computer algorithms are available for automatic calibration.

According to FIG. 3, the transmitter/receiver 4 of FIG.
One more detailed view of 6.48 is shown. Only transmission lines 68, 72, 80 and 84 connected to node 74 are shown. In operation, all terminals are connected to wire 72.6
It receives clock pulses 90.90B, etc., transmitted to 8 etc., and these clock pulses start from a common reference to. The output of transmitter 46 is designated Vx(t) at the input of resistor 56. The received signal, which receives composite reflected signal 92 from node 74 via line 68 at the output of resistor 56, is designated Vr(x). The clock edge transmitted in cable 68 is indicated by clock edge 90B with an arrow pointing toward node 74.

The reflected signal for a short is a falling clock edge that returns to the receiver (48) as voltage Vr(X). However, if an open path exists at node 74, all of the energy will be reflected to the input terminal of receiver 48. Driver 46 and resistor 56 have a combined impedance Ro that is essentially equal to the characteristic impedance of cable 68.

According to the invention, the incident signal and the reflected signal are analyzed. The incident signal represents the actual clock edge power of each cable associated with the terminal. However, the reflected signal is a combination of the energy transmitted from all remaining pins in the system and the energy reflected from this particular pin or terminal.

In the ideal case where all clock edges are applied to all terminals at the same point in time (i.e. the system is calibrated), the associated cables have the same length, so the clock edges are applied to node 74 at exactly the same point in time. arrive at. As a result, no current flows at node 74, thus providing an open circuit. All energy is at node 7
4 to the input terminals of the respective cables. The delay between the incident signal and the reflected signal is therefore equal to 2 TDL. But one signal or clock edge 90B1
90 is provided to node 63, 65, etc. at an earlier point in time than the clock edges of the remaining nodes in the system, then the clock edge transmitted to this particular node is
Node 7 sooner than any other clock edge in the system
Arrive at 4. This results in partial reflections from the low impedance seen at node 74, resulting in driver 46
A portion of the energy from passes through node 74 to reach other lines 72, 80 and 84 in the system. Power transmitted from drivers associated with other cables in the system also passes through node 74 to cable 68;
and includes a part of the signal Vr(x). This means that
This is caused by the lack of "total internal reflection" at node 74 for all lines involved.

Referring to FIG. 4, an incident waveform is shown that represents the signal level Vr(x) at receiver 48 for total reflection from node 74. Each mark on the X-axis of the coordinate system represents one time delay (TDL). line 68
The incident waveform at -86 is represented by a pulse edge 94, which, for reference, has an amplitude of 1. has an amplitude of 0.5 after a period of .The pulse edge is
(2) Measured at 0.25 of the amplitude of x(t). For a fully aligned system, there is a virtual open circuit at node 74, thus resulting in a reflected wave shown by pulse edge 96. For a virtual open circuit condition, the reflected pulse edge requires one delay time to return,
This results in a total delay of 2 TDL between the initial clock edge 94 and the reflected pulse edge. As a result of the reflected edge, the level of Vr(X) increases to the level of V,(t). Pulse value 96 was measured at a level of 0.75 of the total level, which represents 50% of the reflected wave.

For a virtual short at node 74, the reflected pulse edge 92 reflected from node 74 results in a pulse edge 98 (shown in dashed line) that drops to a low voltage level. Here, the incident waveform 94025% at point 93
25 of the short circuit reflected waveform 98 at point 95.
Delta (delay) by measuring the time of % crossing
Note that is 2 TDL and can be used as a measurement of the length of the reference cable 68. Similarly, cable 7
2 and all other cables or lines can be determined. Short circuit waveform 98 is the voltage Vr(x) that occurs when node 74 appears as a short circuit. A short circuit occurs when the incident wave 94 arrives at node 74 before all other pulse edges 94.

According to FIG. 5, three incident waveforms are shown representing the voltages as they appear at the nodes of different receivers A, B and C, and these waveforms have a time skew of Ins. The pulse edge power of receiver A is lns earlier than the pulse edge power of receiver B and 2 ns earlier than the pulse edge power of receiver C.

All three waveforms are superimposed on the same coordinate axes for illustration. In addition, a waveform is shown, which represents the ideal case where there is no skew between the edges of the incident pulse.

The waveform at receiver A consists of two parts, a first part AJ representing the incident pulse edge and a second part "8'" representing the reflected pulse signal. Similarly, the waveform of receiver B has a first part molecule Bl and a second part 1
B'.

The waveform at receiver C is represented by a first portion "C" and a second portion "C'." The ideal waveform condition is
It is represented by an incident wave part DJ and a reflected wave part "D'". As mentioned above, portions D and D' represent the ideal case that would occur for all receivers when the system is calibrated.

According to FIG. 5 and waveforms A and A' for receiver A,
The incident waveform A rises at a value of 50% of the total value, and I
It can be seen that 25% crossing occurs in ns. The one-way delay through the line to node 74 is shown equal to 1.5 ns. The total round trip delay for the incident and reflected signals is therefore 3 ns. In the ideal case, 25% and 7
The 5% intersection should be 30S apart. However, A.
This is not the case because of the time skew of the incident pulse edges to the B and C receivers. In the illustrated example, it can be seen that the value of the reflected portion A' initially decreases because the incident pulse edge from the A receiver arrives at node 74 earlier than the incident pulse edges from the B and C drivers.

This results in a low impedance at node 74 that is reflected back to the A receiver. Dashed line 100 indicates that all other drivers in the system are off or low and A
Only the driver at the receiver node is on. It can be seen that the level of the reflected voltage at the A receiver decreases until incident energy is received from the other driver. When this happens, the voltage increases by its full value. The 75% crossing point is indicated by point 102 on the A' curve. This means that the curve 2
Almost 5.5ns, which is a 4.5ns delay from the 5% intersection
occurs at , and is 1.5 ns longer than the calibrated ideal condition shown by the D' waveform.

The incident clock edge B has a 25% crossing at 2 ns and a 75% crossing at point 104 at approximately 5 ns in the B' waveform. 25% and 75%
An adjustment is necessary for the incoming clock edge since the delay between the crossing points of is equal to 3 ns. However, note that the portion of the B' waveform before the 75% crossing is slightly higher than the ideal condition exhibited by the D' waveform. This means that
This is because the energy of the human waveform and the A waveform before the B waveform travels through the cable, and the transmitted energy is reflected and received earlier by the receiver on the B pin electronics. This increases the voltage level before the 75% crossing. Similarly, due to the late arrival of the C waveform transmission energy, 7
The portion of the B' waveform immediately after the 5% crossing decreases in value.

The incoming clock edge at the C receiver lags the clock edge B by ins, and the 25% crossing occurs at 3 ns. The reflected waveform C' at the C terminal rises immediately due to the incident energy received from both the A and B drivers. As a result, the 75% crossing occurs at point 1 (16), which occurs at approximately 4.5 ns, 1.5 ns behind the 25% crossing of the input clock edge C.
Adjustments must be made accordingly.

It is important to note that the 25% crossing to the input clock edge is only Ins ahead of the 25% crossing of the ideal input clock edge D. However, the delay between the 25% crossing to the incident clock edge and the 75% crossing of the reflected waveform A' is 4.5 ns, resulting in an error of 1.5 ns. The actual error is I ns, ie the error is "amplified". Error amplification may increase by a factor of 21 as the skew between incoming clock edges is reduced by a value less than the driver rise time.

The method of correcting the skew is that the predetermined pin electronics 136
The purpose is to divide the error delay between the 25% crossing and the 75% crossing of the waveform by 2 and make appropriate corrections. The human waveform is therefore delayed by 0.75 ns after the measurement. The B waveform is then measured and no delay is required. The C waveform is then measured, resulting in a delay of 1.5 ns. Thereby, it is necessary to advance the time of the C waveform by 0.75 ns.

Then again the three bin electronic delays are measured and the same method is continued, with the delays being measured and three
compared to the expected delay of ns. If all pin electronics 136 are operated repeatedly, the waveform will be represented by the incident portion and the reflected portion D'. All pin electronics receive this waveform.

In practice, it is observed that a sinusoidal change occurs in the incident and reflected waveforms. These sinusoidal changes typically occur when the deviation between the waveforms exceeds the rise time of the waveforms or the length of the reference cable. In this situation, multiple 25% crossovers and multiple 75% crossovers may occur. It turns out that there is actually no difference in which intersections are measured to determine which error corrections should be made. However, to avoid contradiction, the first
Alternatively, it may be advantageous to use only the second intersection for each measurement. If each operation is repeated, multiple crossings will disappear and the waveform will approach the calibrated waveform DSD' (.

6a-6d, the sequence of repeating curves for terminals A, B and C shown earlier in FIG. 5 is shown. However, for these curves the length of the reference delay cable is significantly reduced, such as when using cables 54, 58 and shorted DUTs to represent the calibration nodes. In FIG. 6a, the incident clock edge of the A receiver has a 25% intersection at point 108 and a 25% intersection at point 110.
5% crossing and another 25% crossing at point 111. B
The incident clock edge at the receiver is 2 at point 112.
The incoming clock edge C, which has a 5% crossing and at the C terminal, has a 25% crossing at point 114.

The reflected portion A' at the A receiver is 75% at point 116.
Has an intersection. The reflection part B' in the B receiver is:
There are three 75% intersections at points 118, 120 and 122. The reflected portion C' at the C receiver is the point 124 K
It has only one 75% intersection. Therefore for an incident clock edge A at the A receiver, point 108.
A choice needs to be made between 110 and 111, and for the reflective portion B' a choice needs to be made between 75% intersection 118, 120 and 1220. An advantageous method of selecting an intersection as described above consists in selecting the first intersection using a linear search algorithm. Therefore, a point 108 on the incident clock edge A and a point 118 on the reflective portion B' are selected as appropriate intersection points. However, the actual algorithm used in tracing Figures 6a-6d is a conventional binary search algorithm that determines which 25% and 75% crossings are within a particular waveform of a receiver. , and this is an advantageous embodiment of the system.

The X-axis of Figures 6a-6d represents the normalized delay between the 75% and 25% crossings. Point 108 has a normalized delay of approximately 2.5 compared to point 116 on the A and A' portions, for example, resulting in an error of 1.5. Therefore, the KA part needs to be adjusted by delaying it by 0.75 times the normalized delay. Similarly, the waveform at the B receiver is 25 at points 112 and 118.
It has a delta (delay) of 0.4 between the % and 75% intersection, resulting in an error of -0.6, and therefore requires an advance of approximately 0.3 times the normalized delay. be. The waveform at the C terminal has a delay of approximately 0.3 between points 114 and 124, thus resulting in an error of →7 times the normalized delay. This requires an adjustment of 0.35 times the normalized delay so that the incoming clock edge C is advanced in time.

According to Figures 6a-6d, it is clear that the repetition is performed in succession, resulting in a reduction in the time skew between the clock edges in the AlB and C receivers. This is shown in Figure 6d, where A, B
and C waveforms all have approximately the same 25% intersection at point 126, and all A', B', and C' waveforms have a 70% intersection at point 128.
Generates a 5% crossover.

Referring to FIG. 7, a schematic block diagram of a portion of an automatic test equipment system that automatically performs skew error correction is shown. The system of FIG. 1 performs a multiplexing function, in which a mask driver and a master clock are provided to drive each pin individually. In the system according to the invention, a tester master oscillator is provided,
It is controlled to drive the pin electronics 136 associated with each node 63, bin or terminal. Each pin electronics includes a local driver 46' and a receiver 48' driven by local pin electronics 136.
has.

According to FIG. 7, C P controlling the automatic calibration system
U 130 is provided. CPU 130 is a conventional type of microprocessor based control unit with associated memory. The CPU controls the master oscillator 132 and outputs a timing reference signal t on line 133.
. supply. The mask oscillator generates a clock reference signal t in response to a control signal received from the CPU 130.
. supply. Master oscillator 132 is connected to a pattern generator 134 that provides address patterns of 1's and 0's for certain tests within the system. single CP
U 130 , pattern generator 134 and master oscillator 132 are connected to respective pin electronics 1 in an auto-calibration circuit.
36.

The pin electronics as shown in the dashed outline box 136 is
One is provided for each pin or terminal of the UT44. Each pin electronics has a driver 46' and a receiver 48' similar to drivers and receivers 46 and 48 of FIG. The driver 46' includes a series resistor 5
6' to a cable 54' similar to cable 54 and to a test terminal or bin or cable 68.72 of the DUT shown in FIG. 1
If the switch 66.70 of the set is closed, the receiver 4
The driver 46 input terminal of 8' is connected to a node point 63' between resistor 56' and cable 68.72.

Driver 46' receives output from formatter 146. Format former 146 receives the binary pattern from pattern generator 134 and
Receive the clock from 8 and convert this pattern to j□+△
It can operate to convert the waveform into a waveform and supply it to the driver 46'. Formatter 146 receives and stores the pattern on a cycle-by-cycle basis and provides appropriate drive signals to driver 46'. Driver clock generator 148
provides timing to the formatter 146;
and is connected to master oscillator 132 via line 133. Driver clock generator 148 is operable to generate leading and trailing edges of the incident waveform to provide a programmable delay. Programmable delay information is stored in delay generator 148 and reference t of master oscillator 132 forms various incident waveform edges.
Determine the delay from The initial delay, which is predetermined and memorized, is stored in the CPU 13 during system initialization.
Calculated by 0.

The output terminal of receiver 48' is connected to a digital comparator 150 which also receives power from a receiver clock generator 152. Receiver clock generator 152 operates similarly to driver clock generator 148, has a programmable delay, and has a clock t on line 133 from mask oscillator 132. A strobe pulse is generated with reference to a reference signal. Digital comparator 150 uses the strobe output of receiver clock generator 152 as a time reference for comparison with the output of driver 48'. The output of this comparator 150 on line 151 is a high level/low level type output, and the digital comparator 150 is configured to examine appropriate points in the incident and reflected pulse waveforms. In an advantageous embodiment, clock generators 148 and 152
is a particularly high precision linear digital delay generator that achieves an accuracy of approximately 50 ps.

CPU (is an address bus 154 and a data bus 15
6 to interface with the main part of the related circuit shown in FIG. address bus 154 and data bus 15
6 interfaces with pin electronics 136, mask oscillator 132 and pattern generator 134. C.P.
U 130 interfaces with and controls all electronic circuitry within the autocalibration circuit. In addition, the pattern generator interfaces with pin electronics 136 via bus 158, thereby transferring the pattern stored in pattern generator 134 to electronic circuitry within pin electronics 136 every j□. I can do it. Essentially, this information is combined with pre-stored information in the registers of clock generators 148 and 152 and formant former 146 to provide cycle-by-cycle output to all driver/receivers as shown at 46'748'. method to provide the appropriate delayed incident waveform or expected receiver waveform.

In operation, the system is initialized for operation by loading all appropriate internal registers within pin electronics 136. Then simply run the system and determine what the output of digital comparator 150 is for a particular pin. CP 0130 interfaces with digital comparator 150 and determines whether a high/low signal level condition exists. All pin electronics 136 operate simultaneously with the signal and provide delayed clock pulse edges to the test circuitry, including node 74. A new error count (Δk) is calculated by the digital electronics associated with each test pin electronics 136 to determine the adjustment to be made. The adjustment is made and the new delay is stored in driver clock generator 148 and includes one iteration. Another such measurement is taken to determine whether the system is within the specified skew characteristics, and if not, another iteration is performed. This continues at 1, where each pin electronics falls within the skew specifications. Once this is achieved,
Information can be stored by the CP 0130 and associated memory or DUTIC used in performing the test.

According to FIG. 8, a flowchart related to the calibration operation information is shown. The flowchart starts with the start block 154.
and proceeds to operation 156 to configure the system so that all parameters of the system, such as initial delay, are placed in the various pin electronics as previously described with reference to FIG. loaded. A clock edge is then initiated, as indicated by action block 158, and the value of N is set equal to one, as indicated by block 160. The value of N represents a particular terminal within the system. Then the program is block 16
Proceed to step 2 and measure the 25% and 75% intersection. A "delta" or delay difference value between the 25% and 75% crossings is then calculated, as indicated by action block 164, and decision blocks 166 and 168 determine whether this delta is less than the corresponding reference delta. A determination is made as to whether , or greater. The reference delta is essentially equal to the time required for an edge to travel through the cables 62-68 in the calibration system to the common node 74 and back to the associated receiver 48 or 48'.

The program first proceeds to decision block 166 to determine whether the delta is equal to the reference delta.

If they are equal, the program proceeds along the rYJ path, and if not, the program proceeds along the rNJ path and reaches decision block 168.

This decision block determines whether the delta is less than the reference delta. If it is smaller, the program rY
Continuing along the J path to action block 170, the delay of driver 46' is reduced by half the value of the difference between the measured delta and the reference delta. If the measured delta is greater than the reference delta, the program proceeds along the rNJ path to action block 172 and the delay at this particular pin is
Increased by half the difference delta. The program is
From action blocks 170 and 172 to decision block 174
Proceed to and determine whether the value N is equal to the maximum value NMAX. If not, the program advances along the N path to action block 176 K, increments the value of N by 1, and then returns to the input of action block 162;
Measure and modify another pin in the system. After correcting all errors, the programmer determines decision block 1
Proceed to 78 to determine if all pins are approximately equal to the reference delta.

If they are not equal, the program executes action block 15
6, reconfigure the system with the new delay, and repeat. If all pins are equal to the reference delta, the program proceeds along the "Y" path to action block 179. Basically, decision block 178 determines that all terminals are within certain constraints with respect to system skew.

At action block 179, the correction factors previously stored in the error table are examined to determine if the calibration error has changed. Then the calibration error is determined by the bin electronics 13
Used to calibrate 6. The time skew calculated with respect to the signal thereby fed to the autocalibration circuit is
The signal provided to the DUT can be varied and calibrated. Therefore, the error coefficient determined using the calibration circuit is
Used to replace previously stored error coefficients and correct for pin electronics skew errors. The previously measured delays from nodes 63 and 65 to their associated pins or terminals 1 are not affected by the error factor. Then Progera, Mu returns to block 180
Proceed to.

In summary, a calibration circuit is provided using multiple cables of known length, one cable associated with each pin electronic circuit in the test system. One end of the cable is connected to a node in the driver/receiver and the other end is connected to a common node 74.

The entire pin electronics are operated with delayed pulse edges to provide a delayed incident waveform. The incident pulse edge and the reflected pulse edge from node 74 are measured at the input terminal of the receiver. By measuring the time difference between the incident and reflected waves, a determination can be made as to whether all transmitted waves arrived at the common node 74 at the same time. The ideal situation is when the one-cycle delay is equal to twice the cable length delay between receiver node 63 and common node 74. Since the previous cable delay is a known value, each pin can be automatically measured in turn and the pulse edge can be adjusted by an amount Δ determined by taking the difference between the measured and expected delays. Each pin is measured in turn and the delay is adjusted for one iteration. The process is then repeated until the delay between the incident and reflected pulse edges at each pin electronics is equal to the expected delay.

Having explained how the calculation of the error correction value in Δ is carried out by measuring the time difference between the incident wave and the resultant reflected wave at the input terminal of the pin electronics, the ideal approach shown in Figure 5. It is clear that the waveforms are delayed by programmed human effort. The program includes time for starting and simultaneously receiving the driver signal at the associated receiver. The difference between the programmed arrival time of the D waveform and the detected arrival time of the driver output when detected is a measure of receiver error that is stored as a receiver error coefficient and used to correct for receiver time skew error.

During testing, removing skew in the receiver is as important as removing skew in the bottle of the device under test. The overall accuracy of the test is proportional to the sum of both types of skew. Calibration of the pin electronics driver is independent of receiver errors. Only after driver calibration can precise detection and correction of receiver errors be performed.

[Brief explanation of drawings]

Fig. 1 is a schematic block diagram of a conventional tester using a switch/IJ box, Fig. 2 is a schematic block diagram of an automatic calibration circuit according to the present invention, and Fig. 3 is a diagram of the driver/receiver shown in Fig. 2. FIG. 4 is a diagram of the incident waveform showing the signal level at the receiver node with respect to the total internal reflection waveform from the calibration circuit node; FIG.
Figures 6a, 6b, 6c and 6d are diagrams of the three incident waveforms seen from the input end of the node of three different pin electronic circuits with a time skew of ns, the waveforms of Figure 5. FIG. 7 is a diagram showing the CPU in the tester that controls the system according to the present invention, and FIG. 8 is a diagram showing a flowchart regarding the calibration operation. 44... Device to be tested, 46... Driver,
48...Receiver, 54.58...Test lead,
63.65... Test node, 66.70... Switch means, 68.72... Calibration lead, 74... Common node, 9°... Incident waveform, 92... Reflected waveform,
130...CI? U. 136...Pin electronic circuit, 146...Format generator, 148...Clock generator, 150...Comparator agent Patent attorney 1) Osamu Netsu

Claims (20)

[Claims] (1) In an automatic calibration circuit that calibrates and corrects time skew occurring at multiple pins or terminals of a device under test, a common calibration node (74 or 44) is provided, and multiple individual test nodes (63) are provided. , 65), one in each case associated with a respective pin or terminal of the device to be tested (44), delay means (pin electronics 136) connected to said test nodes (63, 65); and configuration leads 68, 72 or test leads 54, 58), the delay means comprising leads having a predetermined, known and stored amount of time delay, one in each case for each test. A plurality of pin electronics (136) for the nodes are provided, each pin electronics (136) having a driver (46) and a receiver (48) connected to one of said test nodes (63, 65). coupled to said driver means and said receiver means, and said test node (
63, 65) and the reflected pulse waveform (92) received at the same test node in the receiver from the common node (74 or 44).
) means (130, 146-15) for calculating the delay between
2) are provided, and means (130, 150) are provided for comparing the measured delay with an expected predetermined known delay, the means providing an error factor time delay (2T_D_L and Δk). death,
and coupled to each of said pin electronics (136) and determining in turn an error coefficient (Δk) associated with each pin electronics (136);
46) that computer control means (130) are provided for automatically adjusting the time of test signal generation at each and eliminating time skew occurring at each of said pins or terminals of the device (44) under test; Features an automatic calibration circuit. (2) the error coefficient (Δk) is calculated from the measured delay, and this delay is calculated from the individual pin electronics (13
6), and including delays for individual leads (68, 72) of known length and known delay connected between said test nodes (63, 65) and said common node (74). Automatic calibration circuit described in item 1. (3) the predetermined known and stored delay includes a fixed delay for each lead of known length connected between the test nodes (63, 65) and the common node (74); Said means (130, 150) for comparing the measured delays subtract a fixed delay from the measured delay to obtain said error coefficient (
3. The automatic calibration circuit of claim 2, further comprising means for providing Δk). (4) each lead connected between the test node and the common node includes a calibration circuit lead;
4. The automatic calibration circuit of claim 3, and wherein each calibration circuit lead connected between a test node and the common node has a unique predetermined length and a known delay subtracted from the measured delay. (5) Test leads (with a predetermined, known and stored amount of fixed time delay for each pin or terminal)
54, 58) are provided, and this test lead is
During test mode operation, the test nodes (63, 65
) and a pin or terminal of said device to be tested (44) and is disconnected from said test node (63, 65) during calibration mode operation and compares the measured delays. Automatic calibration circuit according to claim 4, characterized in that said means (130, 150) comprise means for adding a fixed delay of said test lead to said measured delay to calculate an error coefficient (Δk). (6) Each of said pin electronic circuits has switch means (66
, 70, etc.), these switch means connect each of said test nodes to a respective calibration circuit lead in said calibration mode, and said
, 65). The automatic calibration circuit according to claim 5, wherein the test lead is disconnected from the test lead. (7) Each of the pin electronic circuits has switch means (66
, 70 etc.), these switch means disconnecting each of said test nodes (63, 65) from respective calibration circuit leads (68, 72) in said test mode and Automatic calibration circuit according to claim 5, characterized in that the test nodes (63, 65) are connected to the same test node (63, 65). (8) The delay means has a plurality of individual test leads having predetermined known and stored values, each test lead being one of the test nodes (63, 65).
2. The automatic calibration circuit of claim 1, wherein the automatic calibration circuit is connected between the common calibration node (74) and the common calibration node (74). (9) said common calibration node (74) includes a plurality of pins or terminals of the device under test (44), which pins or terminals are connected together and the device under test (44);
9. An automatic calibration circuit according to claim 8, forming an actual common calibration node (74) representing the center of the calibration node (44). 10. The automatic calibration circuit of claim 8, wherein the common calibration node (74) includes a device carrier having shunts connecting pins of the device carrier together. (11) The delay means includes test leads (54, 58), and these test leads, during test mode operation,
Calibration circuit leads (68, 72) connected to the test nodes (63, 65) and disconnected from the test nodes (63, 65) during calibration mode operation are connected to the test nodes (63, 65) during calibration mode operation. The automatic calibration circuit of claim 1, connected between a node and the common node (74). (12) Comparing means (130, 150) compare the difference between the programmed arrival time of the incident pulse waveform from the driver to the associated receiver and the detected actual arrival time of said incident pulse waveform to determine the receiver skew; The automatic calibration circuit of claim 1, including means for calculating an error value. 13. The automatic calibration circuit of claim 12, wherein the receiver skew error is calculated after correcting for time skew occurring at a pin or terminal of a device under test. (14) The automatic calibration circuit according to claim 12, further comprising means for storing the receiver skew error value. (15) The incident pulse waveforms generated by respective drivers in their respective pin electronics (136) simultaneously provide a composite reflected pulse waveform to said common node (74), which composite reflected pulse waveform is connected to all Caused by the simultaneous arrival of the incident waves, no current flows through the common node, forming a virtual open circuit condition at the common node,
The automatic calibration circuit according to claim 1. (16) supplying a test signal from the pin electronics to a terminal or pin of the device under test (DUT) via a lead of a predetermined length and delay, said pin electronics (136) generating a test pulse; and a receiving driver (46)
and a receiver (48), in which a separate pin electronic circuit (136) is provided for each pin or terminal of the DUT (44) to be tested. and said pin electronic circuit (136) has a driver (46) whose output terminals are connected to test nodes (63, 65).
) and this test node is connected to the receiver (4
8), wherein an automatic calibration circuit has a plurality of circuit leads (68, 72, etc.) of a predetermined length and delay, and said calibration circuit is connected to one of said circuit leads. a common shunt node (74) connection to an end, each of said plurality of circuit leads (68, 72, etc.) connecting to said individual test node (63, etc.) at the other end of said circuit lead; timing signal means (148, 146) connected to the driver in the pin electronics;
and computer control means (130) connected to each of said pin electronics (136) and to said timing signal means (148, 146), said computer control means being connected to said test node. simultaneously initialize the incident pulses (such as 90) at and as a result the total energy reflected pulses (92 etc.) from said common shunt node (74).
) and returned to said individual test nodes (such as 63) and said receiver (48) within said pin electronics (136).
is the incident pulse (90 etc.) and the reflected pulse (90 etc.)
2), said pin electronics (136) and said computer control means (130) calculating a time delay between said incident pulse (90) and said reflected pulse (92); and an automatic skew calibration circuit programmed to calculate a skew error adjustment Δk to be added to a timing signal provided to the driver in the pin electronics. (17) the circuit leads (68, 72, etc.) include test circuit leads (54, 58), and the common shunt node (74) includes a device under test (
A device (44) interconnecting all pins or terminals of (44)
17. The automatic skew calibration circuit according to claim 16, comprising: 4). (18) said device interconnecting all pins or terminals of the device (44) comprises a semiconductor device carrier having a shunt connecting the pins centrally and together forming a central common node (74); The automatic skew calibration circuit according to claim 17. (19) The circuit leads (68, 72, etc.) are the calibration circuit leads (68, 72) and the test leads (54, 58).
and during calibration operations, individual calibration circuit leads (68, 65) between the individual test nodes (63, 65) and the common node (74).
17. Automatic skew calibration circuit according to claim 16, further comprising switch means (62, 66) for connecting said test leads (54, 58) to said test nodes (63, 65). (20) All the above calibration circuit leads (68, 72, etc.)
The common node (74) connecting one end of the
17. The automatic skew calibration circuit of claim 16, wherein the circuit forms a virtual electrical aperture path and a virtual node (74) for the device under test (44).