JPH02280379A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To establish a memory such as a static random access memory (SRAM) by employing a fine MISFET without lowering power supply voltage. CONSTITUTION:A low concentration impurity region 4 is provided in a drain side high concentration impurity layer 3 of a single drain structure MISFET, and an aluminum wiring 6 and a gate electrode film 5. The structure is formed using a mask by ion implantation of an opposite conductivity impurity to those of a source and a drain, without using a particularly complicated process. Additionally, when a MIS FET is applied to light doped drain LDD, a low concentration impurity region 7 is formed only on the drain side likewise the single drain structure or the low concentration impurity region 7 is formed on both sides of the source and the drain. Further, voltage between the source and the drain is also dropped to achieve further high reliability.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a semiconductor device and a method for manufacturing the same, and in particular an insulated gate type (hereinafter abbreviated as MIS type) suitable for achieving high reliability.
The present invention relates to a semiconductor device having an Ii field effect transistor and a method for manufacturing the same.

[Conventional technology]

Conventionally, as a structure for achieving high reliability of MIS type field effect transistors, as described in Japanese Patent Laid-Open No. 54-44482, the source and drain are formed with a low concentration impurity region and a gate with high concentration. A low-concentration drain made of impurities, a so-called LDD (Lightly Doped Drain) structure, was formed in a self-aligned manner using an extremely small amount of sidewall spacer remaining on the gate sidewall during anisotropic etching of the insulating film. .

[Problems to be Solved by the Invention] In the above conventional technology, in order to achieve even higher reliability, it is necessary to increase the length of the sidewall spacer in order to increase the length of the low concentration impurity region. be. However, when the line width and line spacing of wiring are reduced due to higher integration of devices, forming long sidewall spacers between fine gate TL poles will conversely lead to an increase in memory cell area. . Particularly in memories such as static random access memories (SRAMs), the increase in chip area has become a big problem, and there has been no choice but to lower the power supply voltage. An object of the present invention is to provide a highly reliable MIS type field effect transistor or a semiconductor including the same which can be formed by an easy and controllable process with little increase in device area! An object of the present invention is to provide a device and a method for manufacturing the same. [Means for Solving the Problems 1] In order to achieve the above object, in the present invention, a high resistance region is added in series on the outside of at least one of the source and drain of the MIS field effect transistor, or is connected to the source and drain. A part of the wiring connected to the MIS type field effect transistor is made to have a high resistance, or at least one of the source and drain of the MIS field effect transistor itself is made to have a high resistance. (Function) Due to the high resistance regions added to the source and drain, M
It is possible to divide the voltage applied from the outside to the source and drain of the IS field effect transistor. As a result, the reliability of the device can be improved. This is the second
This will be explained using figures. As shown in Figure 2(a), the n-channel M has a normal LDD structure.
FIG. 2B shows the relationship between the breakdown voltage between the source and the drain and the resistance R when a resistance R4 is added outside the drain of an IS type field effect transistor. This is a typical device with a channel length of 0.5 μm.
This is an example of an element shown in FIG. It can be seen that as R increases, the withstand voltage greatly improves. At this time, not only the breakdown voltage shown in the figure is reduced, but also the hot carrier effect is reduced and long-term operation reliability is improved. [Example 1 <Example 1>> A first example of the present invention will be described below using FIGS. 1 and 2. The structure shown in FIG. 1(, ) is one in which a low concentration impurity region 4 is provided in a high concentration impurity layer 3 on the drain side of a MIS field effect transistor having a single drain structure. In the figure, 1 is a silicon substrate, 2 is a gate electrode, 5 is an interlayer insulation film, and 6 is an aluminum wiring. Also, the same figure (
b) shows the equivalent circuit of this structure. With this method of adding a resistor in series, by making the resistance value sufficiently large, a single drain structure can be used as is as an MIS field effect transistor. Further, this structure can be formed by ion implanting impurities of a conductivity type opposite to that of the source and drain using a mask, and no particularly complicated process is required. Further, the structure shown in FIG. 2 is an embodiment applied to an LDD N1 structure as a MIS type field effect transistor. 7 in the figure is a low concentration impurity region. In the figure (a), a resistor is formed only in the drain, and in the figure (Q), a resistor is formed in both the source and drain. The effect when it is formed only on the drain side is the same as the case shown in Figure 1, but when it is added on the source side, it is possible to reduce the voltage not only between the source and the drain, but also between the source and the gate, making it even more effective. It is possible to achieve an even higher frequency of aa. If the resistance value in this embodiment is, for example, 100 to 200 Ω for the n-channel and 200 to 400 Ω for the n-channel, the 5Vil source can be used even in an element with a channel length of 0.5 μm. <Example 2> Next, a second example will be described using FIG. 3.4. In the first embodiment, the additional resistor is formed in a part of the high concentration impurity region, but this method increases the number of masks by one. However, if a high resistance WJ9 is formed at the connection between the high concentration impurity layer 3 and the wiring 6 as shown in FIG. 3(a), the resistance can be added by self-alignment without increasing the mask. However, in this case, the withstand voltage changes depending on how the contact hole for connection with the wiring is formed, so the burden on the designer increases to some extent. However, when two or more MIS field effect transistors are arranged in series, contact holes are usually not formed between each transistor.
It is often used in AND, NOR gates, etc. In this case, the above-mentioned additional resistor is only applied to either the source or drain of each transistor, but if there are two or more transistors in series, it is necessary to add a resistor to each transistor in order to divide the voltage by the transistor itself. There isn't. Conversely, if the resistor addition method is used, no extra resistance is added to the connection portion of the series transistors, resulting in high-speed operation. This will be explained using the circuit diagrams of the CMO8 inverter and NAND gate shown in FIGS. r in the diagram
is the additional resistance. In the case of a simple inverter as shown in FIG. 4(c), a resistor r is attached to both the source and drain sides of each transistor, but no resistance is attached to node A in FIG. 2(d). This makes it possible to increase the speed. Note that it can be formed by embedding a high film or the like shown in FIG. Any film with high resistance may be used. Furthermore, if the contact hole is completely filled with a high resistance layer or a multilayer film of a high resistance layer and a low resistance layer, the alignment margin between the wiring layer and the contact hole can be reduced. In addition, as a good example of this method, it can also be formed by burying a polycrystalline silicon film with a high impurity concentration in the contact hole, and then ion-implanting oxygen to a depth of, for example, 10 cm to 10 cm + 28 degrees. nrP
Both channels can be formed at the same time, eliminating the need for a mask. Also, the above embedded layer and arrangement wAy! The contact resistance with J can be reduced by forming a high resistance layer in the middle of the buried layer, and the total resistance can be easily controlled. Another embodiment of the method for increasing the resistance of the contact portion will be described with reference to FIG. First, in FIG. 3(a), the wiring layer itself is made into a multilayer film, and a high resistance film 10 is formed in at least one of the layers, and 411! It can be formed using a process that is easier than manufacturing. It is also possible to use a method that reduces 3 in the figure is a high concentration impurity region,
5 is an insulating film between the eyebrows, and 6 is an aluminum wiring. In this case, a polycrystalline silicon film was used as the high resistance film 10. Further, (b) to (e) in FIG. 4 are examples in which the contact resistance between the wiring and the high concentration impurity layer is increased. Usually, a Schottky junction is formed at the contact between the total bending element and the semiconductor, but if the impurity concentration of the semiconductor is sufficiently high, the junction becomes a tunneling property and becomes an ohmic junction. For this reason,
Conversely, by lowering the impurity concentration on the semiconductor side surface, a Schottky junction with high contact resistance can be formed. In FIG. 3B, after a contact hole is opened, impurities of a conductivity type opposite to that of the high concentration layer 3 are ion-implanted, and can be easily formed. Figure (c) shows that in Figure (b), impurity ions of the same conductivity type as the high concentration layer 3 are implanted deep into the substrate at slightly higher energy to prevent short circuit between the wiring layer and the silicon substrate after forming the contact hole. This is what I did. An example of the impurity distribution in the depth direction is shown in FIG. 1
4 is the high concentration impurity layer 3 that was there at the beginning, 15 is the one whose surface degree is lowered by counter ion implantation, and 16 is the high concentration impurity layer 12 that prevents short circuit with wiring. Also, the distribution shape of 15 is high. It can also be formed by increasing the implantation energy when forming the triple impurity layer. The latter method may be used when resistors are added to all the contact portions on the silicon substrate, but when resistors are selectively added, a mask may be used in the former method. In this way, when resistors are selectively added, two or more types of contact resistor parts having different resistance values can be formed on the same chip, and these can be determined as necessary. Furthermore, as shown in FIG. 2(d), the silicon foil plate may be etched to some extent when forming the contact hole, so that a portion of the substrate with a low surface concentration is connected to the distribution layer A. Also, the same figure (e
) is the same as that shown in FIG. 1(d) with an additional short-circuit prevention layer between the wiring layer and the substrate. In all the embodiments described so far, additional resistors are attached to the outside of the transistor, but in this embodiment, an embodiment in which the source and drain of the transistor themselves have a high resistance will be described with reference to FIG. Generally, in order to increase the resistance of the source and drain of a transistor, it is necessary to increase the length of the low-concentration impurity region as described above in the LDD structure, or to form a further low-concentration impurity region within the low-concentration impurity region. good. However, L.D.
In the case of the D structure, the portion of the low concentration impurity region that reaches just below the gate electrode and the bottom of the sidewall spacer also contain the gate M.
If the concentration in the vicinity of one pole is too low, the hot carrier effect will increase, which will conversely lead to a decrease in reliability. Therefore, there is a lower limit to lowering the concentration in this part, which is generally I
Therefore, in the case of an LDD structure, the area near the gate Q even under the gate electrode and under the sidewall spacer is I x 10.
The above embodiment is shown in Fig. 5(a).
This is the structure shown in . After forming the gate electrode, a first low concentration impurity layer 7 is formed, and after forming the first sidewall spacer 8, an impurity of the opposite conductivity type is introduced to form an impurity with a lower concentration than the first low concentration impurity layer. After forming the layer 18 and further forming the second sidewall spacer 17, the high concentration impurity layer 3 is formed. Although this method can also be formed by double diffusion after forming the first sidewall spacer 8, it becomes difficult to form a single spacer especially when the above-mentioned scaling progresses and the line width and line spacing become smaller. In this example, MI with resistance is self-aligned and has good controllability.
9, which can form an S-type field effect transistor.
In the case shown in d), the silicon substrate is also etched after the first sidewall spacer is formed, and then the silicon substrate is etched as shown in the previous figure (d).
Similarly to a), a second low concentration layer etc. are formed. In this embodiment, controllability is further improved by making the source and drain three-dimensional. In the structure shown in FIG. 5(b), a polycrystalline silicon film 20 is stacked above the source and drain, and a high resistance layer 19 with a low impurity concentration is provided in a part of the stacked film. In this case, no high impurity concentration layer is provided in the substrate. This may be determined based on the resistance value to be added, and a high concentration impurity layer may be included. In addition, in FIG. 3(c), the low concentration layer 18 is formed not within the laminated film but within the substrate at the contact portion between the laminated film and the substrate. In this embodiment, in both FIGS. 22(b) and 3(c), self-alignment is achieved, and the margin for alignment between the contact hole between the source, drain, and wiring and the gate electrode can be reduced. In addition to the methods described above, a method of slightly lowering the impurity concentration of the high concentration impurity region itself is also good. However, in this case, if care is not taken when designing the pattern of the high-concentration impurity region, there is a possibility that more resistance will be added than necessary. especially,
This becomes more of a problem when the pattern has a complicated shape, such as a memory cell in a static memory. <Embodiment 4> Further, an embodiment in which the structure of the present invention is applied to a circuit such as a static random access memory (SRAM) will be described with reference to FIG. The circuit diagrams shown in FIGS. 6(a) and 6(b) are SRAM
This is an example in which an additional resistor is attached to a high-resistance load type memory cell and a complete CMO8 type memory cell. In both cases, a resistor is attached only to the drain side of each transistor, but It may also be located at the source or drain of the transfer gate transistor shown in the figure.This eliminates the need to reduce the voltage applied within the memory cell.For this reason, it is not necessary to reduce the voltage applied to the memory cell. It is possible to operate memory cells and peripheral circuits.Generally, in memory, memory cells have a large effect on chip area, so they are made with the minimum dimensions determined by the lithography at that time, but there is enough room for one peripheral circuit.For this reason, peripheral circuits are (5) It is often the case that the scaling for the power supply is relaxed, and the power supply voltage is lowered for the memory cell to use the minimum size.If the structure of this embodiment is used at least inside the memory cell, the inside of the memory cell will also be It can be operated with the same power supply voltage as the circuit, making it possible to achieve a single power supply of, for example, 5V.Furthermore, as miniaturization progresses, it becomes necessary to lower the power supply voltage.At this time, for example, in SRAM, memory The high-level node voltage of the flip-flop in the cell also decreases,
Since the threshold voltage cannot be lowered very much, there is no operating margin for the memory. Furthermore, the method of lowering the voltage only within the memory cell becomes even more difficult. At this time, when the structure of the present invention is used only in the memory cell, by increasing the added resistance value, it can be operated at a higher voltage than the peripheral circuit, and a memory with a large operating margin can be constructed even at a low power supply voltage. be able to. FIG. 6(C) is an example of the circuit configuration. In the figure, Vc is the power supply voltage that supplies power to the peripheral circuits, and Vm is the power supply voltage that supplies power to the memory cell array. In this case, V c < V m. Both of these power supplies may be supplied from outside the chip, or one of them may be boosted or stepped down inside the chip. In addition, as the degree of integration increases in the future, current consumption will also tend to increase.
This is particularly noticeable in memories that aim to increase speed. In this case, there is an upper limit to the current consumption due to restrictions such as the package, and in this case, the power supply to the chip must be reduced. Therefore, from now on, it is best to apply a low power supply voltage to the peripheral circuits inside the chip, and to use an internally boosted power supply for the memory cells using the semiconductor device of the present invention. (Effect of the invention 1 According to the present invention, it is possible to use a fine MIS type field effect transistor without lowering the power supply voltage.
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ion) is particularly effective for horizontal construction of memory such as SRAM.

[Brief explanation of drawings]

Fig. 1 is a 191-plane view and an equivalent circuit diagram of a semiconductor device according to an embodiment of the present invention, and Fig. 2 is a cross-sectional view of an element of an embodiment in which the present invention is applied to an LDD structure, and a series diagram of breakdown voltage between source and drain. A characteristic diagram showing resistance dependence. Figure 3 is a cross-sectional view of an element and a circuit diagram of an example in which the present invention is applied to a CMOS inverter and a NAND gate. Figure 4 is a cross-sectional view of an element in an example in which the present invention is applied to a contact part. FIG. 5 is a cross-sectional view of an element of an embodiment in which the present invention is applied to an SRAM, and FIG. 6 is a circuit diagram and a circuit block diagram of a semiconductor device according to still another embodiment of the present invention. Explanation of symbols 1...Semiconductor substrate, 2...Gate electrode, 3, 12...
・High concentration impurity region, 4... High resistance region, 5... Interlayer insulating film, 6... Aluminum wiring, 7, 11, 18.2
1...Low concentration impurity region, 8.17...Side wall spacer insulating film, 9.10...High resistance film, 13.
...Contact hole, 14, 15, 16... Impurity distribution, 19... Laminated high resistance film, 20... Laminated low resistance film RCQ) 4th quotient is called water Otsu ryoΦmi・tsu4iKiwa4 3 & N1/IJ 5Ej Jino, ;-// 4 V reward, Megξ for sounding! Shiv cat

Claims (1)

[Claims] 1. A semiconductor device having an insulated gate field effect transistor having a source region and a drain region provided on a semiconductor substrate, a channel formed between them, and a gate electrode that exerts a field effect on the channel. A semiconductor device according to claim 1, further comprising a high resistance region externally connected in series with at least one of the source and drain. 2. The semiconductor device according to claim 1, wherein the high resistance region is located within a high concentration impurity region forming a source and a drain of the transistor. 3. The high-resistance region is located in a contact area between a high-concentration impurity region constituting the source and drain of the transistor and an external low-resistance wiring layer, or in a part of the wiring layer. Semiconductor equipment. 4. The semiconductor device according to claim 3, wherein the impurity concentration of the high concentration impurity region at the interface of the contact portion is lower than that of other high concentration impurity regions. 5. The semiconductor device according to claim 3, wherein at least a part of the high resistance region of the wiring layer is located in a hole opened in an interlayer insulating film between the transistor and the low resistance wiring layer. 6. The semiconductor device according to claim 5, wherein the high resistance portion in the hole is a polycrystalline silicon film with a low impurity concentration or a polycrystalline silicon film with a high impurity concentration containing oxygen. 7. At least one of the source and drain of the transistor includes a high concentration impurity region remote from the gate electrode of the transistor, and a first low concentration impurity region existing between the high concentration impurity region and directly under the gate electrode. The semiconductor device according to claim 1, characterized in that the semiconductor device comprises: 8. Claim 4, characterized in that there is a second low concentration impurity region having a lower concentration than the first low concentration impurity region between the first low concentration impurity region and the high concentration impurity region. semiconductor devices. 9. In the method of forming the high resistance region at the contact portion between the high concentration impurity region constituting the source and drain of the transistor and the external low resistance wiring layer, the wiring layer and the insulating film on the high concentration impurity region are formed. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of introducing an impurity having a conductivity type opposite to that of the high concentration impurity region after opening the contact hole. 10. In the method of forming the high-resistance region at the contact portion between the high-concentration impurity region constituting the source and drain of the transistor and an external low-resistance wiring layer, the wiring layer is formed into a multilayer film, and at least one layer of the multilayer film is formed. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of coating a high resistance film on the semiconductor device. 11. In the method of forming the high resistance region at the contact portion between the high concentration impurity region constituting the source and drain of the transistor and the external low resistance wiring layer, the wiring layer and the insulating film on the high concentration impurity region are formed. 4. The semiconductor device according to claim 3, further comprising the steps of, after opening the contact hole, burying a polycrystalline silicon film in the hole, and introducing a low concentration impurity into the buried polycrystalline silicon film. manufacturing method. 12. In the method of forming the high resistance region at the contact portion between the high concentration impurity region constituting the source and drain of the transistor and the external low resistance wiring layer, the wiring layer and the insulating film on the high concentration impurity region are formed. After opening the contact hole, a step of embedding a polycrystalline silicon film in the hole, a step of introducing a high concentration impurity into the buried polycrystalline silicon film, and a step of ionizing a low concentration of oxygen into the polycrystalline silicon film. 4. The method of manufacturing a semiconductor device according to claim 3, further comprising the step of implanting. 13. A semiconductor device, in a plurality of semiconductor device groups provided on a semiconductor substrate, at least one of the semiconductor device groups includes the semiconductor device according to claim 1. 14. The semiconductor device according to claim 13, wherein at least one of the semiconductor device groups is a memory cell group of a static or dynamic storage device. 15. A semiconductor device having two or more types of circuit groups that operate with two or more types of power supply voltages, characterized in that transistors constituting each circuit group are provided with additional resistances depending on the power supply voltages. 16. The semiconductor device according to claim 15, wherein the semiconductor device is a static or dynamic memory device. 17. A semiconductor device having a static or dynamic memory device, wherein a power supply voltage of a memory cell group of the memory device is higher than a power supply voltage of a peripheral circuit group. 18. The semiconductor device according to claim 17, wherein at least a part of the memory cell group of the memory device comprises the semiconductor device according to claim 1.