JPH02279071A - Picture reader - Google Patents

Abstract

PURPOSE:To set picture gradation with an external command freely by storing a gamma correction data into a rewritable storage device in advance and providing a changeover control means rewriting the correction data in the storage device freely in the case of applying gamma correction to the picture data. CONSTITUTION:A buffer 303 is a buffer whose gate is opened when a correction data is written in a gamma table RAM 109 and connects to a data terminal D of the gamma table RAM 109. The gamma table RAM 109 is provided with ai OE(output enable) terminal to output the data written therein and a data is outputted to either the data terminal of the gamma table RAM 109 or the buffer 303. A switching signal is controlled by a line read start signal LSRT. Thus, the gradation of the picture is set freely by an external command.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to an image reading device, and particularly to an image reading device for obtaining image data faithful to an original image.

[Conventional technology]

In recent years, originals are read using a photoelectric conversion element such as a COD image sensor, the read image data is converted into analog/digital (A/D), and various digital processing is performed to form an image on a printer or on a CRT. Devices that display images are known. Conventionally, in this type of device, if the image data read by the COD image sensor is directly output to an output device such as a printer, the luminous density will be lowered due to the difference between the sensitivity of the COD image sensor and the sensitivity seen by humans. It is common to perform so-called γ correction.

[Problems to be solved by the invention]

By the way, in the above-mentioned device, a number of patterns of gamma correction data are stored in advance in a large-capacity ROM (read-only memory) in accordance with the output characteristics of an output device such as a printer, and the data for gamma correction is Image data corrected based on this information is output. Therefore, it is necessary to determine the γ correction value in advance by considering the characteristics of the printer, and even if γ correction is performed for different output devices such as printers,
An image different from the image requested by the user is output. This also has the disadvantage that the types of output devices such as printers to which the image reading device is attached are limited.

[Purpose of the invention]

This invention solves the above-mentioned problems by storing the correction data in a rewritable storage device that can be set freely from the outside when performing γ correction on image data, and outputs data from a printer having any output characteristic. It is an object of the present invention to provide a highly versatile image reading device that can be applied to other devices.

[Means to solve the problem]

That is, the image reading device of the present invention includes an image reading means for reading an image of a document, an A/D converter for converting image data output from the image reading means into digital image data, and an A/D converter for converting image data output from the image reading means into digital image data. A γ correction means for correcting the image data to a specific value using correction data and outputting the corrected image data, a rewritable storage device for storing the correction data of the γ correction means in advance, and a rewritable storage device for freely rewriting the correction data in the storage device. The invention is characterized in that it has a switching control means.

【Example】

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image reading apparatus of the present invention will be described in detail below with reference to the drawings. 1 and 2 are simplified configuration diagrams of a color image reading device to which the present invention is applicable. A document placed face down on a document table 10 is irradiated with a light source lamp 1 such as a fluorescent lamp, and consists of reflective mirrors 2, 34, a color filter 5 (can be switched to 6.7 by rotating), an optical lens 8, etc. An image of the original is formed on an image reading means made of a photoelectric conversion element such as a CCD image sensor 9 via an optical system, and the original is read in the main scanning direction. As shown in FIG. By pulling it, the document moves along a guide rail 12 arranged parallel to the document table 10 . An image reading means consisting of a photoelectric conversion element such as the CCD image sensor 9, which scans the document table 10 and reads the document in the sub-scanning direction, is installed at a suitable location in the apparatus, and reads the image of the document. Convert images into electrical signals. 11 is a reference white plate for shading distortion correction. Next, FIG. 3 shows switching means for the color filters 5, 6.7. That is, color filters 5°6.7, each of which transmits only light of a specific wavelength, are arranged at predetermined intervals in a cylindrical filter holder 16, and the filter holder 16 is rotated by a motor 17 connected in the axial direction. The color filters 5, 6, and 7 are switched. The filter holder 16 is installed in front of the optical lens 8 placed in front of the CCD image sensor 9, and is switched and controlled separately from the movement of the carriage 22. After reading the image of the original, the filter holder 16 is rotated in parallel with the operation of returning the carriage 22 to the scanning start position, thereby efficiently switching. While the filter holder 16 is rotating, the position of the next filter is detected by the detection disk 18 and the detection sensor 19, and the filters are switched with high precision. These three color filters 5, 6.7 color-separate the information of the color document into red, green, and blue. The filter switching means is switched and controlled by a CPU, which will be described later. This C
The control means consisting of PU drives the motor 17 based on the filter position detected by the detection sensor 19, rotates the filter holder 16 by a predetermined angle, and rotates the color filter 5.6.7.
The information of a color document is separated into red, green, and blue by switching sequentially. The control scheme for document scanning will be explained with reference to the flowchart in FIG. First, when the power switch is turned on, the LEDs on the operation unit light up in sequence to notify the operator that the power is turned on and the CPU is operating normally (SPI).
Next, the carriage 21, 22 carrying the optical system moves in the opposite direction to the sub-scanning movement direction, and when it crosses a sensor at a predetermined standby position, the so-called home position, the position of the optical system is detected. (SF3). From there, it moves another 47 steps in the opposite direction and stops. When the steps up to this point are completed, a polling state is entered in which commands from the host computer, such as starting reading, are accepted (SF3). When a read start command is sent from the host computer, the red filter 5 is selected from among the three color filters 5 and 6.7 in preparation for reading (S
F3), then read the black reference data that will be the reference data for shading distortion correction (SF3), from here 1
The motor 14 is advanced in the sub-scanning direction by 32 steps (SF
6). Here, turn on lamp 1 (SF3), and turn on lamp 1 for 1 second.
Wait for it to stabilize (SF3). The reference white plate 11 is read at this position (SF3). This is to obtain white reference data for shading distortion correction, as described above. From here, the optical system is further moved in the main scanning direction to the reading start position (SPIO). At this stage, a signal for reading one screen with the red filter 5 must be set in the hardware (5PII), and then further in the sub-scanning direction. Set a signal to read one line in the hardware (SF12). When the reading for one line is completed, an end interrupt is generated from the hardware (SF12).
F13), Since reading of one line is completed, move the optical system to the next line (SF14), Send the image data of one line read at this time to the host computer side (SF15) ), when the transmission of the image data is completed, it is determined that the screen reading has ended by looking at the flag indicating that one screen has been read (SF16).
). If it is not finished, return to 5P12, and when finished, turn off the lamp 1 (5P17), switch to the next green filter 6 (SPL8), and at the same time return the optical system to the position for obtaining the white reference. Repeat the same operation for the blue filter. That is, a color original is used by switching color filters, and the optical system is scanned three times to separate the image signal components into three color image signal components and read them. Next, the basic circuit configuration of the image reading device of the present invention will be explained with reference to FIG. The image of the original image formed through the reflecting mirrors 2, 3.4 and the optical lens 8 in FIG. be done. This signal is converted into a digital signal by an A/D converter 103. As it is, shading distortion is included due to uneven luminous intensity distribution of the light source consisting of the lamp l, uneven luminous intensity due to dirt on the glass surface of the document table 10 and reflection mirrors 2 and 3.4, and uneven luminous intensity distribution of the optical lens 8. , performs digital calculation to correct this shading distortion. The shading distortion correction means includes a correction memory 106 consisting of a RAM (random access memory) that stores a reference white level and a reference black level, a shading correction calculation circuit 105 that performs digital calculations, and the correction memory 10
The clock generator 104 controls the timing of writing/reading data to and from 6. The signal after the shading distortion correction is converted into a predetermined density by a density conversion means consisting of a density conversion circuit 107. The density adjustment means consisting of the density adjustment circuit 108 adjusts the density by adding or subtracting a certain value to the digital image signal. These shading distortion correction means, density conversion means, and density adjustment means are
It is desirable to be able to develop quickly by creating a gate array (A in the figure). Once the digital image signal has been prepared through the above operations, γ correction is performed to match the human visual sensitivity. By performing γ correction after processing density/density, etc., the read image can be improved. This makes it possible to prevent deterioration of the output image, such as loss of gradation or blurring of the outline of the output image. Rewritable storage device e.g. γ
A table RAM (γ correction circuit) 109 stores digital image signals adjusted by processing the density/density, etc.
The data output from the RAM becomes the image signal after the γ correction. Before reading the contents of the γ table RAM 109, data for γ correction is written. The γ-corrected digital image signal is converted into 2-value data by a binary/dither conversion circuit IO consisting of a gate array (B in the figure).
Value conversion or dither conversion processing is performed. It is also possible to bypass this circuit 110 without performing binary/dither conversion processing. The digital image signal processed as described above is written into a line memory (RAM) 111 that can store one main scanning line. The digital image signal stored in the line memory 111 is read out in response to a request from the CPU (central processing unit) 112 shown in FIG.
4 to an external device. FIG. 6 shows the shading distortion correction calculation circuit 10 of FIG.
5. It is a block diagram of each circuit of the density conversion circuit 107 and the density|concentration adjustment circuit 108, and this is demonstrated. The correction formula for shading distortion correction is as follows.The procedure for realizing this formula will be described. ■ -Read the black reference board and correct the shading distortion R.
It is written to AM202 as reference black level data. (2) While reading the reference black level data, read the --like white reference plate and input the two data to the subtracter 2o3. Then, the difference is written as (reference white level - reference black level) into the shading distortion correction RAM 2024::. ■ The original is read while reading the reference black level data to the input of the subtracter 203 and the (reference white level - reference black level) data to the input of the multiplier/divider 204, and the signal of the image data is first input to the subtracter 203. (signal-reference black level) is obtained, and then input to the multiplier/divider 204. The output of the multiplier/divider 204 at this time becomes a digital image signal after shading distortion correction. This digital image signal is stored in the shading distortion correction RAM 20 for sub-scanning density conversion.
2, and repeat this ■ until the original is read. The above operations are controlled by a timing signal synchronized with the CCD drive clock, and the generator 201 also generates a strobe signal indicating the valid period of the digital image signal. The density conversion by the density conversion circuit 107 with the magnification set is as follows:
The scanning is performed separately for main scanning and sub-scanning. First, the sub-scanning density conversion circuit 205 performs sub-scanning density conversion. Prior to this, the read data of the previous line stored in the shading distortion correction RAM 202 is read out and averaged with the currently read data. Which line to take the average is determined by the sub-scanning density conversion logic circuit 206. Next, the main scanning density conversion circuit 207 is determined in the same way.
208 is a main scanning density conversion logic circuit. The image data subjected to density conversion through the above operations is subjected to density adjustment by a density adjustment circuit 1.8 controlled by the CPU. That is, the image density is adjusted by adding or subtracting a certain value to the image data. Next, the γ correction means related to the γ table RAM 109 shown in FIG. 5 will be explained with reference to FIG. Buffer 301 contains image data and γ table RAM1
09, and the register 302 is a register with a gate that holds an address when writing correction data to the γ table RAM 109. Both the buffer 301 and register 302 are γ table RA
It is for specifying the address of M109, either one
One is always connected to the address terminal A of the γ table RAM 109. Next, a switching control means that allows the correction data in the γ table RAM 109 to be freely rewritten will be described. The buffer 303 is a buffer that opens the gate when writing correction data to the γ table RAM 109, and is connected to the data terminal of the γ table RAM LO9. The γ table RAM 109 also has an OE (output enable) terminal for outputting written data, and data is output from either the data terminal of the γ table RAM 109 or the buffer 303. The switching signal is controlled by the line read start signal LSRT. The procedure for writing the above correction data will be explained with reference to FIG. In this case, since the LSRT signal is not output, the register 302 and the buffer 303 function as an oven, and the data output terminals of the buffer 301 and the γ table RAM 109 are closed. First, in order to specify the address on the γ table RAM 109 in SPI, address data is written in the register 302 selected in advance by the CPU.Next, in SP2, correction data is written in the γ table RAMLO9. When the table RAM 109 is selected in advance, data is written. This makes the writing control software somewhat complicated, but the CPU
When looking at the γ table RAM 109, there is only one address, and there is no need to connect the address bus from the CPU, which simplifies the circuit configuration. Next, in the γ correction procedure, when LSRT is output, the data output terminals of the buffer 301 and the γ table RAM 109 are opened, and the register 302 and buffer 303 are closed. Therefore, the density-adjusted image data shown in FIG. 6 is input to the address section of the γ table RAM 109, and data corresponding to the address at the time of input is output as corrected data. Conventionally, for this γ correction data, a large-capacity ROM was prepared instead of the γ table RAM 109, correction data for several patterns were registered in the ROM in advance, and the correction data was exchanged by switching the patterns. However, this method requires a separate pattern switching circuit, and the RAM
The circuit size is about the same as when Therefore R.O.
The advantages of replacing M with RAM are far greater. By using RAM, a pattern switching circuit is no longer required, and correction data can be located in the memory area managed by the CPU, so corrections and changes can be made freely. be. It is also possible to specify correction data from the outside through the interface circuit. In the image reading device of this invention, actual image data is read at 256 gradations (1), output data after correction is 64 gradations (6 bits), and the rest is 2 bits "0" from the LSB (least significant bit). However, 2 bits “0” from the MSB (most significant bit) are also possible, and 64
You can freely change not only the gradation, but also 16 gradations, 8 gradations, and 4 gradations. By using RAM, you can gain an immeasurable degree of freedom. Note that the rewritable storage device is not limited to RAM, but may also be core memory, floppy disk, magnetic bubble memory, etc. Next, by the binary/dither conversion circuit 110 shown in FIG.
Means for comparing the image data with the slice level value of the dither pattern block and outputting it as binary data (■ below), specifying the - location of the dither pattern block, and outputting the digitized image data. The means for outputting the data as binary data (see below) and the rewriting means for arbitrarily rewriting the slice level value of the dither pattern block (see below) will be explained in detail with reference to FIG. In the following description, it is assumed that the slice data written to the binary dither memory 404 consisting of the image data 410 and the RAM has a length of 8 bits. Naturally, the comparator 411 also has a length of 8 bits. Control of the image reading device of the present invention, for example, a readout control signal,
Permission/prohibition of buffer output, setting of the X-axis address 407 and Y-axis address 408, and data transfer to the binary dither RAM 404 are all controlled by the cPU 112. (2) The procedure for writing slice data into the binary dither RAM 404 will be explained. The buffered latch 402 and the buffer 403 are enabled to output, and the CPU data bus 40 is first
The address is latched from 9 to the buffered latch 402.0 Next, slice data is given to 2 (11) dither memory (RAM) 404 via the buffer 403, and at the same time a write pulse is sent to the write control signal 405 to write one data. Thereafter, the above operation is repeated as many times as necessary to finish writing the slice data. At this time, the read control signal is kept in a state where reading is prohibited. In addition, the write control signal 405 is set to a write-inhibited state, and the slice data storage state during binarization is as shown in FIG. Therefore, the X-axis address 407 and the Y-axis address 408 are fixed to address 1, and by setting the read control signal 406 to a read permission state of 0 or more, the binarized slice data is input from the RAM 404 to the comparator 411. Here, when the image data 410 is input to the comparator 411, it is compared with the slice level value and binarized data can be obtained.
, the buffer 403, the write control signal 405, and the read control signal 406 are kept in the same state as in the binarization procedure in (2). FIG. 11 shows an example of a dither pattern block in a state in which slice data is stored during dither processing. Like 4×
A dither matrix of 4 was used. Of course iXJ (ij
is an integer). Before reading starts, set the X-axis address 407 so that address 1 is selected.
, and set the Y-axis address 408. Comparator 411
The slice data written to address 1 is input to. Here, when one pixel is read and input to the comparator 411, it is compared with the slice level value and two pixels of white or black are read.
Obtain valued data. At this time, the X-axis address 407 is incremented by one in synchronization with a strobe signal (not shown) representing binarization, and the address is set for the next data. Thereafter, the address increases sequentially as shown by ■ in FIG. 11, but when address 4 is reached, the X-axis address 407 is controlled so as to return to address 1 again. Repeat this for one line. When one line is finished, move to Y-axis address 40.
8 is incremented by one, and the X-axis address 407 is reset so that address 5 is selected. From then on, the addresses will change from addresses 1 to 4 to addresses 5 to 8.9 to 12.13 to
16, and performs processing like the interval of one line as shown in Figure 11 ■ to ■. When the l line of Figure 11 ■ is completed, the X-axis address 407 and Y-axis address 408 are reset. control so that address 1 is selected again. Thereafter, the above operation is repeated until all lines have been read. ■ In this circuit, the slice data value can be arbitrarily set to an 8-bit length. In addition, since the size of the dither matrix and the structure of slice data can be set arbitrarily, it is possible to freely obtain dithered images that match the original image, and when converting into binarization, it is possible to freely create binary values that are either dark or light. It becomes possible to obtain a converted image. Additionally, since the memory for binarization and dither processing is shared, the binarization comparison circuits that previously had to be prepared can be combined into one, simplifying the circuit and reducing the number of parts. . Finally, the write address control means for arbitrarily specifying the write address of image data in the line memory 111 of FIG. 5 will be explained using the memory write circuit of FIG. 12. The interface 501 is for inputting and outputting data from the outside, and enables DMA (direct memory access mode) operation. Buffer 502 is for accessing line memory Ill by CPU 112, and is a gate that is enabled except during DMA operation and image data reading. Register 503 is DMA
This is an address setting register for outputting the data in the line memory 111 to the outside via the interface 501 by operation, and the first address to be transferred is set by the CPU.
112. It is auto-incremented after one cycle of read operation. Buffer 504 is the current gate and is valid during the DMA operation. The register 505 is a register that specifies the start address when writing the image data 410 to the line memory 111, and is auto-incremented after writing. Buffer 506 is the gate at that time and is enabled during image data reading. The buffer 509 is a data gate for writing the image data 410 into a storage device, for example, the line memory 111, and is enabled while the image data is being read. Line memory 111 contains image data 410 and CPU1
accessed directly from 12. This line memory 111
is a RAM having a data storage area for temporarily storing the digital amount of image data that increases or decreases, and a data storage area for storing data handled by the CPU 112 (work data). Buffer 508 is CPU 11
This is a gate for directly reading/writing data from 2 to the line memory 111, and is valid during DMA operation and during image data reading. DMA control circuit 51
0 is a part that performs general DMA control, and consists of R/W logic, DMA activation, word count register, etc. For R/W from the CPU 112, the address is valid from the buffer 502 and the data from the buffer 508 is valid.
All addresses of line memory 111 are accessible. In the DMA operation, the first address to be transferred is written in the register 503, the number of bytes to be transferred is written in the word count register in the DMA control unit 510, and DMA is activated.The address is transferred from the buffer 504 to the line memory 11.
The D terminals of 1 and 1 become valid, respectively, and 1 and 1 are enabled without going through the CPU 112. Data is output to the outside via the interface byte by byte. At this time, when the 1-byte transfer is completed, the register 503 is auto-incremented. The writing operation of the image data 410 to the line memory 111 is performed by writing the write start address to the register 505 and then writing the image data 410 to the line memory 111 by a WT (write) signal output in synchronization with the image data 410.
The image data 410 is written to an arbitrary address. At the same time, the contents of register 505 are also auto-incremented. By writing the image data 410 from an arbitrary position in the line memory 111 as described above, when transferring the image data 410 to the outside through an interface circuit, it is possible to easily add a certain code to the beginning of the image data 410. can be executed. Further, when the line memory 111 is used as a work area for the CPU 112, the image data 410 can be written in a free area, so that the memory (RAM) can be used effectively. Furthermore, multiple lines of image data are stored in the same memory (R
AM) can be stored on the line memory 111 with a single memory element, making it easy to convert transfer formats.
It is possible to share the memory of the CPU with the CPU, which greatly simplifies the circuit configuration.

【Effect of the invention】

As described above, in the image reading device of the present invention, when gamma-correcting image data, the correction data for gamma correction is stored in advance in a rewritable storage device, and the correction data in this storage device can be freely rewritten. and a switching control means. Therefore, it is possible to provide an image reading device that can be attached to an output device such as a printer having any output characteristics. Furthermore, since the correction data in the storage device can be freely rewritten, the gradation of the image can be freely set by external instructions.

[Brief explanation of drawings]

FIG. 1 is a simplified configuration diagram of a color image reading device to which the present invention can be applied, FIG. 2 is a configuration diagram showing a means for moving the carriage shown in FIG. 1, and FIG. 3 is an explanatory diagram of filter switching means. Fig. 4 is a color image reading device control flowchart, Fig. 5 is a block diagram of the electric circuit, Fig. 6 is a block diagram for shading distortion correction, density conversion, and density adjustment, and Fig. 7 is a block diagram for γ correction. 8 is a partial flowchart of FIG. 7, FIG. 9 is a block diagram of the binary/dither converter, FIGS. 10 and 11 are explanatory diagrams of the dither matrix, and FIG. 12 is a memory diagram. FIG. 3 is a configuration diagram of a writing section. 9... Photoelectric conversion element 103... A/D converter 109... γ table RAM 301... Buffer 302... Register 30
3...Buffer patent applicant: A Hon Seimitsu Kogyo Co., Ltd. Same as above: NEC Corporation

Claims (1)

[Claims] 1. An image reading means for reading an image of a document; an A/D converter for converting image data from the image reading means into digital image data; The present invention includes a γ correction means for correcting and outputting a value, a rewritable storage device for storing correction data of the γ correction means in advance, and a switching control means for freely rewriting the correction data in this storage device. Characteristic image reading device.