JPH02279022A - Bch decoding circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for the production of an exclusive clock and the speed conversion processing by exclusively ORing bit error information obtained from a calculated syndrome and a data part of a BCH error correction code subject to parallel conversion to correct the bit error of the data part. CONSTITUTION:A serial parallel conversion means 11 applies parallel conversion to all bits of a data part and a parity part of a received BCH error correction code. A division means 13 fetches the BCH error correction code subject to parallel conversion, and exclusive OR is taken with a generation polynomial when the most significant bit of a dividend of each stage is logical '1' through the division processing in which the generation polynomial is used as a divisor and when the result is logical '0', the arithmetic processing taking OR with all '0' is repeated to calculate a syndrome. Then an error correction means 15 takes exclusive OR between bit error information obtained from the syndrome and the data part of the BCH error correction code subject to parallel conversion to correct the bit error of the data part. Thus, the production of an exclusive clock and the speed conversion processing are not required.

Description

[Detailed Description of the Invention] [Summary] The purpose of this invention is to eliminate the need for dedicated clock generation and speed conversion processing for division processing for calculating syndromes in a BCH decoding circuit that performs error correction using a BCH error correction code. , serial-parallel converting means for parallel converting all bits of the data part and parity part of the received BCH error correction code;
The parallel-converted BCH error correction code is taken in, and if the most significant bit of the dividend in each stage is "1" in the division process using the generator polynomial as the divisor, it is exclusive ORed with the generator polynomial, and if it is "0" If so, a division means calculates the syndrome by repeating the arithmetic process of calculating the logical sum with all 0s, and the exclusive logical sum of the bit error information obtained from this syndrome and the data part of the parallel-converted BCH error correction code. and error correction means for correcting bit errors in the data part.

[Industrial application field]

The present invention provides B
The present invention relates to a BCH decoding circuit that performs error correction using a CH error correction code.

In particular, the present invention relates to a BCH decoding circuit with improved division means for calculating syndromes for obtaining bit error information necessary for error correction.

[Conventional technology]

In the DLC (Digital Loop Carrier) system that the DDS network has introduced to accommodate remotely located subscribers, there are RT) which interphases with the line
Mbps) It is possible to multiplex up to 24 channels to efficiently accommodate subscribers.

In such systems, in order to guarantee the quality of transmitted data, for example, a BCH error correction code based on a (16.8) BCH algorithm, which is a shortened version of the (17,9) BCH algorithm, is used. This BCH error correction code generates an 8-bit parity part for the 8-bit data part, and transmits it as a combined 16-bit BCH error correction code (BCH code) with redundancy. be. Also, on the receiving side, this 16-bit BC
8 after receiving the H error correction code and performing error correction processing.
Outputs only the data part of the bit.

Therefore, even if the data rate on the network side and the subscriber line side is, for example, 64 kbps, on the multiplexed line between them, the B
A CH error correction code will be transmitted.

Here, the flow of processing of the BCH error correction code will be explained.

The BCH encoding circuit has an 8-bit data section [10101
010], the 8-bit parity part (010000
10], and calculate 1 which is the sum of the data part and parity part.
As a 6-bit BCH error correction code, it is multiplexed in a predetermined manner via a multiplexing circuit and sent out on the line. If a 1-bit error occurs on the line for this 16-bit BCH error correction code, the receiving side will receive, for example, (10
10100001000010), one bit is received incorrectly (marked with *).

Note that the generator polynomial for this BCH error correction code is
x ”+ x ’+ x ’+ x ’+ 1 (10
0111001).

FIG. 4 is a block diagram showing an example of the configuration of a conventional BCH decoding circuit that performs error correction using such a CH error correction code.

In the figure, the division circuit 41 receives 16 bits)
Division is performed using the (128 kbps) BC)l error correction code as the dividend and the generator polynomial as the divisor, and the syndrome (01110010) that is the remainder is calculated.

This syndrome is caused by the R
This serves as an address input to the OM 42, and 8-bit bit error information (00000010) is output from the ROM 42.

Also, the received 16-bit (128 kbps) BC
The data part (10101000) of the upper 8 bits of the H error correction code is extracted via the data part extraction circuit 43. This data section signal is transmitted to the data rate conversion circuit 44.
Speed conversion to a data rate of 64 kbps is performed via the divider circuit 41 and the RO
A delay corresponding to the access time of M42 is provided.

The exclusive OR circuit (EXOR) 46 receives the bit error information (00000010) output from the ROM 42,
The 8-bit data section (10 bits) output from the delay circuit 45
101000), and the error-corrected 8-bit data part (10101010) is output as a signal with a data rate of 64 kbps.

FIG. 5 is a block diagram showing an example of the configuration of a conventional division circuit used in such a CH decoding circuit.

In the figure, the division circuit includes serially connected registers (Do to D7) 51° to 51? , exclusive OR circuits 53° to 53 . are inserted, and the respective registers (D7) 51? The configuration is such that an exclusive OR with the output of is taken.

16-bit BCH error correction code (101010000
1000010) is serially input to this division circuit.

The table shows the state transition of each register in response to the input signal of this division circuit.

Note that the values of each register at the time when all 16-bit BCH error correction codes including the 8-bit data part and parity part are input are latched into the 8-bit latch circuit 55 as the syndrome of the BCH error correction code.

(Margins below this page) [Problem to be solved by the invention] Such a conventional division circuit has an 8-bit data section and a parity section that are 16-bit (128 kbps) BC.
12 to be input serially as an H error correction code.
An 8kHz clock was required.

However, the actual data speed is 64kbps, which is 64kbps.
Although 4 kHz and 8 kHz clocks are present in the device, 128 kHz or higher clocks are not used. Therefore, in order to perform a division operation using a conventional division circuit, it was necessary to generate a dedicated 128 kHz clock.

The error corrected data must also be converted to a 64 kbps data rate for interfacing to the DDS network or subscriber line. That is, in order to input the burst signal on the multiplexed line (1,544 Mbps) to the divider circuit, the data rate is 128 Mbps.
Convert to kbps serial signal and further convert to 64kbps
must be converted to a data rate of therefore,
When a conventional division circuit is used, two speed conversion processes are required.

The present invention solves these conventional problems,
When calculating the syndrome of BCH error correction code,
It is an object of the present invention to provide a BCH decoding circuit that can eliminate the need for dedicated clock generation and speed conversion processing required only for the division processing.

In addition, the same applicant has already filed a patent application I for the same purpose.
II (Japanese Patent Application No. 63-145272, "Dividing Circuit"), the present invention achieves the object with a different structure.

[Means to solve the problem]

FIG. 1 is a block diagram of the principle of the present invention.

In the figure, the serial/parallel converter 11 converts the received BC)
All bits of the data part and parity part of the error correction code are converted into parallel.

The division means 13 takes in the parallel-converted BCH error correction code, performs a division process using the generator polynomial as a divisor, and performs an exclusive OR with the generator polynomial if the most significant bit of the dividend in each stage is "1". , if it is "0", the syndrome is calculated by repeating the arithmetic process of calculating the logical sum with all 0s.

The error correction means 15 takes the exclusive OR of the bit error information obtained from this syndrome and the data part of the parallel-converted BCH error correction code, and corrects the bit error in the data part.

[For production]

FIG. 2 shows the above-mentioned BCH error correction code (101010
division means 13 corresponding to the input of 0001000010)
It is a figure explaining the principle of operation of.

The 16-bit BCH error correction code is converted into serial/parallel converter 1.
1, the signal is parallel-converted and input to the dividing means 13.

The dividing means 13 uses the generator polynomial (100111001)
A division operation is performed with . If so, an arithmetic operation is performed to logically OR it with all 0s, and the final remainder (01110010) becomes the syndrome to be sought.

The error correction means 15 uses the syndrome obtained by the division means 13 as an address input to the ROM 17, and extracts bit error information necessary for BCH error correction. Next, an exclusive OR circuit (EXOR) 18 performs an exclusive OR of the bit error information and the data portion of the BCH error correction code converted into parallel, thereby correcting the bit error in the data portion. Error-corrected data can be obtained from the 8-bit latch circuit 19.

[Example] Hereinafter, an example of the present invention will be described based on the drawings.

FIG. 3 is a block diagram showing the configuration of an embodiment of the serial/parallel conversion means and division means used in the BCH decoding circuit of the present invention.

Note that FIG. 3(a) shows its overall configuration, and FIG. 3(b) shows its overall configuration.
) shows the configuration of an embodiment of each arithmetic circuit used in the division means.

In the figure, a 16-bit latch circuit 31 corresponding to the serial-to-parallel conversion means receives a 16-bit BCH error correction code (1010100001000) input as a serial signal.
010) are converted into parallel and output. Note that the 8-bit data section (10101000) is output from output terminals Q1 to Q8, and the 8-bit parity section (01
000010) are output from output terminals Q9 to Q16.

The dividing means includes eight arithmetic circuits 33° to 33.
and an 8-bit latch circuit 39.

The arithmetic circuit 33 has input terminals 11 to I9 and output terminals 01-
08. The input terminals 12, 13° 17.18 and the output terminals Of, 02, 06, 07 are directly connected, respectively. Exclusive OR circuit (EXOR) 34, 35, 36
．． The input terminal El is connected to each one input of 37, and the input terminals I4, 15, 16.1 are connected to the other input of each
9 is connected, and each output has output terminals 03 and 04, respectively.
05.08 is connected. The arrangement of the exclusive OR circuits corresponds to the generator polynomial, and the output data thereof corresponds to the calculation results of each stage shown in FIG.

Arithmetic circuit 33. The output terminals Ql-QB of the 16-bit latch circuit 31 corresponding to each bit of the data section and the output terminal Q9 corresponding to the most significant bit of the parity section are connected to the input terminal It-19 of the 16-bit latch circuit 31. The input terminals ■1 to I9 of the arithmetic circuit 33□ are connected to the arithmetic circuit 33. output terminal O1~
Output terminal QIO of 08 and 16 bit latch circuit 31
is connected.

Similarly, each arithmetic circuit 33. ~33. is connected,
Output terminals 01 to 08 of the arithmetic circuit 33° are connected to an 8-bit latch circuit 39.

Note that the figure shows output data of a 16-bit latch circuit and each arithmetic circuit.

In such a configuration, each arithmetic circuit 33 performs exclusive OR with the generator polynomial if the most significant bit (■1) of the input data is "1", and performs exclusive OR with the generator polynomial if it is "0" By repeating the calculation process of calculating the sum, the final calculation circuit 33. You can output the syndrome from .

That is, the data (01110010) input to the 8-bit latch circuit 39 is the syndrome that is finally sought.

[Effects of the Invention] As described above, the division means used in the BCH decoding circuit of the present invention has a 128k
1 that is input in parallel without requiring a Hz clock
By logical operation processing of 6-bit BCH error correction code,
8-bit syndromes can be output in parallel immediately.

In addition, in the error correction process of the BCH error correction code, 6
It becomes possible to directly convert to a data rate of 4 kbps.

In this way, it is possible to realize a CH decoding circuit that can speed up syndrome calculation with a simple configuration, and is extremely useful in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention; FIG. 2 is a diagram explaining the operating principle of the division means according to the present invention; FIG. 3 is a block diagram showing the configuration of an embodiment of the serial-to-parallel conversion means and the division means; FIG. 5 is a block diagram showing an example of the configuration of a conventional BCH decoding circuit, and FIG. 5 is a block diagram showing an example of the configuration of a conventional division circuit. In the figure, 1 is a serial/parallel conversion means, 3 is a division means, 5 is an error correction means, and 7 is a ROM. 8 is an exclusive OR circuit (EXOR), 9 is an 8-bit latch circuit, 1 is a 16-bit latch circuit, 3 is an arithmetic circuit, ~37 is an exclusive OR circuit (EXOR), is an 8-bit latch circuit, is a division circuit, is ROM. is a data part extraction circuit, is a data rate conversion circuit, is a delay circuit, is an exclusive OR circuit (EXOR), is a register, is an exclusive OR circuit (EXOR), and is an 8-bit latch circuit.

Claims (1)

[Claims] (1) Serial-to-parallel conversion means (11) for parallel converting all bits of the data part and parity part of the received BCH error correction code; and division by taking in the parallel-converted BCH error correction code and using the generator polynomial as a divisor. In the process, if the most significant bit of the dividend in each stage is "1", take the exclusive OR with the generator polynomial, and if it is "0", take the OR with all 0s. The syndrome is calculated by repeating the calculation process. The division means (13
), and an error correction means (15) for correcting bit errors in the data part by performing an exclusive OR of the bit error information obtained from this syndrome and the data part of the parallel-converted BCH error correction code. B characterized by having
CH decoding circuit.