JPH0227768A - Thin film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE:To eliminate the short-circuit defect of a TFT due to the pinhole of a thin film by forming a gate insulating film interposed between a gate electrode and an operating semiconductor layer of a polyimide layer having specific thermal expansion coefficient. CONSTITUTION:A gate insulating film 3 interposed between a gate electrode G and an operating semiconductor layer 5 is formed of a polyimide layer having 4X10<-6>-4X10<-5> [ deg.K<-1>] of thermal expansion coefficient. The polyimide film may be formed of a single layer or multilayers, and in case of the multilayer configuration, a short-circuit defect due to a pinhole can be more effectively prevented. When the polyimide film is formed by a spin coating method, pinholes in the film is extremely reduced. The thermal expansion coefficient of the inorganic semiconductor layer of a-Si layer for forming an operating semiconductor layer 4 is approx. 3X10<-6>[ deg.K<-1>], while when the polyimide film is employed as the film 3, the difference of both can be reduced, and cracks due to thermal expansion, contraction are eliminated.

Description

[Detailed Description of the Invention] [Summary] Active matrix type liquid crystal display devices and electronic
Regarding thin film transistors (TPTs) used to drive luminescent panels, etc., and their manufacturing methods, this article aims to eliminate short-circuit defects in TPTs caused by pinholes in the thin film.

In a thin film transistor having an active semiconductor layer, a gate electrode, and a gate insulating film interposed between the active semiconductor layer and the gate electrode, the gate insulating film has a coefficient of thermal expansion of 4.
The structure is made of a polyimide film of X 10-b to 4 X to-'('K-1).

[Industrial application field]

The present invention relates to a thin film transistor (TPT) used for driving an active matrix liquid crystal display device, an electroluminescent (EL) panel, etc., and a method for manufacturing the same.

A TPT matrix in which a TPT is arranged at each intersection of a data bus line and a scan path line is used to drive this type of liquid crystal display device or EL panel, etc., but the TPT matrix used here is free from short circuit defects. It is necessary that TPT be integrated. The reason for this is that if there is even one short-circuit defective TPT, the pass line connected to the defective TPT will be short-circuited, and in the display device, all pixels connected to that pass line will cause display defects, so-called This is because it becomes a serious defect called a line defect.

[Conventional technology]

FIG. 4 shows a cross-sectional structure of a main part of a conventional thin film transistor (TPT).

■ is an insulating substrate like a glass substrate, G is about 80n thick
3 is a gate insulating film made of a 5iN (silicon nitride) film with a thickness of about 300 nm, and 5 is an a-5i (amorphous) film with a thickness of about 1100 nm. 6 is a protective film made of Stow (silicon dioxide) film with a thickness of about 1100 nm, and S and D are about 39 nm thick.
The source and drain electrodes are made of n''a-5iN9 and a Ti (titanium) film 10 with a thickness of about 1100 nm.

Each layer of the SiN film, a-Si layer, and Si0g film is made of 5IH4 (silane) and NH, (ammonia) + S, respectively.
i H4r S I Plasma chemical vapor deposition (P-CVD) using a mixed atmosphere of Ha and N20 (nitrogen oxide)
Formed by law.

[Problem to be solved by the invention]

The rate of occurrence of TPT short circuit defects in the above structure depends on the pinhole density of the gate insulating film 3.

P-CV conventionally used to form gate insulating film 3
Method D is known as a film forming method with the lowest pinhole density among adhesion forming methods.

However, there are still no pinholes in the insulating film formed by the P-CVD method, and there are 4 to 5 pinholes per square centimeter.

Therefore, TP integrated with TPT using such a film
The T matrix cannot completely eliminate short circuit defects. In order to obtain a high yield under such circumstances, a redundant configuration in which a plurality of TPTs are connected to one pixel is adopted. With this configuration, when a defective element is detected, the defective element can be repaired by cutting it with a laser, thereby improving manufacturing yield. However, this repair is difficult to automate and requires a large amount of man-hours.

An object of the present invention is to eliminate the occurrence of short-circuit defects in TPT due to pinholes in the thin film constituting the TPT, and to make it possible to manufacture a TPT matrix with high yield.

[Means to solve the problem]

As shown in FIG. 1, in the present invention, the gate insulating film 3 interposed between the gate electrode G and the active semiconductor layer 5 has a thermal expansion coefficient of 4XlO-' to 4Xl0-'("K-1"). It is formed using a polyimide film.

The polyimide film constituting the gate insulating film 3 may be a single layer or a multilayer structure, and a multilayer structure can more reliably prevent short-circuit defects caused by pinholes.

In FIG. 1 and FIG. 4, the same parts or similar parts are given the same reference numerals.

[For production]

The polyimide film used for the gate insulating film 3 can be formed by a spin code method. The insulating film formed by this spin code method has the advantage of having extremely few pinholes in the film.

On the other hand, many polyimides with low coefficients of thermal expansion have recently appeared. Therefore, the active semiconductor layer 4 in contact with the polyimide film
The coefficient of thermal expansion of the inorganic semiconductor layer such as the a-Si layer that constitutes the
The coefficient of thermal expansion of the gate insulating film 3 is 4 x 10-1 to 4
A polyimide film of 10-b ('K-1) can be used.

Since the difference in coefficient of thermal expansion between the two can be reduced in this way, there is no risk of cranking of the polyimide film due to thermal expansion or contraction.

Furthermore, the polyimide film can have a multilayer structure, and in this case, even if pinholes occur in each polyimide film in rare cases, the probability that the pinholes in each layer will connect with each other is extremely low.

Therefore, a pinhole-free gate insulating film can be obtained.

As described above, the present invention can eliminate pinholes in the gate insulating film 3, thereby eliminating short-circuit defects between the gate and source/drain of TPT, and increasing the manufacturing yield of TF.
A T matrix can be realized. Further, according to the present invention, since the insulating film is formed by the spin code method, mass production becomes easy.

〔Example〕

An embodiment of the present invention is shown in FIGS. 2A and 2B below.

and FIG. 2C (al~01). For convenience of explanation, FIG. 2A, FIG. 2B, and FIG. )
-TJ) and Fig. 2C (al) - (J) are main part sectional views showing the section taken along the line B-B and the section taken along the line CC of Fig. 2A (al-01), respectively.

[Figure 2 (see al) A film with a thickness of approximately 8 mm is placed on a glass substrate l as a transparent insulating substrate.
After forming the gate electrode G and the scan path line 2 made of a 0 nm Cr (chromium) film, for example, a polyimide PIQ-L100 manufactured by Hitachi Chemical Co., Ltd.
After coating to a thickness of nm and final curing at 400°C,
On top of that, apply the above polyimide pHll~L100 at approximately 15%.
It is coated to a thickness of 0 nm and final cured at 400° C. to form a polyimide film 3 having a two-layer structure.

[See Figure 2 fbl] Next, using chemical vapor deposition (P-CVD), the film was deposited to a thickness of approximately IQ.
nm 5tN (silicon nitride) film4. Thickness approximately 1100n
a-3i (amorphous silicon) film 5. Thickness approx. 14
A 0 nm Stow (silicon dioxide) film 6 is continuously formed. When producing each of these thin films, 5iN4 (silane)/NH, (ammonia) was used as the generated gas, respectively.
r s I N4.

5iHa/N! O (nitrous oxide) can be used.

[See Figure 2 (C)] Next, a photoresist manufactured by Microposit Co., Ltd., for example, is applied on top of these. IP-1400 is applied to form a resist film 7.

[See FIG. 2+d+] Exposure light is applied to the resist film 7 from the back side of the glass substrate 1 using the gate electrode G and the scan path line 2 as a mask, and exposure is performed by a self-alignment method. 7' in the figure indicates an unexposed area.

[See Figure 2 (e)] By developing this, the exposed areas are dissolved.

The resist film 8 is removed and consists only of the unexposed portion 7'.
remains.

[See FIG. 2 (fll) Using the resist film 8 as a mask, the exposed portion of the SiO film 6 is removed by etching.
A SiO□ film 6 aligned with the scan path line 2 is obtained.

[Figure 2 (see gl)] On top of this, at a substrate temperature of about 120°C, n”a was formed as a contact layer by the P-CVD method using SiH mixed with 0.5% PH3 (phosphine) as the generated gas. −
A St layer 9 is formed to a thickness of approximately 3 Q nm, and a Ti (titanium) film 10 is further deposited thereon to a thickness of approximately ]00 nm by vacuum evaporation.
Form to a thickness of .

[FIG. 2 (see hl)] Next, the resist film 8 is removed, and at the same time, the Ti film 1O and the n''a-3i layer 9 adhering to the upper layer are lifted off.

[See Figure 2 (1)] Next, Ti in other regions except the region where the TPT element will be formed is
The film IQ, the n''a-5i layer 9. and the a-Si layer 5 are removed by dry etching using CF4 (Freon) using a resist film (not shown) as a mask.

As a result, the drain electrode and source bridge S are defined, and the TPT is completed.

[See Figure 2 U)] A transparent conductive film made of a transparent quaternary material such as ITO is formed on this, and unnecessary parts of this are removed to form the data bus line 11 and pixel electrode E. An example TPT matrix is obtained.

Typical characteristics of the TPT manufactured as described above are shown in Figure 3 (al).
This is a diagram showing PT characteristics, and is provided for comparison with this example. In both figures, the horizontal axis is the gate voltage Vg (unit: ■), and the vertical axis is the drain current 1d (unit: A).

As seen in both figures, the TPT characteristics of this embodiment are comparable to those of the conventional structure, and have no hysteresis.

Furthermore, since the gate insulating film 3 of this embodiment is formed of a two-layer polyimide film, pinholes are less likely to occur. Even if a pinhole occurs, the pinhole in the upper layer and the lower layer will be formed at the same location, and there is a very low risk that the two will connect, so this pinhole will hardly become a pinhole in the gate insulating film 3. Therefore, TPT of this example
is pinhole free. However, in order to stack polyimide films in multiple layers of two or three or more layers in this manner and to make the film pinhole-free, it is necessary to cure the lower polyimide layer and then apply the upper polyimide layer.

Furthermore, the polyimide used in this example has a coefficient of thermal expansion of 4X10-b to 4X10-'('K-
1], the aSi forming the active semiconductor layer
The difference in thermal expansion coefficient from layer 5 is small, and there is no risk of cranking due to temperature changes.

Note that in the embodiment, the gate insulating film 3 and aS i q
Although the SiN film 4 was interposed between the polyimide film 5 and the polyimide film 5, this was done in consideration of the interface characteristics with the a-8i layer 5, which is an active semiconductor layer. Rather than depositing Si on the polyimide film as in this example,
A better quality aSi layer can be obtained by forming the N film 4 and depositing a-stls on it. In this way S
If the P-CVD method is used in the step of laminating the iN film and the a-3i layer, it is sufficient to simply switch the generated gas, and the manufacturing process will not be complicated.

〔Effect of the invention〕

According to the present invention, it is possible to eliminate pinholes that exist in P-CVD insulating films, so it is possible to eliminate short-circuit defects between the gate and source/drain of TPT, and the manufacturing yield of TPT can be improved. It can be improved.

Further, according to the present invention, since the insulating film is formed by the spin code method, mass production becomes easy.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the configuration of the present invention; Fig. 2A, Fig. 2B, and Fig. 2C (a) to (j) are explanatory diagrams of embodiments of the present invention; Fig. 3 (a) and (b) are FIG. 4, which is a diagram explaining the effects of the present invention, is a diagram explaining the structure of a conventional TPT. In the figure, ■ is an insulating substrate (glass substrate). 2 is the scan path line, 3 is the gate insulating film (polyimide film), 4 is the SiN film, 5 is the active semiconductor layer (a-8i layer), 6 is the protective film (Sio□ film), is the data bus line, and G is the data bus line. The gate electrode is shown. D codrain electric winter lion 4q crescent groove pa 2' customer 1all'' 11112 8th 1st
Figure 1 Glass substrate 3: polyimide film Figure 2A Figure 2B Present invention - Example explanatory diagram Figure 2 Figure 2C Figure '5v-4 (CI) → Gate voltage vgrv)

Claims (4)

[Claims] (1) In a transistor configuration including an active semiconductor layer (5), a gate electrode (G), and a gate insulating film (3) interposed between the active semiconductor layer and the gate electrode, the gate insulating film (3) However, the coefficient of thermal expansion is 4×10^-^6~4
A thin film transistor characterized by being made of a polyimide film of ×10^-^5 [^゜K^-^1]. (2) The thin film transistor according to claim 1, characterized in that a silicon nitride film (4) is interposed between the active semiconductor layer (5) and the gate insulating film (3) made of a polyimide film. (3) When manufacturing a thin film transistor having an active semiconductor layer (5), a gate electrode (G), and a gate insulating film (3) interposed between the active semiconductor layer and the gate electrode, an insulating substrate (1 ) forming a gate electrode (G) having a predetermined pattern on the insulating substrate (1) including the gate electrode, and applying polyimide on the insulating substrate (1) including the gate electrode, and then curing the applied polyimide at a predetermined temperature. The method includes the steps of repeating a series of steps to form a gate electrode (3) made of at least one polyimide film, and forming an active semiconductor layer (5) on the gate insulating film (3). Characteristic method for manufacturing thin film transistors. (4) An active semiconductor layer (5) on the gate insulating film (3)
4. The method according to claim 3, further comprising the step of forming an inorganic insulating film using a chemical vapor deposition method prior to forming the semiconductor layer, and then continuously forming an active semiconductor layer by switching the generated gas. A method for manufacturing thin film transistors.