JPH0227730U - - Google Patents
Info
- Publication number
- JPH0227730U JPH0227730U JP10575888U JP10575888U JPH0227730U JP H0227730 U JPH0227730 U JP H0227730U JP 10575888 U JP10575888 U JP 10575888U JP 10575888 U JP10575888 U JP 10575888U JP H0227730 U JPH0227730 U JP H0227730U
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor element
- integrated circuit
- circuit device
- hybrid integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/541—Dispositions of bond wires
- H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10575888U JPH0227730U (en:Method) | 1988-08-09 | 1988-08-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10575888U JPH0227730U (en:Method) | 1988-08-09 | 1988-08-09 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0227730U true JPH0227730U (en:Method) | 1990-02-22 |
Family
ID=31338663
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10575888U Pending JPH0227730U (en:Method) | 1988-08-09 | 1988-08-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0227730U (en:Method) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60931B2 (ja) * | 1979-06-13 | 1985-01-11 | 株式会社東芝 | 異方性磁石の製造方法及び製造装置 |
-
1988
- 1988-08-09 JP JP10575888U patent/JPH0227730U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60931B2 (ja) * | 1979-06-13 | 1985-01-11 | 株式会社東芝 | 異方性磁石の製造方法及び製造装置 |