JPH02275647A - Wire bonding method of integrated circuit - Google Patents

Wire bonding method of integrated circuit

Info

Publication number
JPH02275647A
JPH02275647A JP1097956A JP9795689A JPH02275647A JP H02275647 A JPH02275647 A JP H02275647A JP 1097956 A JP1097956 A JP 1097956A JP 9795689 A JP9795689 A JP 9795689A JP H02275647 A JPH02275647 A JP H02275647A
Authority
JP
Japan
Prior art keywords
fingers
semiconductor chip
film
integrated circuit
wire bonding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1097956A
Other languages
Japanese (ja)
Inventor
Hirotoshi Mine
峰　浩利
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1097956A priority Critical patent/JPH02275647A/en
Publication of JPH02275647A publication Critical patent/JPH02275647A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To obtain stabler connection by connecting the electrode pad of a semiconductor chip and a finger and bonding the finger and the lead of a base by a wire. CONSTITUTION:A semiconductor chip 1 is placed onto a film to which fingers 2 are formed, the fingers 2 and electrode pads are conformed, and the semiconductor chip 1 is loaded onto the film while each finger 2 and the electrode pads corresponding to the fingers are connected through heating. Bases are arranged around the film, and the fingers 2 and the leads of the stitch sections 4 of the bases corresponding to the fingers are bonded by wires 3. Accordingly, the fingers and the leads can be connected stably.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路のワイヤボンディング方法に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a method for wire bonding integrated circuits.

〔従来の技術〕[Conventional technology]

従来、集積回路が形成された半導体チップ以降の配線接
続には、ワイヤボンディング法、テープキャリヤボンデ
ィング法及びフリップチップボンディング法などの方法
のうちいずれかの方法を用いてボンディングを行ってい
た６ 第２図は従来のワイヤボンディング方法を用いてワイヤ
でステッチ部と半導体チップとをボンディングを行った
状態を示す平面図である。このワイヤボンディング方法
は、ワイヤボンディング装置を利用して、半導体チップ
１の電極パッドとベース上のステッチ部４のリードとを
ワイヤで接続する方法である。Conventionally, wiring connections after a semiconductor chip on which an integrated circuit is formed have been bonded using one of the following methods: wire bonding, tape carrier bonding, and flip-chip bonding. The figure is a plan view showing a state in which a stitch portion and a semiconductor chip are bonded with a wire using a conventional wire bonding method. This wire bonding method is a method of connecting the electrode pads of the semiconductor chip 1 and the leads of the stitched portion 4 on the base with wires using a wire bonding device.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、近年、集積回路は素子寸法縮小化、多ピ
ン化の方向に向っている。このため、集積回路のビン数
が増加し、半導体チップの電極パッドの間隔が狭くなり
安定したボンディング結果が得られないという欠点があ
る。このボンディング結果と安定させるために、その間
隔がある程度の大きさが必要であるが、半導体チップサ
イズが大きくなってしまう欠点かある。However, in recent years, integrated circuits have been moving toward smaller element sizes and increased pin count. As a result, the number of bins in the integrated circuit increases, and the spacing between the electrode pads of the semiconductor chip becomes narrower, making it difficult to obtain stable bonding results. In order to stabilize this bonding result, the spacing needs to be of a certain size, but this has the disadvantage that the semiconductor chip size increases.

本発明の目的は、かかる問題を解決するワイヤボンディ
ング方法を提供することにある。An object of the present invention is to provide a wire bonding method that solves this problem.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の集積回路のワイヤボンディング方法は、集積回
路が形成された半導体チップの周囲にｍｆ記半導体チッ
プの電極パッドに対応するフィンガーが形成されたフィ
ルムを配置し、前記電極パッドと前記フィンガーを接続
するとともに前記半導体チップを前記フィルム上に搭載
する工程と、この工程の後に、前記フィルムの周囲にリ
ードが形成されたベースを配置するとともに前記フィン
ガーと前記リードとを接続する工程とを含んで構成され
る。In the integrated circuit wire bonding method of the present invention, a film in which fingers corresponding to electrode pads of the mf semiconductor chip are formed is placed around a semiconductor chip on which an integrated circuit is formed, and the electrode pads and the fingers are connected. and mounting the semiconductor chip on the film, and after this step, arranging a base on which leads are formed around the film and connecting the fingers and the leads. be done.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例を説明するための半導体チッ
プの平面図である。この方法は、まず、この集積回路の
構造を、半導体デツプ１とベースのステッチ部４との間
に、フィンガー２が形成されたフィルムを設けたことで
ある。またこの接続方法は、テープキャリヤボンディン
グ方法によりフィンガー２と電極パッドとを接続し、そ
の後に、このフィンガー２とベースのステッチ部のリー
ドとを接続することである。FIG. 1 is a plan view of a semiconductor chip for explaining one embodiment of the present invention. In this method, the integrated circuit is first structured by providing a film on which fingers 2 are formed between the semiconductor depth 1 and the stitched portion 4 of the base. Further, this connection method is to connect the finger 2 and the electrode pad by a tape carrier bonding method, and then connect the finger 2 and the lead of the stitched portion of the base.

次に、この方法を工程順に説明する。まず、半導体チッ
プ１を、フィンガー２が形成されたフィルム上に乗せ、
フィンガー２と電極パッドを合わせ、加熱させて、半導
体チップ１をフィルムに搭載させると同時に各フィンガ
ー２とこれに対応する電極パッドを接続させる。次に、
従来と同様に、フィルムの周囲にベースを配置し、フィ
ンガー２とこれに対応するベースのステッチ部４のリー
ドとをワイヤ３で接続することである。なお、フィンガ
ー２の一端側の間隔は、半導体チップ１の電極パッドの
間隔と同じにし、フィンガー２の他端側の間隔は、ベー
スのステッチ部のリード間隔と同じにすることである。Next, this method will be explained step by step. First, a semiconductor chip 1 is placed on a film on which fingers 2 are formed,
The fingers 2 and the electrode pads are brought together and heated to mount the semiconductor chip 1 on the film and connect each finger 2 to the corresponding electrode pad at the same time. next,
As in the prior art, the base is arranged around the film, and the fingers 2 and the corresponding leads of the stitched portions 4 of the base are connected by wires 3. Note that the spacing at one end of the fingers 2 is the same as the spacing between the electrode pads of the semiconductor chip 1, and the spacing at the other end of the fingers 2 is the same as the lead spacing of the stitched portion of the base.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、フィンガーが形成された
フィルムを半導体チップとベースとの間に配置させ、半
導体チップの電極パッドとフィンガーを接続した後に、
フィンカーとベースのリードとをワイヤで接続すること
によって、互いに間隔の広いフィンガーとベースのリー
ドとをワイヤーで接続出来るので、より安定した接続方
法が得られるという効果がある。As explained above, in the present invention, after placing a film on which fingers are formed between a semiconductor chip and a base, and connecting the electrode pads of the semiconductor chip and the fingers,
By connecting the fin car and the lead of the base with a wire, the fingers that are widely spaced from each other and the lead of the base can be connected with the wire, which has the effect of providing a more stable connection method.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例を説明するための半導体チッ
プの平面図、第２図は従来のワイヤボンディング法を用
いてワイヤでステッチ部と半導体チップとをボンディン
グを行った状態を示す平面図である。 １・・・半導体チップ、２・・・フィンカー、３・・・
ワイヤ、４・・・ステッチ部。 代理人　弁理士　　内　原　　晋FIG. 1 is a plan view of a semiconductor chip for explaining an embodiment of the present invention, and FIG. 2 is a plan view showing a state in which a stitched portion and a semiconductor chip are bonded with a wire using a conventional wire bonding method. It is a diagram. 1...Semiconductor chip, 2...Finker, 3...
Wire, 4...stitch part. Agent Patent Attorney Susumu Uchihara

Claims (1)

【特許請求の範囲】[Claims] 集積回路が形成された半導体チップの周囲に前記半導体
チップの電極パッドに対応するフィンガーが形成された
フィルムを配置し、前記電極パッドと前記フィンガーを
接続するとともに前記半導体チップを前記フィルム上に
搭載する工程と、この工程の後に、前記フィルムの周囲
にリードが形成されたベースを配置するとともに前記フ
ィンガーと前記リードとを接続する工程とを含んでいる
ことを特徴とする集積回路のワイヤボンディング方法。A film on which fingers corresponding to electrode pads of the semiconductor chip are formed is arranged around a semiconductor chip on which an integrated circuit is formed, and the electrode pads and the fingers are connected and the semiconductor chip is mounted on the film. A method for wire bonding an integrated circuit, the method comprising the steps of: arranging a base on which leads are formed around the film and connecting the fingers and the leads after this step.
JP1097956A 1989-04-17 1989-04-17 Wire bonding method of integrated circuit Pending JPH02275647A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1097956A JPH02275647A (en) 1989-04-17 1989-04-17 Wire bonding method of integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1097956A JPH02275647A (en) 1989-04-17 1989-04-17 Wire bonding method of integrated circuit

Publications (1)

Publication Number Publication Date
JPH02275647A true JPH02275647A (en) 1990-11-09

Family

ID=14206120

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1097956A Pending JPH02275647A (en) 1989-04-17 1989-04-17 Wire bonding method of integrated circuit

Country Status (1)

Country Link
JP (1) JPH02275647A (en)

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