JPH02273376A - Delay control circuit - Google Patents

Abstract

PURPOSE:To obtain an output signal which undergone the continuous delay control over a wide delay range by applying the continuous delay control to an input signal with a delay control signal and simultaneously switching alternatively the input signal with a synchronized selection control signal. CONSTITUTION:When the control voltage is changed from the GND voltage through the voltage Vcc, a delay control means 5 outputs the delay control signals to the delaying means 1 and 2. Then each delay value of both means 1 and 2 has a linear change so that the delay value is set at the minimum value C with the GND voltage of the control voltage and set at the maximum value D with the Vcc/2 voltage respectively. Then an output signal that undergone the delay control covering the value C through the value D via the means 5 is outputted while the control voltage is changed from the GND voltage through the Vcc/2 voltage, i.e., as long as the means 1 is connected to a selection means 3 via a contact point (a) switched by a selection control signal. On the other hand, an output signal covering the minimum value 2C through the maximum value 2D is outputted while both means 2 and 3 are connected to each other via a contact point (b).

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay control circuit used in video tape recorders and the like.

[Conventional technology]

As a first conventional example of this type of delay control circuit, one constructed as shown in the block diagram of FIG. 7 is known. This delay control circuit includes a plurality of delay means 10, 11 such as a second-order all-bus filter that delays and outputs an input signal from the outside, and each delay means 10, 11 are connected in multiple stages. The output signal from is 2 human power 1
A selection means 12 called an output device selectively switches the output and outputs the output. Therefore,
The output end of each delay means 10.11 and the input end of the selection means 12 are connected to each other via contacts a and b arranged on this selection means 12, and these contacts a and b are connected to the selection control means. The switching operation is performed by a selection control signal output from 13. Note that this selection control signal is outputted from the selection control means 13 in response to an external control voltage. Further, delay means 1011
Each of these delays the input signal by a preset amount of delay. For example, the delay means 10 delays the input signal by a preset delay amount.
Furthermore, the delay means 11 is configured to realize delay control of a delay amount of B.

Therefore, in this delay control circuit, the selection control means 1
If the delay means 10 and the selection means 12 are connected through the contact a switched by the selection control signal from 3, the output terminal of the selection means 12 will control the delay by the delay amount A with respect to the input signal. The output signal is output. In addition, when the delay means 11 and the selection means 12 are connected through a contact, the delay amount A+B with respect to the input signal.
The output signal whose delay has been controlled by the amount of time is outputted from the output terminal of the selection means 12.

On the other hand, as a second conventional example of such a delay control circuit,
There is one as shown in the block diagram of FIG. This delay control circuit is constructed by connecting a plurality of delay means 15.16 consisting of variable mutual conductance filters in multiple stages, and the delay amount in each of the delay means 15.16 varies from the minimum value C to the maximum value. It is designed to be able to change continuously within a range of . A delay control means 17 is connected to these delay means 15 and 16. The delay control means 17 outputs a delay control signal that changes the amount of delay based on an external control voltage.

Therefore, in this delay control circuit, the delay control means 1
7, the delay amount of each of the delay means 15 and 16 is controlled simultaneously in the range from C to D, and the output terminal of the delay means 16 outputs the minimum value CX2 with respect to the input signal.
An output signal whose delay is controlled over a range from (2·C) to the maximum value Dx2 (2·D) is output.

[Problem to be solved by the invention]

By the way, in the delay control circuit according to the first conventional example described above, the output signal is delayed by the delay amount set in advance in the delay means 10.11, that is, by the delay amount that is discrete from each other such as A or A+B. However, it was not possible to obtain an output signal whose delay was continuously controlled with respect to the input signal.

On the other hand, in the delay control circuit according to the second conventional example, the delay means 1
5.16 Based on the minimum value C and maximum value of the delay amount set respectively, double the delay amount, that is, 2・C
An output signal whose delay is continuously controlled over a range of 2·D is obtained. However, it has not been possible to obtain an output signal whose delay is continuously controlled over a wider range than this delay amount range, for example, from the minimum value C to the maximum value 2·D.

The present invention was devised in view of the current situation, and an object of the present invention is to provide a delay control circuit that can obtain an output signal whose delay is continuously controlled over a wider range of delay amounts.

[Means to solve the problem]

A delay control circuit according to the present invention includes a plurality of delay means that delay an input signal based on a delay control signal, and selectively switches and outputs an output signal of each delay means connected in multiple stages based on a selection control signal. The present invention is characterized by comprising a selection means, a delay control means for outputting the delay control signal based on the control voltage, and a selection control means for outputting the selection control signal based on the control voltage.

[Effect]

According to the above configuration, the input signal is continuously delayed in each of the delay means connected in multiple stages based on the delay control signal from the delay control means, and the output signal from each delay means is outputted from the selection control means. The signal is selectively switched and output based on the selection control signal. Therefore, if the delay control signal output based on the control voltage and the selection control signal are synchronized, the amount of delay in each delay means will change continuously in the range from the minimum value C to the maximum value C. Therefore, the output terminal of the selection means outputs an output signal that is continuously delayed and controlled over the range from the minimum value C to the maximum value 2.D with respect to the input signal.

〔Example〕 Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram showing a schematic configuration of a delay control circuit according to the present invention, and each of FIGS. 2 to 6 is an explanatory diagram showing a delay control state.

This delay control circuit is constructed by connecting delay means 1.2 in multiple stages, each consisting of a mutual conductance variable filter that delays and outputs an input signal from the outside. The output signal is selectively switched by a selection means 3, which is called a two-manpower one-output device, and then output. The output end of each delay means 1.2 and the input end of the selection means 3 are connected to each other via contacts a and b provided on the selection means 3, and these contacts a and b are The switching operation is performed by a selection control signal outputted from the selection control means 4. Note that this selection control signal is outputted from the selection control means 4 based on an external control voltage, and the selection control means 4 outputs the control voltage from the G
1/2Vcc voltage (+2.5V) from ND voltage (OV)
The signal connecting the output end of the delay means 1 and the input end of the selection means 3 via the contact a until then is connected, and the contact is closed between the 1/2 cc voltage and the cc voltage (+5V). A signal connecting the delay means 2 and the selection means 3 is outputted through the delay means 2 and the selection means 3.

In addition, these delay means 1. The amount of delay in each of the delay means 1 and 2 is set to be able to change continuously in the range from, for example, the minimum value C to the maximum (lILD), and each delay means 1 and 2 has a delay amount based on an external control voltage. Delay control means 5 for outputting a delay control signal for changing the amount
is connected. From this delay control means 5, the control voltage changes from the GND voltage to ■. , a signal for continuously controlling the delay amount of each delay means 1 and 2 is output.

That is, as shown in FIG. 2, the delay amount by one of the delay means 1 and 2 is the minimum value C when the control voltage is the GND voltage, and is 1/2. , the control voltage is changed linearly so that it reaches the maximum value, and then the control voltage is changed to 1 /
The setting is such that when the lightning voltage exceeds 2 V cc, the voltage is changed linearly from the minimum value C to the maximum value again. Therefore, as shown in FIG. 3, the delay amount due to both delay means connected in multiple stages] and 2 is the minimum value Cx2 (2・C) when the control voltage is the GND voltage, and 1/2
After the V ec voltage is linearly changed to the maximum value DX2 (2・D), the control voltage is changed to 1/2.
When the Vcc lightning voltage is exceeded, the voltage is again changed linearly from the minimum value 2·C to the maximum value 2·D.

Therefore, in this delay control circuit, the control voltage is
D voltage (OV) to 1/2Vcc voltage (+2.5V), that is, delay means 1 through contact a switched by the selection control signal from selection control means 4.
While the output terminal of the selection means 3 is connected to the input terminal of the selection means 3, an output signal whose delay is controlled over the range from the minimum value C to the maximum value is outputted from the output terminal of the selection means 3 with respect to the input signal. That will happen. And the control voltage is 1/2■o
, from the voltage (+2.5V) to the VCC voltage (+5V), that is, the delay means 2 and the selection means 3 are connected via a contact which is switched by a selection control signal from the selection control means 4. During this period, the output terminal of the selection means 3 changes the input signal from the minimum value 2・C to the maximum value 2・D.
An output signal whose delay is controlled over a range of is output.

Therefore, the minimum value C of the delay amount in each delay means 1.2 is equal to half of the maximum value, that is, C=1/
If it is set in advance to be 2D, the control voltage will be 1 from the output terminal of the selection means 3, as shown in FIG.
/ 2 V cc lightning voltage as the breaking point, and
An output signal whose delay amount is continuously controlled over a range from the minimum value C to the maximum value 2.D is output.

At this time, the minimum value C of the delay amount in each delay means 1 and 2 is smaller than half of the maximum value (c<1/2
D) If set, as shown in FIG. 5, the maximum delay amount of delay means 1 and the minimum delay amount 2・C of delay means 2 are mutually different at the time when the control voltage becomes 1/2 VC6 voltage. It will be duplicated. Furthermore, if the minimum value C of the delay amount in each delay means 1.2 is set larger than half of the maximum value (C>1/2D), the control voltage will change as shown in FIG. When the voltage reaches 1/2 VC6, the maximum delay amount by the delay means 1 and the minimum delay amount 2.multidot.C by the delay means 2 become separated from each other. Therefore, in the present invention, it is necessary to set the minimum value C of the delay amount in each delay means 1.2 to be equal to or smaller than half the maximum value (C≦1/2D).

Incidentally, in the above description, the delay control circuit according to the present invention is constructed by two delay means 1.2, but the scope of application of the present invention is not limited to this, and for example, three delay means 1.2 are used. It goes without saying that a delay control circuit may be constructed using the above-mentioned delay means.

〔Effect of the invention〕

As explained above, according to the present invention, the input signal in each of the delay means connected in multiple stages is continuously delayed based on the delay control signal from the delay control means, and the output from each delay means is The signals are selectively switched and output based on the selection control signal from the selection control means. Therefore, if the delay control signal output based on the control voltage and the selection control signal are synchronized,
The amount of delay in each delay means changes continuously in the range from its minimum value to its maximum value.

As a result, according to the delay control circuit according to the present invention, the delay amount is continuously controlled over a wide range from the minimum value of the delay amount set by a single delay means to the maximum value of the delay amount set by a plurality of delay means. A delay-controlled output signal will be output.

[Brief explanation of drawings]

1 to 6 relate to the present invention, in which FIG. 1 is a block diagram showing a schematic configuration of a delay control circuit, FIG. 2 is an explanatory diagram showing the amount of delay in a single delay means, and FIG. is an explanatory diagram showing the amount of delay in two delay means, and each of FIGS. 4 to 6 is an explanatory diagram showing the amount of delay of the output signal from the selection means. In addition, FIGS. 7 and 8 relate to the conventional example, and FIG.
FIG. 8 is a block diagram showing a delay control circuit as a conventional example. FIG. 8 is a block diagram showing a delay control circuit as a second conventional example. Reference numerals 1 and 2 in the figure are delay means, 3 is selection means, 4 is selection control means, and 5 is delay control means. W Encounter Summer Festival q111 Cao's message l Hong to every tomb q ■ l Liu Fan &=> r- to Tian Cao's letter

Claims (1)

[Claims] (1) A plurality of delay means for delaying an input signal based on a delay control signal, a selection means for selectively switching and outputting an output signal of each delay means connected in multiple stages based on a selection control signal, and a control voltage. A delay control circuit comprising: delay control means for outputting the delay control signal based on the control voltage; and selection control means for outputting the selection control signal based on the control voltage.