JPH02272942A - High-speed data transmission system - Google Patents

High-speed data transmission system

Info

Publication number
JPH02272942A
JPH02272942A JP1093153A JP9315389A JPH02272942A JP H02272942 A JPH02272942 A JP H02272942A JP 1093153 A JP1093153 A JP 1093153A JP 9315389 A JP9315389 A JP 9315389A JP H02272942 A JPH02272942 A JP H02272942A
Authority
JP
Japan
Prior art keywords
data
speed data
parallel
bits
speed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1093153A
Other languages
Japanese (ja)
Other versions
JP2961743B2 (en
Inventor
Takashi Sakaguchi
尚 坂口
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP1093153A priority Critical patent/JP2961743B2/en
Publication of JPH02272942A publication Critical patent/JPH02272942A/en
Application granted granted Critical
Publication of JP2961743B2 publication Critical patent/JP2961743B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Communication Control (AREA)

Abstract

PURPOSE:To transfer high-speed data for a long distance by correcting phase deviation with low-speed data, for which the serial/parallel conversion of the high-speed data is executed, and afterwards, returning the data to the original high-speed data. CONSTITUTION:A serial/parallel converter 1, frame bit inserters 2-4, frame bit detectors 5-7, phase adjusters 8-10 and parallel/serial converter 11 are provided. In a transmission side, high-speed data 100 are converted to (n+1)-number of parallel data/(m) bit second [(n) and (m) are integral numbers] and a frame bit is inserted to an idle bit, which is allocated to the respective parallel data for each (n+1) bits, and sent. In a reception side, this frame bit is detected and the phase deviation of the respective parallel data is corrected. Afterwards, the data are returned to high-speed data 260. Thus, a transmission system can be obtained to be applied even when the transmission distance is long.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は高速データの伝送方式に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to a high-speed data transmission system.

〔従来の技術〕[Conventional technology]

従来、高速データを伝送する際、高速データを直/並列
変換して、伝送速度を低下させて伝送する方法がある。
Conventionally, when transmitting high-speed data, there is a method of serial/parallel conversion of the high-speed data to reduce the transmission speed.

〔発明が解決しようとする問題点〕・ ところで、上述のような伝送方式では、受信側で並/直
列変換して再び高速データに戻すには各並列データ間に
位相ずれが生じないようにしなければならず、このため
、伝送距離が短い場合にしか適用できないという問題点
がある。
[Problems to be solved by the invention]- By the way, in the above-mentioned transmission system, in order to perform parallel/serial conversion on the receiving side and return it to high-speed data, it is necessary to ensure that there is no phase shift between each parallel data. Therefore, there is a problem that it can only be applied when the transmission distance is short.

本発明の目的は伝送距離が長い場合にも適用できる伝送
方式を提供することにある。
An object of the present invention is to provide a transmission method that can be applied even when the transmission distance is long.

〔問題点を解決するための手段〕[Means for solving problems]

本発明では、nxm(n、mは正整数)ビット/秒の高
速データをmビット/秒の低速伝送路を用いて送信側か
ら受信側に送る際に用いられ、前記送信側で前記高速デ
ータを(n+1)個のmビット秒の並列データに変換す
る変換手段と、該各並列データに(n+1)ピント毎に
割り当てられた窒ビットにフレームビットを挿入して送
出する手段と、前記受信側で前記フレームビットを検出
して前記各並列データの位相ずれを補正する手段とを有
することを特徴とする高速データ伝送方式が得られる。
In the present invention, high-speed data of nxm (n, m are positive integers) bits/second is sent from a transmitting side to a receiving side using a low-speed transmission line of m bits/second, and the high-speed data is transmitted on the transmitting side. converting means for converting the data into (n+1) m-bit-second parallel data; means for inserting frame bits into bits allocated for each (n+1) focus in each of the parallel data and transmitting the data; and the receiving side. A high-speed data transmission method is obtained, comprising means for detecting the frame bits at and correcting a phase shift of each of the parallel data.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図を参照して、第2図に示す2×m(mは正整数)
ビット/秒(bpS)の高速データ100を直/並列変
換器1で3個の並列データ110゜120.130に直
/並列変換する。つまり、第2図に示す並列データ17
0,180及び190に変換され、これら並列データ1
70,180゜及び190のF−1,F−2,F−3の
位置には空ビットを割当て可能である。
2×m (m is a positive integer) shown in FIG. 2 with reference to FIG.
A serial/parallel converter 1 converts high-speed data 100 bits per second (bpS) into three pieces of parallel data 110°120.130. In other words, the parallel data 17 shown in FIG.
0, 180 and 190, these parallel data 1
Empty bits can be assigned to positions F-1, F-2, and F-3 at 70, 180 degrees, and 190 degrees.

この空ビットにはフレームビ・ント挿入器2,3及び4
によりそれぞれフレームビット140゜150、及び1
60が挿入される。そして、これら並列データはそれぞ
れ伝送路170’、180’及び190′に送り出され
る。受信側ではフレームビット検出器5,6.及び7で
各並列データのフレームビット位置を検出してこの検出
結果に基づいて位相調整器8,9.10によって位相の
そろった並列データ230,240.及び250にする
。そして、これら並列データ230,240゜及び25
0は並/直列変換器11により高速データ260に戻さ
れる。
This empty bit is filled with frame bit inserters 2, 3 and 4.
frame bits 140, 150, and 1, respectively.
60 is inserted. These parallel data are then sent to transmission lines 170', 180' and 190', respectively. On the receiving side, frame bit detectors 5, 6 . and 7 detect the frame bit position of each parallel data, and based on the detection result, phase adjusters 8, 9.10 adjust the parallel data 230, 240 . and 250. And these parallel data 230, 240° and 25
The 0 is returned to high speed data 260 by parallel/serial converter 11.

〔発明の効果〕〔Effect of the invention〕

以上説明したように2本発明では、高速データを直/並
列変換した低速の並列データ間の位相がずれを補正して
いるから元の高速データに戻すことができ、高速データ
を長距離の低速伝送路を用いて伝送することができると
いう効果がある。
As explained above, in the present invention, the phase shift between low-speed parallel data obtained by serial/parallel conversion of high-speed data is corrected, so it is possible to restore the original high-speed data, and convert high-speed data into long-distance low-speed data. This has the advantage that it can be transmitted using a transmission path.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示すブロック図。 第2図は本発明の一実施例を説明するだめのタイムチャ
ートである。 1・・・直/並列変換器、2,3.4・・・フレームビ
ット挿入器、5,6.7・・・フレームビット検出器。 8.9.10・・・位相調整器、11・・・並/直列変
換器。 第2図
FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a time chart for explaining one embodiment of the present invention. 1... Serial/parallel converter, 2, 3.4... Frame bit inserter, 5, 6.7... Frame bit detector. 8.9.10... Phase adjuster, 11... Parallel/serial converter. Figure 2

Claims (1)

【特許請求の範囲】[Claims] 1、n×m(n、mは正整数)ビット/秒の高速データ
をmビット/秒の低速伝送路を用いて送信側から受信側
に送る際に用いられ、前記送信側で前記高速データを(
n+1)個のmビット秒の並列データに変換して、該各
並列データに(n+1)ビット毎に割り当てられた空ビ
ットにフレームビットを挿入して送出し、前記受信側で
前記フレームビットを検出して前記各並列データの位相
ずれを補正するようにしたことを特徴とする高速データ
伝送方式。
1. Used when sending high-speed data of n×m (n, m are positive integers) bits/second from the transmitting side to the receiving side using a low-speed transmission line of m bits/second, and the high-speed data is transmitted on the sending side. of(
n+1) pieces of parallel data of m bits per second, frame bits are inserted into the empty bits allocated every (n+1) bits in each parallel data, and the frame bits are sent out, and the receiving side detects the frame bits. A high-speed data transmission system, characterized in that the phase shift of each of the parallel data is corrected.
JP1093153A 1989-04-14 1989-04-14 High-speed data transmission equipment Expired - Lifetime JP2961743B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1093153A JP2961743B2 (en) 1989-04-14 1989-04-14 High-speed data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1093153A JP2961743B2 (en) 1989-04-14 1989-04-14 High-speed data transmission equipment

Publications (2)

Publication Number Publication Date
JPH02272942A true JPH02272942A (en) 1990-11-07
JP2961743B2 JP2961743B2 (en) 1999-10-12

Family

ID=14074597

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1093153A Expired - Lifetime JP2961743B2 (en) 1989-04-14 1989-04-14 High-speed data transmission equipment

Country Status (1)

Country Link
JP (1) JP2961743B2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336192B1 (en) 1998-02-16 2002-01-01 Nippon Telegraph And Telephone Corporation Parallel redundancy encoding apparatus
US7706380B2 (en) 2004-07-07 2010-04-27 Mitsubishi Denki Kabushiki Kaisha Data transmission method, data transmission apparatus and data transmission system using this method
WO2010131428A1 (en) * 2009-05-14 2010-11-18 パナソニック株式会社 Communication cable

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6336192B1 (en) 1998-02-16 2002-01-01 Nippon Telegraph And Telephone Corporation Parallel redundancy encoding apparatus
US6557110B2 (en) 1998-02-16 2003-04-29 Nippon Telegraph And Telephone Corporation Channel-to-channel skew compensation apparatus
US7706380B2 (en) 2004-07-07 2010-04-27 Mitsubishi Denki Kabushiki Kaisha Data transmission method, data transmission apparatus and data transmission system using this method
WO2010131428A1 (en) * 2009-05-14 2010-11-18 パナソニック株式会社 Communication cable
JPWO2010131428A1 (en) * 2009-05-14 2012-11-01 パナソニック株式会社 communication cable

Also Published As

Publication number Publication date
JP2961743B2 (en) 1999-10-12

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