JPH02272613A - Counter - Google Patents

Abstract

PURPOSE:To speed up counting operation by means of simple constitution by providing the counter with a memory circuit for storing binary data obtained by adding N bits to a certain binary data and outputting data counted up by N bits in each data input. CONSTITUTION:Data obtained of adding '1' to an address signal to be binary data for specifying a data area in a rapid memory 12 are stored in a data table as count-up data. In the case of outputting data obtained by counting up input data ID to be prescribed data by '1', the input data ID are inputted to the address pins AP0 to APn of the memory as address signals and a reading signal 13 is activated, so that binary data counted out from the input data by '1' are outputted from data pins DP0 to DPn as output data OD. Consequently, the counter capable of high speed counting operation can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a counter using a high-speed memory element.

[Conventional technology]

A conventional high-speed counter is a look-ahead carry counter. As shown in Fig. 4, its internal configuration includes multiple logic gates and multiple Ds that latch and output human input data in synchronization with the rising edge of the counter clock signal.
type flip-flop (hereinafter abbreviated as D-F/F)
It is composed of In the figure, (1) is human data ID0 to ID input through AND gates (AI') to (A4).

A load signal that enables latching of (2) to (5) to D-F/F (Fl) to (F4) via OR gates (OI) to (04), each of the above input data ID0 to Ion-, (
2) - (5) are latched by the rise of the counter clock (11) input to D-F/F (Fl) - (F4), and the output data ODo - 0Dn-+ (7) -
(10) is output. Also, when the load signal (1) is made non-aquive, the latched output data ODo
~00n-I(7) ~(lO) is the counter clock (
11) is counted up every time the signal rises, and the output data OD0 to QDn-+ (7) to (10) are incremented by +1 and output. Note that (6) is the carry signal from the previous stage, and is the carry signal from the previous stage. -In the first place. −.

Carry signal for all stages ((:RYo)
~((:1IYn-2) is included.

Next, the operation will be explained. Input data■D0~IDn
-+ When counting up (2) to (5), first activate (L) D (1) to the load signal LO.
AND Kate (AI) ~ (8,) in which human data is input via the inverter (N1)
and input the data IDo ”=IDn-+ (2)
After determining ~(5), set (11) to counter clock CL.
launch. Then, the D F/F inside the counter
(F+) to (F4) are each AND gate (AI) to (A4
) and the human-powered data 10. ~10. .

(2) to (5) are latched, output data ODo to OD,
.

(7) - (16) input data as is ■Do - In,
.

Output (2) to (5). After the output data is determined, its inversion is transferred from the Q terminal of D -F/F (F, ) to (F4) to the next stage input carry signal CRYo'' (:RY, -+ (
6) through each inverter (N4) to (N6)
The count-up data is input to each of the AND gates (N,) to (N3) and is sent to the next counter clock (11).
) to be generated. After that, the rot signal is OA [1 (1)
When the counter clock CL is made non-active (High level) and the counter clock CL is turned on (11), the count-up data of the NAND gates (N1) to (N3) and A
ND gate (A5) ~ (AI2) OR gate (0
1) through (04) D -F/F (F,) ~ (F
4) and output data 00o"00.-+ (7
) to (16) are incremented by one count.

(Problem to be Solved by the Invention) Since the conventional counter is configured as described above, when counting up input data, it requires the operation of loading confirmed input data by inputting a load signal, and the operation of counting up manual data. This requires two cycles of count-up operation to output the data as output data, which limits the speed of the count operation.

Additionally, as the number of pids (number of digits) of human data increases and the number of counter stages increases, the carry signal from the previous counter also increases, which increases the number of gate inputs for performing logical AND.
There were problems such as the circuit becoming complicated.

This invention was made to solve the above-mentioned problems, and has an extremely simple configuration that allows the counter to be counted up in one cycle of time after the input data is determined, and does not require manual labor from the previous stage. The purpose is to obtain.

[Means to solve the problem]

In the counter according to the present invention, binary value data having a plurality of bits is input as an address signal, and in a data area corresponding to the address signal, binary value data obtained by adding N bits to the binary value data is stored as a data table. The device is equipped with a memory circuit for storing data, and is configured to read binary value data incremented by N bits as a count output every time binary value data is input.

[Effect]

In the memory circuit according to the present invention, when binary value data as an augend is input as an address signal, a binary value obtained by adding N bits to the binary value data is obtained from a data table specified by the address signal. Since the data is read and output as a counted up addition number, the counting operation can be performed at a speed equivalent to the access time of the memory circuit.

(Example) Hereinafter, an example of the present invention will be explained with reference to the drawings.
The figure shows a high-speed memory constituting the counter according to this embodiment. In the figure, (12) is a high-speed memory element, and address pins (AP, ) to (APo) have multiple bits of input data IDo as an address signal. “IDo(2)
〜(5) is manually input and the data pin (DPo)〜(op,
) has output data 00. as count-up data. ~
00n(7) to (lO) are output.

By activating (13) with the read signal READ of the high speed memory (12), count up data can be taken out. (14) is a write signal W for writing count up data to memory.
It is RITIE.

As shown in FIG. 2, the data area of the high speed memory (I2) has data obtained by adding 1 to the binary data address signal specifying the data area, for example, the address is ro-0.
If it is 002J, ro-00124 is stored in the data table as count-up data in the data area corresponding to the address. Therefore, when counting up and outputting the manual data ID, which is predetermined binary value data, by +1, input data 10 as an address signal to the address bins (APo) to (AP, , ) of the memory, and then output the read signal. When (13) is activated, the binary value data counted up by +1 from the input data is output as the output data OD at the data pins (opo) to (op,).
It is output from

Further, the number of output data bins and the number of input address bins of the memories may be different, or a plurality of memories may be used so that the number of input address bins and the number of output data bins are the same. Figure 3 shows 1 using 18 256 x 1 bit memories.
This is an example of an 8-bit counter, and the memory read time is 1
If it is 5 ns, data can be counted up in 15 ns.

In the above embodiment, the input data IDo to ID are set and the read signal is activated to output count-up data, but the count-up data 000 to O
Continuous count-up output is possible by returning Dn to the address pins AP0 to AP and activating the read signal with a time difference from the feedback timing.

(Effects of the Invention) As described above, according to the present invention, the augend consisting of binary value data is used as the address signal of the memory, and the data obtained by adding +1 to the address signal is stored in the data area of the memory. Therefore, the count-up data of the augend can be output only by reading the memory.
This has the advantage of providing a counter that can perform high-speed counting operations with an extremely simple circuit configuration.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of a counter according to an embodiment of the present invention;
FIG. 2 is a table diagram showing the relationship between memory addresses and data, FIG. 3 is a diagram showing an example of a counter using a plurality of memories, and FIG. 4 is a configuration diagram of a conventional counter. In the figure, (2) to (5) are input data IDo to ID
n, (7) to (8) are output data ODo to 00.
, (12) is a memory, and (13) is a read signal. In each figure, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Claims] A memory circuit is provided in which binary value data having a plurality of bits is input as an address signal, and in a data area corresponding to the address signal, binary value data obtained by adding N bits to the binary value data is stored as a data table. A counter characterized in that for each binary data numerical value input, binary numerical data incremented by N bits is read out as a count output.