JPH02271712A - Comparison circuit - Google Patents

Abstract

PURPOSE:To extend an input voltage effective range up to fully the power voltage range by providing two comparators whose input voltage effective range differs from each other and switching an output voltage of the comparators in response to the level of the input voltage. CONSTITUTION:A level detection circuit 2 compares a noninverting input voltage VIN with a reference voltage between an effective lower limit input voltage VL and an effective lower limit input voltage VH. The circuit outputs a detection signal VDT at a high level when the voltage VIN is lower than an intermediate voltage VM and the detection signal VDT at a low level when the voltage VIN is higher than the intermediate voltage VM. Then an output voltage V01 of a 1st comparator 1A is selected by the signal VDT when the voltage VIN is lower than the voltage Vw and outputted and an output voltage V02, of a 1st comparator 1B is selected by the signal VDT when the voltage VIN is higher than the voltage VM and outputted. Thus, the input voltage effective range of the comparator circuits is extended up to fully the power voltage range from a low power level VSS to a high power level VDD and the stable operation is obtained within the range.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a comparison circuit, and more particularly to a comparison circuit constructed of a CM□S semiconductor integrated circuit, built into a microcomputer, etc., and operated with a single power supply.

[Conventional technology]

A conventional technique will be explained with reference to the drawings.

FIG. 4 (a>, (b) shows the first comparison circuit of the conventional comparison circuit, respectively.
and FIG. 6 is a circuit diagram showing a second example.

These comparison circuits gate the output voltage ■. A common-mode voltage input terminal T to which the common-mode input voltage VIN that is in phase with the common-mode input voltage VIN is input.
A first N-channel (or P-channel) MOS type transistor Q1 (or Qll) connected to IN and a gate connected to an output voltage ■. The reference voltage input terminal TREF is connected to the reference voltage input terminal TREF which inputs the reference voltage VREF having the opposite phase to an N-channel (or P-channel) MOS type second transistor Q2 (or Q12) with The drains are connected to the first and second transistors Ql, Q2 (Qll.

N-channel (or P-channel) MOS type third transistor Q3 (or Q13) of a constant current source that is connected to the source of Q12) and inputs a predetermined voltage to the gate, and the source is connected to the high potential side (or low potential side). ) is connected to the power supply terminal (VDD (or Vss)) of the P-channel (or N-channel) MOS type fourth transistor Q4 ( or Q14) and the power supply terminal (VDD (or VSS)) with the source on the high potential side (or low potential side)
and connect the gate to the third transistor Q3 (Q13
), and a P-channel (or N-channel) MOS type fifth transistor Q5 (or Q15) whose drain is connected to the output terminal To and the train of the second transistor Q2 (Q12). Type commercial
It has an O8 differential amplifier configuration.

Next, the operation of these comparison circuits will be explained.

FIG. 5 is a current/voltage characteristic diagram of P-channel and N-channel transistors for explaining the operation of the comparison circuit shown in FIG. 4(a).

First, analog common-mode input voltage VIN and reference voltage VI
The operating point of the comparator circuit when F is in the relationship V I N = V REF is the current of the N-channel transistor.
It is set at point A, which is the intersection of the voltage characteristic curve CN2 and the current/voltage characteristic curve CP2 of the P-channel transistor.

Now, when the relationship is V IN > V FLep,
The potential at node N1 becomes a low level, and the operating point shifts to point B. Further, when the relationship of V I N < V REF is established, the potential of the node N1 becomes high level and the operating point shifts to the 0 point.

The levels at each of these operating points are then amplified to obtain the final comparison result.

[Problem to be solved by the invention]

The conventional comparison circuit described above includes a first transistor Ql (or Q-th transistor) whose gate is connected to the common-mode voltage input terminal TIN, and a second transistor Q2 (or Q12) whose gate is connected to the reference voltage input terminal TREP. , these first and second transistors Q+ +, Q2 (or Q+t
, Q12) and the power supply terminal (Vss (or V
A third transistor Q3(DD)) connected between
or Q13), these first to third transistors Ql to Q3 (or Qll to Q
13) each have a threshold voltage, so if the common-mode input voltage V IN and reference voltage VREF are lower (or higher) than these threshold voltages, normal comparison operation will not be performed and correct comparison results will not be obtained. There is a drawback that the effective range for the input voltage, that is, the effective input voltage range is narrower than the power supply voltage range between the low potential side and the high potential side.

SUMMARY OF THE INVENTION An object of the present invention is to provide a comparator circuit that can widen the effective input voltage range to the power supply voltage range between the low potential side and the high potential side.

[Means to solve the problem]

The comparison circuit of the present invention is provided between power supply terminals on a low potential side and a high potential side, and has a first input terminal as a common-mode voltage input terminal for inputting a common-mode input voltage that is in phase with a first output voltage. A second input terminal is connected to a reference voltage input terminal into which a reference voltage having a reverse phase with respect to the first output voltage is input, and a low potential side power supply voltage is connected with respect to the in-phase input voltage and the reference voltage. It has a valid input voltage range between the valid upper limit input voltage,
a 0MO3 type first comparator that compares the common-mode input voltage with the reference voltage and outputs the first output voltage; and a first comparator provided between the low potential side and high potential side power supply terminals; connects an input terminal of the input terminal to the common mode voltage input terminal into which the common mode input voltage that is in phase with the second output voltage is input;
A second input terminal is connected to the reference voltage input terminal into which the reference voltage having a phase opposite to the second output voltage is input, and a high potential side power supply voltage is connected to the in-phase input voltage and the reference voltage. a 0MO8 type second comparator that has an input voltage effective range between the effective lower limit input voltage and compares the common-mode input voltage with the reference voltage and outputs the second output voltage;
a level detection circuit that outputs a detection signal that is at a first level when the common-mode input voltage is lower than an intermediate voltage between the effective upper limit input voltage and the effective lower limit input voltage and is at a second level when it is higher; and a switching circuit that outputs the first output voltage when the signal is at a first level and outputs the second output voltage when the signal is at a second level.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

The first comparator IA is constructed of a circuit similar to the comparison circuit shown in FIG. 4(b), and is provided between the power supply terminals on the low potential side and the high potential side, The second input terminal is connected to the common mode voltage input terminal TIN which inputs the common mode input voltage 'VIH which is in phase with the first output voltage V01, and the second input terminal is connected to the first output voltage V01.
The output voltage V. Connected to the reference voltage input terminal T RlF that inputs the reference voltage VREP with the opposite phase to 1, and outputs the low potential side power supply voltage (VSS) and the effective upper limit input voltage (VH) with respect to the in-phase input voltage VIN and the reference voltage VREP. has a valid input voltage range (VRl) between
is compared with the reference voltage VR, , and the first output voltage ■ol
Output.

The second comparator IB is constructed of a circuit similar to the comparison circuit shown in FIG. 4(a), and is provided between the power supply terminals on the low potential side and the high potential side, A reference voltage VRE is connected to a common-mode voltage input terminal TIN that inputs a common-mode input voltage VIN that is in phase with the second output voltage Vo2, and the second input terminal is connected to a reference voltage VRE that is in reverse phase with respect to the second output voltage V02.
The reference voltage input terminal TRP that inputs F is connected to F, and the high potential side power supply voltage (■DD) and effective lower limit input voltage (Vt) are connected to the common-mode input voltage V'B and the reference voltage ■RIl:F.
It has a valid input voltage range VR2 between , and outputs a second output voltage Vo2 by comparing the in-phase input voltage VIN with the reference voltages VRF and F.

The level detection circuit 2 includes a comparator 21 and two inverters 1
．． , I2, and outputs a detection signal VDT which becomes a high level when the common mode input voltage VIN is lower than an intermediate voltage VM between the effective upper limit input voltage (VH> and the effective lower limit input voltage (VL)) and becomes a low level when it is higher. do.

The switching circuit 3 includes two analog switches AS1AS2 and an inverter I3, and outputs the output voltage o1 of the first comparator IA when the detection signal V07° is high level, and outputs the output voltage o1 of the first comparator IA when the detection signal V07° is low level. Outputs the output voltage V(,2) of IB.

The amplifier 4 amplifies the output voltage of the switching circuit 3 and outputs the amplified voltage.

Next, the operation of this embodiment will be explained.

FIG. 2 is a characteristic diagram showing the effective input voltage ranges of the first and second comparators for explaining the operation of this embodiment.

As mentioned above, the first comparator IA has the same circuit configuration as the comparison circuit shown in FIG.
Third transistor Qll~Q! 3 each have a threshold voltage, so the threshold voltage of transistor Q+3 and transistor Q11 are determined from the high potential side power supply voltage VDD.
Normal comparison operation for the common mode input voltage V, N, and reference voltage VREF that is higher than the voltage obtained by adding the threshold voltage of 1Q12 (hereinafter referred to simply as the threshold voltage ■T). will no longer be carried out. Threshold voltage ■ from this high potential side power supply voltage VDD. The voltage obtained by subtracting is the effective upper limit input voltage (8) mentioned above.

Therefore, the effective input voltage range of this first comparator IA is:
The voltage ranges from the low voltage side power supply voltage ■ss to the effective upper limit input voltage VH.

As mentioned above, the second comparator IB has a circuit configuration similar to that of the comparison circuit shown in FIG. is the high potential side power supply voltage V. D to the effective lower limit input voltage ■L of (Vss+Vd).

In the level detection circuit 2, the level of the common-mode input voltage VIN is compared with a voltage exactly intermediate between the effective lower limit input voltage VL and the effective upper limit input voltage VH, that is, the intermediate voltage VM, as a reference, and the common-mode input voltage VIN is compared with the intermediate voltage VM. The detection signal V is high level when it is lower and low level when it is higher.
Output DT.

Then, by this detection signal VDT, the common mode input voltage VIN
is lower than the intermediate voltage vM, the output voltage V01 of the first comparator IA is selected, and when it is higher, the output voltage V01 of the second comparator IA is selected.
B's output voltage V. 2 is selected and output, the effective input voltage range of this comparison circuit is the low potential side power supply voltage VS
The power supply voltage range from S to the high potential side power supply voltage VDD is widened, and stable results can be obtained within this range.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

In this embodiment, a switch circuit 5 is provided, and this switch circuit 5 allows the common mode input voltages V1, 4 and the reference voltage vhE to
p is selected and the level of these voltages is set to an intermediate voltage V,
When the level of these voltages is around the intermediate voltage 7M, a through current flows through the comparator 21 of the level detection circuit 2, increasing the current consumption.In this case, by switching these voltages, , there is an advantage that it is possible to prevent an increase in current consumption.

〔Effect of the invention〕

As explained above, the present invention has a configuration in which two comparators with different effective input voltage ranges are provided and the output voltages of these comparators are switched according to the level of the input voltage.
This has the effect of expanding the effective input voltage range to the full extent of the power supply voltage range.

Child, TREE...Reference voltage input terminal.

Claims (1)

[Claims] Provided between the power supply terminals on the low potential side and high potential side,
A first input terminal is connected to a common-mode voltage input terminal that inputs a common-mode input voltage that is in phase with the first output voltage, and a second input terminal is connected to a reference voltage that is in reverse phase with respect to the first output voltage. has a valid input voltage range between the low potential side power supply voltage and the effective upper limit input voltage with respect to the common-mode input voltage and the reference voltage, and connects the common-mode input voltage to the reference voltage input terminal. A first comparator of CMOS type that outputs the first output voltage by comparing the first output voltage with the first output voltage, and a first comparator that is provided between the power supply terminals on the low potential side and the high potential side, and connects the first input terminal to the second output voltage. The reference is connected to the common-mode voltage input terminal that inputs the common-mode input voltage that is in phase with the voltage, and the second input terminal is connected to the reference voltage that inputs the reference voltage that is in reverse phase with respect to the second output voltage. is connected to a voltage input terminal, has a valid input voltage range between a high potential side power supply voltage and an effective lower limit input voltage with respect to the common mode input voltage and a reference voltage, and compares the common mode input voltage with the reference voltage. a CMOS type second comparator that outputs the second output voltage; and when the common mode input voltage is lower than an intermediate voltage between the effective upper limit input voltage and the effective lower limit input voltage, the voltage becomes a first level and is high. a level detection circuit that outputs a detection signal that sometimes becomes a second level; and a level detection circuit that outputs a detection signal that is at a second level at times, and a
and a switching circuit that outputs a second output voltage when the output voltage is at a second level.