JPH02271658A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent characteristics of a title device as a protective diode from being varied owing to variations in distance and withstand voltage from being varied by specifying a difference between the shortest distance between a short side of a high concentration N-type semiconductor region and the boundary of an N-type region and the shortest distance between a long side of said region and the boundary of the N type region. CONSTITUTION:A shortest distance L between a short side of a high concentration N type region 21 is defined and formed so as to be longer corresponding to the maximum of a positional displacement due to at least production variations compared with a shortest distance Ly between a long side of said region 22 and the boundary of the N-type region 21. With a title semiconductor device arranged as such, the shortest distance Ly between the long side of the high concentration N-type semiconductor region 22 and the boundary of the N-type region 21 is more shortened than the shortest distance Lx on the short side at all times even through there is produced variations of manufacture such as mask displacement and pattern shifting and the like. Accordingly, resistance on the long side is reduced to facilitate production of a surge current. Hereby, diode action and surge absorption are securely be achieved to prevent withstand voltage to static electricity and instability from being varied.

Description

Detailed Description of the Invention (Industrial Field of Application) The present invention relates to a semiconductor device such as a bipolar type semiconductor device having a protection diode for protecting an internal circuit against surge input. The present invention relates to a semiconductor pattern of a semiconductor formed by epitaxial growth or the like.

(Conventional Technology) Conventionally, as a technology in this field, solid state technology (solid state technology) has been used.
Pattern shift and pattern distortion in CVD epitaxy on silicon (JP, 61-68) .

Conventionally, bipolar and other semiconductor devices have pad parts (
Some devices are equipped with a protection diode (electrode) to protect the internal circuit from surge input. Examples thereof are shown in FIGS. 2 to 4.

FIG. 2 is a circuit diagram of a protection diode provided in a conventional semiconductor device, FIG. 3 is a pattern diagram thereof, and FIG. 4 is a sectional view of FIG. 3.

As shown in FIG. 2, the input and output pads 1 provided in the semiconductor device are connected to the internal circuit and to the N+ side electrode of a protection diode 10, and the P+ side electrode of the protection diode 10 is connected to the internal circuit. Connected to ground potential VSS.

In FIGS. 3 and 4 showing an example of the structure of the pad 1 and the protection diode 10, an N- type region 10a is formed on a P+ type semiconductor substrate 9 by epitaxial growth. A highly doped N+ type semiconductor region (floating collector) 1 having a substantially rectangular planar shape is provided on the bottom surface of the N− type region 10a.
0b is formed, and an N+ type contact diffusion layer 10C is formed above it. The N- type region 10a is P+
It is isolated from other element regions by a mold isolation region 10d. These P+ type semiconductor substrates 9, N
- type region 10a, high concentration N+ type semiconductor region N+, contact diffusion N10c and isolation region 10d
Thus, a protection diode 10 is formed.

A connecting metal layer 12 is formed on the P+ type semiconductor substrate 9 via an insulating layer 11, and the metal layer is connected to the contact diffusion layer 10C via a contact hole 13. Further, a part of the metal layer 12 has a passivation portion 1
A pad 1 is formed at a.

That is, the pad 1 and the N+ side electrode of the protection diode 10 are formed in the same isolation area surrounded by the isolation region 10d. Note that the same effect can be obtained even if the N'' side electrode of the protection diode 10 is formed in an isolation area separate from the pad 1.
In terms of space, there is a disadvantage that the pattern becomes larger due to the isolation area.

Next, the operation will be explained.

The P+ type semiconductor substrate 9 and the isolation region 10d are at the ground potential ■SS, and let us consider a case in which a negative surge is applied to the pad 1 with respect to this ground potential VSS.
In this case, P+ type semiconductor substrate 9-high concentration N+ type semiconductor region 10b=N- type region 10a-contact diffusion layer 10C
→ Pad 1, the ground potential ■SS is P
A current flows from the +-type semiconductor substrate 9 toward the pad 1, and the potential level of the pad 1 is clamped by a protection diode 10 to protect the internal circuit.

Conversely, consider a case where a voltage higher than the power supply for the semiconductor device is applied to pad 1. If the internal circuit connected to pad 1 is provided with a diode (not shown) pointing toward the power supply (a diode with a P+ electrode on the top of the pad and an N+ electrode on the power supply side), current will flow through that diode. When a clamp is applied and such a guide is not provided, such as in the case of CIVTO8 (complementary MO8) input, the protection diode 10 formed on the pad 1 part is
breaks down and causes a current to flow in the direction of the ground potential VSS, protecting the internal circuit.

In this way, the contact diffusion layer 10c, the heavily doped N+ type semiconductor region 10b, and the like have a function of protecting the internal circuit against surge input.

(Problems to be Solved by the Invention) However, the semiconductor device having the above configuration has the following problems.

In the epitaxial growth process of the N- type region LOa, as described in the above-mentioned literature, the position of the highly doped N+-type semiconductor region 10b is shifted due to pattern shift (displacement in the lateral direction of the centroid of the surface shape). The amount varies depending on whether the amount is large or small, and the distance between the high concentration N+ type semiconductor region 10b and the isolation region 10d varies.

In addition, variations in the distance occur due to mask misalignment during mask alignment during the formation of the high concentration N+ type semiconductor region 10b and the like. When such variations occur,
The characteristics (resistance component and breakdown voltage) of the protection diode 10 in the pad 1 portion vary, and the electrostatic protection function of the protection diode 10 varies.

Therefore, even if a plurality of identical protection diodes 10 are patterned and laid out on the same P+ type semiconductor substrate 9,
There are problems in that the electrostatic capacity differs depending on the pad 1 connected to each protection diode 10, and that the electrostatic capacity varies during mass production. Furthermore, when such variations occur, the Electronic Industries Association of Japan (EIAJ) standard (capacitance C =
There was also a problem that some pads 1 did not satisfy (200 pF, resistance R = 0 Ω, voltage 200 μ or more).

In addition, in severe cases, the high concentration N+ type semiconductor region 10b
Concentration of the electric field due to the flow of current from the sides of, e.g.
In FIG. 3, the upper short side of the deep N+ type semiconductor region 10b and the isolation region 10d opposite thereto.
In some cases, a destroyed area may occur between the two.

The present invention solves the problem that the conventional technology had, because the distance between the highly doped N+ type semiconductor region 10b and the isolation region 10d fluctuates due to mass production variations and pad positions, and the characteristics as a protection diode vary accordingly. The object of the present invention is to provide a semiconductor device that solves the problem that the electrostatic capacity changes due to changes in electrostatic capacity.

(Means for Solving the Problem) In order to solve the problem, a first invention provides a P-type semiconductor substrate, an N-type region formed in the P-type semiconductor substrate,
a highly doped N-type semiconductor region formed at the bottom of the N-type region and having a substantially rectangular planar shape with long sides and short sides; a contact region formed on the high-concentration N-type semiconductor region;
In the semiconductor device, the high concentration N-type semiconductor region includes a connecting metal layer formed on the P-type semiconductor substrate via an insulating layer and connected to the N-type region via the contact region. The shortest distance between the short side and the boundary of the N-type region is longer than the shortest distance between the long side and the boundary of the N-type region by at least the maximum value of positional deviation due to manufacturing variations. It is something.

In a second invention, the N-type region of the first invention is formed by an N-type epitaxial growth layer that is grown on the P-type semiconductor substrate.

In a third invention, the contact region of the first invention is formed into a substantially rectangular shape having a long side along the long side of the heavily doped N-type semiconductor region and a short side along the short side.

In a fourth invention, the high concentration N-type semiconductor region of the second invention is provided with a long side parallel to the pattern shift direction of the epitaxial growth layer.

(Function) According to the first invention, since the semiconductor device is configured as described above, the shortest distance between the long side of the highly doped N-type semiconductor region and the boundary of the N-type region is determined by mask misalignment and pattern. Even if manufacturing variations such as shifts occur, the distance will always be shorter than the shortest distance on the short side, reducing the resistance value on the long side and making it easier for surge current to flow. Moreover, the long sides of this high concentration N-type semiconductor region have the function of enlarging the flow path of surge current, reducing the electrolytic density caused by the surge current, and preventing damage from occurring.

The N-type epitaxial growth layer of the second invention facilitates the formation of the N-type region. The contact area of the third invention is
It has the function of alleviating the electric field concentration of the surge current flowing between it and the highly doped N-type semiconductor region, thereby preventing the occurrence of damage. The highly doped N-type semiconductor region of the fourth invention functions to eliminate resistance value fluctuations due to pattern shift between its long side and the boundary of the N-type region. With υC, the above problem can be solved.

(Embodiment) FIG. 1 shows an embodiment of the present invention, and is a pattern diagram of a semiconductor device having a protection diode.
The figure is a sectional view taken along line A-A.

Similar to the conventional semiconductor device, this semiconductor device is provided with a protection diode having a ground side P+ type electrode and a pad side N+ type electrode in the pad part, and the pad side N+ type electrode is placed in the same isolation area as the pad. is forming.

That is, an N- type region 21 is formed on a P+ type semiconductor substrate 20 by epitaxial growth or a method of growth. A heavily doped N+ type semiconductor region (floating collector) 22 having a substantially rectangular planar shape is buried in the bottom surface of the N- type region 21, and an N+ type contact diffusion layer 23 is formed above it. The contact 1 to the diffusion layer 23 have a substantially rectangular planar shape with a long side along the long side of the heavily doped N+ type semiconductor region 22 and a short side along the short side. The N- type region 21 is isolated from other element regions by a P+ type isolation region 24. These P+ semiconductor substrate 20, N- type region 2
1. High concentration N+ type semiconductor region 22, contact diffusion layer 2
3 and the isolation region 24 form a protection diode.

On the P+ type semiconductor substrate 20, an insulating layer 25 such as 3102 is formed.
Connecting metal layer 26 such as A1 and grounding metal N2 through
7 is formed. The connection metal layer 26 is connected to the contact diffusion layer 23 through a contact hole 28, and a portion of the connection metal layer 26 forms a pad 26a in the passivation section 29. The contact hole 28 and the contact diffusion layer 23 constitute a contact region. The grounding metal layer 27 is connected to the isolation region 24 via a contact hole 30.

As shown in FIG. 1, if the direction in which the highly doped N+ type semiconductor region 22 shifts due to manufacturing variations due to pattern shift is the X-axis direction, and the direction perpendicular thereto is the Y-axis direction, the highly doped N+ type semiconductor region 22 and the contact diffusion layer 23 are arranged and formed so that their long sides are in the X-axis direction.

Furthermore, the shortest distance between the short side of the highly doped N+ type semiconductor region 22 and the boundary of the N type region 21, that is, the distance between the highly doped N'' type semiconductor region 22 and the isolation region 24 in the X-axis direction is Lx, When Ly is the shortest distance between the long side of the high concentration N+ type semiconductor region 22 and the boundary of the N− type region 21, that is, the distance between the high concentration N+ type semiconductor region 22 and the isolation region 24 in the Y-axis direction. , Lx Ly>Δm...(1) However, Δm; Maximum one shift distance of mask shift or LX-Ly>Δm+Δn...(2) However, mn
; The high concentration N+ type semiconductor region 22 is arranged and formed under the condition that the pattern shift is the maximum value. When the N- type region 21 is formed using an epitaxially grown layer, the design is made so as to satisfy the equation (2), and when the N-type region 21 is formed using another layer, the equation (1) is satisfied. Further, the grounding metal layer 27 is connected to the isolation region 24 through a contact hole 30 formed on the isolation region 24 on the distance LX side.

In the above configuration, even if manufacturing variations occur due to mask misalignment or pattern shift during manufacturing, it is designed under conditions that satisfy the above formula (1) or (2).
Distance L in the y-axis direction in the high concentration N+ type semiconductor region 22
y can be made shorter than the distance LX in the X-axis direction.

Therefore, the resistance value Rx between the distances Lx becomes larger than the resistance value Ry between the distances MLy, and current flows more easily in the Y-axis direction.

Therefore, for example, when a negative surge is applied to the pad 26a, the surge absorption operation will surely occur in the Y-axis direction.
A surge current flows through the route of grounding metal layer 27 - isolation region 24 - high concentration N+ type semiconductor region 22 - N - type region 21 - contact diffusion layer 23 - pad 26a, and is connected to connection metal layer 26. Protects internal circuitry (not shown).

This embodiment has the following advantages.

(a> Since the grounding metal layer 27 is connected to the isolation region 24 in the Y-axis direction, the potential increase in the isolation region 24 due to the sheet resistance of the isolation region 24 when a surge current flows is suppressed. This can be reliably prevented.

This is also effective in preventing latch-up due to a potential rise in the isolation region 24 during a protective operation (diode clamp) when a surge is applied.

(b) Since the long sides of the high concentration N+ type semiconductor region 22 and the contact diffusion layer 23 are arranged in the X-axis direction, the high concentration N+ type semiconductor region 23 and the contact diffusion layer 23 are arranged in the Y-axis direction. Compared to this, the opposing surface facing the isolation region 24 in the X-axis direction is larger. Since a surge current flows through this wide opposing surface and a diode operation is performed, the density of the electric field generated by the surge current becomes smaller. Therefore, it is possible to accurately prevent the problem that when a surge current flows, the electric field is concentrated in a narrow place and damage is likely to occur.

(c) When the N- type region 21 is formed of an epitaxially grown layer, the long side of the highly doped N+ type semiconductor region 22 is provided parallel to the pattern shift direction of the epitaxially grown layer, that is, the X-axis direction.

In this way, there is no variation in resistance value due to pattern shift within the distance Ly in the Y-axis direction, so that the electrostatic withstand voltage as designed can be obtained.

(d) As in (a) to (c) above, it becomes possible to determine the surface that always causes diode operation without depending on manufacturing variations due to mask misalignment or pattern shift;
By designing the pattern of a semiconductor device by taking into consideration the direction of manufacturing variations, it is possible to realize a semiconductor device having a stable and reliable protection diode.

FIG. 6 is a pattern diagram of a semiconductor device showing another embodiment of the present invention, and the same elements as those in FIG. 1 are given the same reference numerals.

The required withstand voltage of the pad 26a itself (for example, an input voltage range of 10V to 0) is within the isolation region 24-
When close to or in contact with the high concentration N+ type semiconductor region 22,
High concentration N+ type semiconductor region 22 and isolation region 2
4 (for example, 20 V), that is, it is sufficient to ensure that the voltage input is equal to or lower than the withstand voltage between the isolation region 24 and the high concentration N+ type semiconductor region 22 at the time of contact.

A pattern layout as shown in FIG. 6 may be used for the pad 26a.

In Figure 6, the X-axis direction is a high concentration N+ which forms a rectangle.
The high concentration N+ type semiconductor region 22 formed as a protective guide is set in the direction in which manufacturing variations in the type semiconductor region 22 occur.
If the distance between the short side facing the Y direction and the isolator 24 is LyLy2, and the distance between the long side facing the X direction and the Isolation controller 24 is Lxo, then Lx
The highly doped N" type semiconductor region 22 is arranged and formed so as to contact or cross the isolation region 24 so that o≦0 (μm).

Corresponding to this, the contact diffusion layer 23 is shaped like a rectangle.
The long side is arranged in the y-axis direction, and the short side is arranged in the x-axis direction. With this design, even if there are variations in the dimensions and placement position of the heavily doped N+ type semiconductor region 22 during manufacturing, the distances t, y1 . X for Ly2
The axial distance N L x □ can be shortened, and the diode can be reliably operated in the X-axis direction.

In this case as well, as in FIG.
Reliability can be further improved by connecting a grounding metal layer 27 for surge absorption to the isolation region 24 in the X-axis direction that is in contact with or crosses the type semiconductor region 22. .

Note that the present invention is not limited to the illustrated embodiment, and various modifications are possible. Examples of variations include the following.

(i) The connection metal layer 26 may be formed on the P+ type semiconductor substrate 20 other than on the N− type region 21.

The bonding pad 26a formed of the connection metal layer 26 may be another electrode such as a bump electrode.

(ii) The patterns shown in FIGS. 1 and 6 and the cross section shown in FIG. 5 can be modified into shapes, structures, layers arranged, etc. other than those shown.

(Effects of the Invention) As explained in detail above, according to the first invention, the distance between the high concentration N-type semiconductor region and the boundary of the N-type region is reduced due to manufacturing variations due to mask misalignment, pattern shift, etc. Even if there are variations, the diode operation and surge absorption operation can be performed reliably in the specified direction (plane).

Therefore, it is possible to prevent variations and instability in the electrostatic withstand capacity of the connection metal layer due to manufacturing variations. Furthermore, since the diode operating surface can be predicted, it is possible to accurately place and form the ground wiring for current absorption, which is expected to be effective in preventing latch-up caused by the rise in potential in the isolation region during surge absorption operation. can.

In the second invention, the manufacturing process is simplified. In the third invention, when a surge current flows between the heavily doped N+ type semiconductor region and the contact diffusion layer, the density of the electric field generated by the surge current is reduced, so damage caused by electric field concentration can be prevented.

In the fourth invention, since there is no variation in resistance value due to pattern shift between the highly doped N-type semiconductor region and the boundary between the N-type region, the electrostatic withstand voltage as designed can be obtained.

[Brief explanation of drawings]

Fig. 1 is a pattern diagram of a semiconductor device showing an embodiment of the present invention, Fig. 2 is a circuit diagram of a protection diode in a conventional semiconductor device, Fig. 3 is a pattern diagram of Fig. 2, and Fig. 4 is a pattern diagram of a conventional semiconductor device. 5 is a sectional view taken along line A--A in FIG. 1, and FIG. 6 is a pattern diagram of a semiconductor device showing another embodiment of the present invention. 20...P+ type semiconductor substrate, 21...
N- type region, 22...High concentration N+ type semiconductor region, 23... Contact diffusion layer, 24...
・Isolation region, 25...Insulating layer, 2
6...Metal layer for connection, 26a...Pad, 27...Metal layer for grounding.

Claims (1)

[Claims] 1. A P-type semiconductor substrate, an N-type region formed on the P-type semiconductor substrate, and a substantially rectangular planar shape formed at the bottom of the N-type region and having a long side and a short side. a highly doped N-type semiconductor region; a contact region formed on the highly doped N-type semiconductor region; and a contact region formed on the P-type semiconductor substrate via an insulating layer and connected to the N-type region via the contact region. In the semiconductor device, the high concentration N-type semiconductor region has a shortest distance between the short side and the boundary of the N-type region such that the shortest distance between the long side and the boundary of the N-type region is 1. A semiconductor device characterized in that the semiconductor device is formed to be longer than the shortest distance by at least the maximum value of positional deviation due to manufacturing variations. 2. The semiconductor device according to claim 1, wherein the N-type region is an N-type region grown on the P-type semiconductor substrate.
A semiconductor device formed using a type epitaxial growth layer. 3. The semiconductor device according to claim 1, wherein the contact region has a substantially rectangular shape having a long side along a long side of the high concentration N-type semiconductor region and a short side along a short side. 4. The semiconductor device according to claim 2, wherein the high concentration N-type semiconductor region has a long side parallel to a pattern shift direction of the epitaxial growth layer.